Datasheet AD7846KP, AD7846KN, AD7846JN, AD7846AQ, AD7846AP Datasheet (Analog Devices)

LC2MOS

a

FEATURES
16-Bit Monotonicity over Temperature
ⴞ2 LSBs Integral Linearity Error
Microprocessor Compatible with Readback Capability
Unipolar or Bipolar Output
Multiplying Capability
Low Power (100 mW Typical)

GENERAL DESCRIPTION

The AD7846 is a 16-bit DAC constructed with Analog Devices’

2

MOS process. It has V

LC
an on-chip output amplifier. These can be configured to give a
unipolar output range (0 V to +5 V, 0 V to +10 V) or bipolar
output ranges (±5 V, ±10 V).

The DAC uses a segmented architecture. The 4 MSBs in the
DAC latch select one of the segments in a 16-resistor string.
Both taps of the segment are buffered by amplifiers and fed to a
12-bit DAC, which provides a further 12 bits of resolution. This
architecture ensures 16-bit monotonicity. Excellent integral
linearity results from tight matching between the input offset
voltages of the two buffer amplifiers.

In addition to the excellent accuracy specifications, the AD7846
also offers a comprehensive microprocessor interface. There are
16 data I/O pins, plus control lines (CS, R/W, LDAC and CLR).
R/W and CS allow writing to and reading from the I/O latch.
This is the readback function which is useful in ATE applica­tions. LDAC allows simultaneous updating of DACs in a multi­DAC system and the CLR line will reset the contents of the
DAC latch to 00 . . . 000 or 10 . . . 000 depending on the state
of R/W. This means that the DAC output can be reset to 0 V in
both the unipolar and bipolar configurations.

The AD7846 is available in 28-lead plastic, ceramic, and PLCC
packages.

REF+

and V

reference inputs and

REF–

16-Bit Voltage Output DAC

AD7846

FUNCTIONAL BLOCK DIAGRAM

V

V

V

V

REF +

REF –

R

R

R

16

SEGMENT

SWITCH
MATRIX

4

A2

A1

V

SS

AD7846

12-BIT DAC

12

DAC LATCH

12

I/O LATCH

DB15 DB0

PRODUCT HIGHLIGHTS

1. 16-Bit Monotonicity
The guaranteed 16-bit monotonicity over temperature makes
the AD7846 ideal for closed-loop applications.

2. Readback
The ability to read back the DAC register contents minimizes
software routines when the AD7846 is used in ATE systems.

3. Power Dissipation
Power dissipation of 100 mW makes the AD7846 the lowest
power, high accuracy DAC on the market.

DD

CC

R

R

A3

CONTROL

LOGIC

DGND

R

IN

V

OUT

CS

R/ W

LDAC

CLR

REV. E

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 2000

(V

= +14.25 V to +15.75 V; VSS = –14.25 V to –15.75 V; VCC = +4.75 V to +5.25 V.

DD

V

AD7846–SPECIFICATIONS

loaded with 2 k⍀, 1000 pF to 0 V; V

OUT

1

specifications T

MIN

to T

MAX

, unless otherwise noted.)

= +5 V; RIN connected to 0 V. All

REF+

Parameter J, A Versions K, B Versions Unit Test Conditions/Comments

RESOLUTION 16 16 Bits

UNIPOLAR OUTPUT V

Relative Accuracy @ +25°C ±12 ±4 LSB typ 1 LSB = 153 µV

T

to T

MIN

Differential Nonlinearity Error ±1 ±0.5 LSB max All Grades Guaranteed Monotonic

MAX

±16 ±8 LSB max

Gain Error @ +25°C ±12 ±6 LSB typ V

T

to T

MIN

MIN

to T

2

2

MAX

MAX

Offset Error @ +25°C ±12 ±6 LSB typ

T
Gain TC
Offset TC

±16 ±16 LSB max

±16 ±16 LSB max
±1 ±1 ppm FSR/°C typ
±1 ±1 ppm FSR/°C typ

BIPOLAR OUTPUT V

Relative Accuracy @ +25°C ±6 ±2 LSB typ 1 LSB = 305 µV

T

to T

MIN

Differential Nonlinearity Error ±1 ±0.5 LSB max All Grades Guaranteed Monotonic

MAX

±8 ±4 LSB max

Gain Error @ +25°C ±6 ±4 LSB typ V

to T

T

MIN

MAX

±16 ±16 LSB max

Offset Error @ +25°C ±6 ±4 LSB typ V

T

MIN

to T

MAX

±16 ±12 LSB max

= 0 V, V

REF–

Load = 10 MΩ

OUT

= –5 V, V

REF–

Load = 10 MΩ

OUT

Load = 10 MΩ

OUT

= 0 V to +10 V

OUT

= –10 V to +10 V

OUT

Bipolar Zero Error @ +25°C ±6 ±4 LSB typ

T

to T

MIN

MAX

Gain TC
Offset TC

2

2

Bipolar Zero TC

2

±12 ±8 LSB max
±1 ±1 ppm FSR/°Ctyp
±1 ±1 ppm FSR/°Ctyp
±1 ±1 ppm FSR/°Ctyp

REFERENCE INPUT

Input Resistance 20 20 kΩ min Resistance from V

40 40 kΩ max Typically 30 kΩ

V

Range VSS + 6 to VSS + 6 to Volts

REF+

V

Range VSS + 6 to VSS + 6 to Volts

REF–

VDD – 6 VDD – 6

VDD – 6 VDD – 6

REF+

to V

REF –

OUTPUT CHARACTERISTICS

Output Voltage Swing VSS + 4 to VSS + 4 to V max

VDD – 3 VDD – 3

Resistive Load 2 2 kΩ min To 0 V
Capacitive Load 1000 1000 pF max To 0 V
Output Resistance 0.3 0.3 Ω typ
Short Circuit Current ±25 ±25 mA typ To 0 V or Any Power Supply

DIGITAL INPUTS

VIH (Input High Voltage) 2.4 2.4 V min
VIL (Input Low Voltage) 0.8 0.8 V max
IIN (Input Current) ±10 ± 10 µA max
CIN (Input Capacitance)

2

10 10 pF max

DIGITAL OUTPUTS

VOL (Output Low Voltage) 0.4 0.4 Volts max I
VOH (Output High Voltage) 4.0 4.0 Volts min I
Floating State Leakage Current ±10 ±10 µA max DB0–DB15 = 0 to V
Floating State Output Capacitance210 10 pF max

POWER REQUIREMENTS

V

DD

V

SS

V

CC

I

DD

I

SS

I

CC

Power Supply Sensitivity

3

+11.4/+15.75 +11.4/+15.75 V min/V max
–11.4/–15.75 –11.4/–15.75 V min/V max
+4.75/+5.25 +4.75/+5.25 V min/V max
5 5 mA max V
5 5 mA max V

4

1 1 mA max

1.5 1.5 LSB/V max

Power Dissipation 100 100 mW typ V

NOTES

1

Temperature ranges as follows: J, K Versions: 0°C to +70°C; A, B Versions: –40°C to +85°C

2

Guaranteed by design and characterization, not production tested.

3

The AD7846 is functional with power supplies of ± 12 V. See Typical Performance Curves.

4

Sensitivity of Gain Error, Offset Error and Bipolar Zero Error to VDD, VSS variations.

= 1.6 mA

SINK

SOURCE

Unloaded

OUT

Unloaded

OUT

Unloaded

OUT

= 400 µA

CC

Specifications subject to change without notice.

–2–

REV. E

AD7846

These characteristics are included for design guidance and are not
subject to test. (V

AC PERFORMANCE CHARACTERISTICS

to –15.75 V; VCC= +4.75 V to +5.25 V; RINconnected to 0 V.)

Limit at

to T

T

MIN

MAX

Parameter (All Versions) Unit Test Conditions/Comments

1

Output Settling Time

6 µs max To 0.006% FSR. V
9 µs max To 0.003% FSR. V

Slew Rate 7 V/µs typ

Digital-to-Analog Glitch

Impulse 70 nV-secs typ DAC alternately loaded with 10 . . . 0000 and

01 . . . 1111. V

AC Feedthrough 0.5 mV pk-pk typ V

REF–

DAC loaded with all 0s.

Digital Feedthrough 10 nV-secs typ DAC alternately loaded with all 1s and all 0s. CS High.

Output Noise Voltage

Density 1 kHz–100 kHz 50 nV/√Hz typ Measured at V

V

REF+

NOTES

1

LDAC = 0. Settling time does not include deglitching time of 2.5 µs (typ).

Specifications subject to change without notice.

(V

TIMING CHARACTERISTICS

Parameter Limit at T

t

1

t

2

t

3

t

4

t

5

t

6

t

7

0 ns min R/W to CS Setup Time
60 ns min CS Pulsewidth (Write Cycle)
0 ns min R/W to CS Hold Time
60 ns min Data Setup Time
0 ns min Data Hold Time
120 ns max Data Access Time
10 ns min Bus Relinquish Time

MIN

to T

= +14.25 V to +15.75 V; V

DD

(All Versions) Unit Test Conditions/Comments

MAX

= –14.25 V to –15.75 V; VCC = +4.75 V to +5.25 V)

SS

60 ns max

t

8

t

9

t

10

t

11

t

12

NOTES

1

Timing specifications are sample tested at +25°C to ensure compliance. All input control signals are specified with tR = tF = 5 ns (10% to 90% of +5 V) and timed
from a voltage level of 1.6 V.

2

t6 is measured with the load circuits of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.

3

t7 is defined as the time required for an output to change 0.5 V when loaded with the circuits of Figure 2.

Specifications subject to change without notice.

DBN

3k⍀

a. High Z to V

Figure 1. Load Circuits for Access Time (t6)

DBN

a. V

3k⍀

to High Z

OH

0 ns min CLR Setup Time
70 ns min CLR Pulsewidth
0 ns min CLR Hold Time
70 ns min LDAC Pulsewidth
130 ns min CS Pulsewidth (Read Cycle)

5V

3k⍀

100pF

DGND

5V

3k⍀

10pF

DGND

to High Z

OL

R/ W

OL

CS

DATA

CLR

LDAC

DGND

DGND

OH

100pF

DBN

b. High Z to V

DBN

10pF

b. V

= +5 V; VDD= +14.25 V to +15.75 V; VSS= –14.25 V

REF+

= 0 V, V

= V

REF–

t

1

t

8

loaded. V

OUT

loaded. V

OUT

unloaded.

OUT

= 1 V rms, 10 kHz sine wave.

REF+

. DAC loaded with 0111011 . . . 11.

OUT

= 0 V.

t

3

t

2

t

4

t

9

t

5

t

10

= 0 V. Typically 3.5 µs.

REF–

= –5 V. Typically 6.5 µs.

REF–

t

1

t

12

t

6

DATA VALIDDATA VALID

t

t

t

9

8

9

Figure 3. Timing DiagramFigure 2. Load Circuits for Bus Relinquish Time (t7)

t

3

t

7

t

10

t

11

5V

0V

5V

0V

5V

0V

5V

0V

5V

0V

REV. E

–3–

AD7846

ABSOLUTE MAXIMUM RATINGS

1

VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.4 V to +17 V

V

to DGND . . . . . . . . . . . . . . . –0.4 V, VDD + 0.4 V or +7 V

CC

(Whichever Is Lower)

to DGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.4 V to –17 V

V

SS

V

to DGND . . . . . . . . . . . . . . . . VDD + 0.4 V, VSS – 0.4 V

REF+

to DGND . . . . . . . . . . . . . . . . VDD + 0.4 V, VSS – 0.4 V

V

REF–

V

to DGND2 . . . . . . . . VDD + 0.4 V, VSS – 0.4 V or ±10 V

OUT

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one Absolute
Maximum Rating may be applied at any one time.

2

V

may be shorted to DGND, VDD, VSS, VCC provided that the power dissipation

OUT

of the package is not exceeded.

(Whichever Is Lower)

to DGND . . . . . . . . . . . . . . . . . . VDD + 0.4 V, VSS – 0.4 V

R

IN

Digital Input Voltage to DGND . . . . . . –0.4 V to V

Digital Output Voltage to DGND . . . . . –0.4 V to V

+ 0.4 V

CC

+ 0.4 V

CC

Power Dissipation (Any Package)

To +75°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 mW

Derates above +75°C . . . . . . . . . . . . . . . . . . . . . 10 mW/°C

Operating Temperature Range

J, K Versions . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C

A, B Versions . . . . . . . . . . . . . . . . . . . . . . . –25°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering) . . . . . . . . . . . . . . . . . . +300°C

ORDERING GUIDE

Model Temperature Range Relative Accuracy Package Description Package Options

AD7846JN 0°C to +70°C ±16 LSB Plastic DIP N-28A
AD7846KN 0°C to +70°C ±8 LSB Plastic DIP N-28A
AD7846JP 0°C to +70°C ±16 LSB Plastic Leaded Chip Carrier (PLCC) P-28A
AD7846KP 0°C to +70°C ±8 LSB Plastic Leaded Chip Carrier (PLCC) P-28A
AD7846AP –40°C to +85°C ± 16 LSB Plastic Leaded Chip Carrier (PLCC) P-28A
AD7846AQ –40°C to +85°C ±16 LSB Ceramic DIP Q-28
AD7846BP –40°C to +85°C ±8 LSB Plastic Leaded Chip Carrier (PLCC) P-28A

CAUTION

ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected;
however, permanent damage may occur on unconnected devices subject to high energy electro­static fields. Unused devices must be stored in conductive foam or shunts. The protective foam
should be discharged to the destination socket before devices are removed.

TERMINOLOGY
LEAST SIGNIFICANT BIT

This is the analog weighting of 1 bit of the digital word in a DAC.
For the AD7846, 1 LSB = (V

REF+–VREF–

)/216.

Relative Accuracy

Relative accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the end­points of the DAC transfer function. It is measured after adjust­ing for both endpoints (i.e., offset and gain errors are adjusted
out) and is normally expressed in least significant bits or as a
percentage of full-scale range.

Differential Nonlinearity

Differential nonlinearity is the difference between the measured
change and the ideal change between any two adjacent codes. A
specified differential nonlinearity of ±1 LSB over the operating
temperature range ensures monotonicity.

Gain Error

Gain error is a measure of the output error between an ideal
DAC and the actual device output with all 1s loaded after offset
error has been adjusted out. Gain error is adjustable to zero
with an external potentiometer.

Offset Error

This is the error present at the device output with all 0s loaded
in the DAC. It is due to op amp input offset voltage and bias
current and the DAC leakage current.

Bipolar Zero Error

When the AD7846 is connected for bipolar output and 10 . . . 000
is loaded to the DAC, the deviation of the analog output from the
ideal midscale of 0 V is called the bipolar zero error.

Digital-to-Analog Glitch Impulse

This is the amount of charge injected from the digital inputs to
the analog output when the inputs change state. This is normally
specified as the area of the glitch in either pA-secs or nV-secs
depending upon whether the glitch is measured as a current or a
voltage.

Multiplying Feedthrough Error

This is an ac error due to capacitive feedthrough from either of
the V

terminals to V

REF

when the DAC is loaded with all 0s.

OUT

Digital Feedthrough

When the DAC is not selected (i.e., CS is held high), high fre­quency logic activity on the digital inputs is capacitively coupled
through the device to show up as noise on the V
noise is digital feedthrough.

–4–

WARNING!

ESD SENSITIVE DEVICE

pin. This

OUT

REV. E

AD7846

PIN CONFIGURATIONS

DIP

DB2

1

DB1

2

DB0

3

V

4

DD

V

5

OUT

R

6

IN

SS

AD7846

7

TOP VIEW

(Not to Scale)

8

9

10

11

12

13

14

V

REF+

V

REF–

DB15

DB14

DB13

DB12

DB11

V

PLCC

DD

V

DB0

DB1

DB2

V

V

REF+

V

REF–

DB15

DB14

4 3 2 1 28 27 26

5

OUT

6

R

IN

7

8

9

V

SS

10

11

12 13 14 15 16 17 18

DB13

DB12

PIN 1
IDENTIFIER

AD7846

TOP VIEW

(Not to Scale)

DB11

DB10

DB3

DB9

28

27

26

25

24

23

22

21

20

19

18

17

16

15

DB4

DB8

DB3

DB4

DB5

LDAC

CLR

CS

R/W

V

CC

DGND

DB6

DB7

DB8

DB9

DB10

DB5

DB7

25

24

23

22

21

20

19

LDAC
CLR
CS

R/W

V

CC

DGND

DB6

PIN FUNCTION DESCRIPTION

Pin Mnemonic Description

1–3 DB2–DB0 Data I/O pins. DB0 is LSB.

4V

DD

Positive supply for analog circuitry. This is
+15 V nominal.

5V

6R

OUT

IN

DAC output voltage pin.

Input to summing resistor of DAC output
amplifier. This is used to select output
voltage ranges. See Table I.

7V

REF+

V

Input. The DAC is specified for V

REF+

REF+

= +5 V.

8V

REF–

V

Input. For unipolar operation con-

REF–

nect V

to 0 V and for bipolar operation

REF–

connect it to –5 V. The device is specified
for both conditions.

9V

SS

Negative supply for the analog circuitry.
This is –15 V nominal.

10–19 DB15–DB6 Data I/O pins. DB15 is MSB.

20 DGND Ground pin for digital circuitry.

21 V

CC

Positive supply for digital circuitry. This is
+5 V nominal.

22 R/W R/W input. This can be used to load data to

the DAC or to read back the DAC latch
contents.

23 CS Chip select input. This selects the device.
24 CLR Clear input. The DAC can be cleared to

000 . . . 000 or 100 . . . 000. See Table II.

25 LDAC Asynchronous load input to DAC.

26–28 DB5–DB3 Data I/O pins.

Table I. Output Voltage Ranges

Output Range V

REF+

0 V to +5 V +5 V 0 V V

V

REF–

R

IN

OUT

0 V to +10 V +5 V 0 V 0 V
+5 V to –5 V +5 V –5 V V

OUT

+5 V to –5 V +5 V 0 V +5 V
+10 V to –10 V +5 V –5 V 0 V

REV. E

–5–

AD7846–Typical Performance Curves

Figure 4. AC Feedthrough. V
1 V rms, 10 kHz Sine Wave

500

V

= V

REF–

= 0V

REF+

GAIN = +1
DAC LOADED WITH ALL 1s

400

300

200

REF+

=

8

VDD = +15V
VSS = –15V
V

= +1Vrms

REF+

6

V

= 0V

REF–

4

– mV p-p

OUT

V

2

0

2

10

3

10

4

10

FREQUENCY – Hz

5

10

Figure 5. AC Feedthrough vs.

Frequency

V

OUT

50mV/DIV

30

VDD = +15V
VSS = –15V

= ⴞ5V SINE WAVE

V

REF+

V

= 0V

REF–

GAIN = +2

20

– V p-p

OUT

V

10

0

6

10

1102103104105106107

10

FREQUENCY – Hz

Figure 6. Large Signal Frequency
Response

V

OUT

LDAC

50mV/DIV

5V/DIV

100

NOISE SPECTRAL DENSITY – nV/冪Hz

0

2

10

3

10

10

FREQUENCY – Hz

4

5

10

Figure 7. Noise Spectral Density

Figure 10. Pulse Response
(Large Signal)

5V/DIVDATA

6

10

Figure 8. Digital-to-Analog Glitch
Impulse Without Internal Deglitcher
(10 . . . 000 to 011 . . . 111 Transition)

Figure 11. Pulse Response
(Small Signal)

0.5␮s/DIV

Figure 9. Digital-to-Analog Glitch
Impulse With Internal Deglitcher
(10 . . . 000 to 011 . . . 111 Transition)

Figure 12. Spectral Response of
Digitally Constructed Sine Wave

1␮s/DIV

5V/DIVDATA

–6–

REV. E

AD7846

4.0

3.5

3.0

2.5

2.0

INL – LSBs

1.5

1.0

0.5
11

12 13 14 15

VDD/VSS – Volts

Figure 13. Typical Linearity vs. VDD/V

TA = +25ⴗC

= +5V

V

REF+

V

= 0V

REF–

GAIN = +1

16

SS

CIRCUIT DESCRIPTION
Digital Section

Figure 15 shows the digital control logic and on-chip data
latches in the AD7846. Table II is the associated truth table.
The D/A converter has two latches that are controlled by four
signals: CS, R/W, LDAC and CLR. The input latch is con­nected to the data bus (DB15–DB0). A word is written to the
input latch by bringing CS low and R/W low. The contents of
the input latch may be read back by bringing CS low and R/W
high. This feature is called “readback” and is used in system
diagnostic and calibration routines.

Data is transferred from the input latch to the DAC latch with
the LDAC strobe. The equivalent analog value of the DAC
latch contents appears at the DAC output. The CLR pin resets
the DAC latch contents to 000 . . . 000 or 100 . . . 000, depend­ing on the state of R/W. Writing a CLR loads 000 . . . 000 and
reading a CLR loads 100 . . . 000. To reset a DAC to 0 V in a
unipolar system the user should exercise CLR while R/W is low;
to reset to 0 V in a bipolar system exercise the CLR while R/W
is high.

R/W
CLR

DAC

16

CS

DB15 RST

DB15 SET
DB14–DB0

RST

3-STATE I/O

DB15 DB0

DB15–DB0

LATCHES

16

LATCH

16

LDAC

Figure 15. Input Control Logic

REV. E

–7–

1.0

0.8

0.6

0.4

DNL – LSBs

0.2

0

11

12 13 14 15

VDD/VSS – Volts

TA = +25ⴗC
V

= +5V

REF+

V

= 0V

REF–

GAIN = +1

16

Figure 14. Typical Monotonicity vs.
V

DD/VSS

Table II. Control Logic Truth Table

CS R/W LDAC CLR Function

1 X X X 3-State DAC I/O Latch in High-

Z State

0 0 X X DAC I/O Latch Loaded with

DB15–DB0

0 1 X X Contents of DAC I/O Latch

Available on DB15–DB0

X X 0 1 Contents of DAC I/O Latch

Transferred to DAC Latch

X 0 X 0 DAC Latch Loaded with

000 . . . 000

X 1 X 0 DAC Latch Loaded with

100 . . . 000

D/A Conversion

Figure 16 shows the D/A section of the AD7846. There are
three DACs, each of which have their own buffer amplifiers.
DAC1 and DAC2 are 4-bit DACs. They share a 16-resistor
string but have their own analog multiplexers. The voltage refer­ence is applied to the resistor string. DAC3 is a 12-bit voltage
mode DAC with its own output stage.

The 4 MSBs of the 16-bit digital code drive DAC1 and DAC2
while the 12 LSBs control DAC3. Using DAC1 and DAC2, the
MSBs select a pair of adjacent nodes on the resistor string and
present that voltage to the positive and negative inputs of
DAC3. This DAC interpolates between these two voltages to
produce the analog output voltage.

To prevent nonmonotonicity in the DAC due to amplifier offset
voltages, DAC1 and DAC2 “leap-frog” along the resistor string.
For example, when switching from Segment 1 to Segment 2,
DAC1 switches from the bottom of Segment 1 to the top of
Segment 2 while DAC2 stays connected to the top of Segment

1. The code driving DAC3 is automatically complemented to
compensate for the inversion of its inputs. This means that any
linearity effects due to amplifier offset voltages remain un­changed when switching from one segment to the next and
16-bit monotonicity is ensured if DAC3 is monotonic. So,
12-bit resistor matching in DAC3 guarantees overall 16-bit
monotonicity. This is much more achievable than the 16-bit
matching which a conventional R-2R structure would have
needed.

AD7846

V

REF+

SEGMENT 16

V

DAC1

S1

S3

S15

S17

DB15–DB12 DB15–DB12

SEGMENT 1

REF–

DAC2

S2

S4

S14

S16

Figure 16. D/A Conversion

Output Stage

The output stage of the AD7846 is shown in Figure 17. It is
capable of driving a 2 kΩ/1000 pF load. It also has a resistor
feedback network which allows the user to configure it for gains
of one or two. Table I shows the different output ranges that are
possible.

An additional feature is that the output buffer is configured as a
track-and-hold amplifier. Although normally tracking its input,
this amplifier is placed in a hold mode for approximately 2.5 µs
after the leading edge of LDAC. This short state keeps the DAC
output at its previous voltage while the AD7846 is internally
changing to its new value. So, any glitches that occur in the
transition are not seen at the output. In systems where the
LDAC is tied permanently low, the deglitching will not be in
operation. Figures 8 and 9 show the outputs of the AD7846
without and with the deglitcher.

R

IN

10k⍀

DAC3

ONE

SHOT

LDAC

10k⍀

C1

V

OUT

Figure 17. Output Stage

UNIPOLAR BINARY OPERATION

Figure 18 shows the AD7846 in the unipolar binary circuit
configuration. The DAC is driven by the AD586, +5 V refer­ence. Since R

is tied to 0 V, the output amplifier has a gain of

IN

2 and the output range is 0 V to +10 V. If a 0 V to +5 V range is
required, R

should be tied to V

IN

, configuring the output

OUT

stage for a gain of 1. Table III gives the code table for the circuit
of Figure 18.

1␮F

R

A3

V

V

R

+15V

V

REF+

REF–

DAC3

A1

12 BIT DAC

A2

C1

AD586

SIGNAL

GROUND

DB11–DB0

R1
10k⍀

*ADDITIONAL PINS
OMITTED FOR CLARITY

4

DD

AD7846*

V

SS

–15V

R

IN

V

OUT

+5V

V

CC

V

OUT

R

DGND

IN

V

OUT

(0V TO +10V)

Figure 18. Unipolar Binary Operation

Table III. Code Table for Figure 18

Binary Number Analog Output
in DAC Latch (V

OUT

)

MSB LSB
1111 1111 1111 1111 +10 (65535/65536) V
1000 0000 0000 0000 +10 (32768/65536) V
0000 0000 0000 0001 +10 (1/65536) V
0000 0000 0000 0000 0

NOTE
1 LSB = 10 V/216 = 10 V/65536 = 152 µV.

Offset and gain may be adjusted in Figure 18 as follows: To
adjust offset, disconnect the V
DAC with all 0s and adjust the V

input from 0 V, load the

REF–

voltage until V

REF–

OUT

= 0 V.
For gain adjustment, the AD7846 should be loaded with all 1s
and R1 adjusted until V
If a simple resistor divider is used to vary the V

= 10 (65535)/(65536) = 9.999847 V.

OUT

voltage, it is

REF–

important that the temperature coefficients of these resistors
match that of the DAC input resistance (–300 ppm/°C). Other­wise, extra offset errors will be introduced over temperature.
Many circuits will not require these offset and gain adjustments.
In these circuits, R1 can be omitted. Pin 5 of the AD586 may be
left open circuit and Pin 8 (V

) of the AD7846 tied to 0 V.

REF–

–8–

REV. E

AD7846

BIPOLAR OPERATION

Figure 19 shows the AD7846 set up for ±10 V bipolar opera­tion. The AD588 provides precision ±5 V tracking outputs
which are fed to the V

REF+

and V

inputs of the AD7846.

REF–

The code table for Figure 19 is shown in Table IV.

+15V

–15V

+15V

4

V

DD

V

REF+

AD7846*

V

REF–

V

–15V

+5V

V

DGND

SS

CC

V

OUT

R

V
(–10V TO +10V)

IN

SIGNAL
GROUND

*ADDITIONAL PINS
OMITTED FOR CLARITY

OUT

10k⍀

+15V

R1
39k⍀

C1

1␮F

R2

R3

100k⍀

AD588

Figure 19. Bipolar ±10 V Operation

Table IV. Offset Binary Code Table for Figure 19

Binary Number Analog Output
in DAC Latch (V

OUT

)

MSB LSB
1111 1111 1111 1111 +10 (32767/32768) V
1000 0000 0000 0001 +10 (1/32768) V
1000 0000 0000 0000 0 V
0111 1111 1111 1111 –10 (1/32768) V
0000 0000 0000 0000 –10 (32768/32768) V

NOTE
1 LSB = 10 V/215 = 10 V/32768 = 305 µV.

Full scale and bipolar zero adjustment are provided by varying
the gain and balance on the AD588. R2 varies the gain on the
AD588 while R3 adjusts the +5 V and –5 V outputs together
with respect to ground.

For bipolar zero adjustment on the AD7846, load the DAC with
100 . . . 000 and adjust R3 until V

= 0 V. Full scale is ad-

OUT

justed by loading the DAC with all 1s and adjusting R2 until

= 9.999694 V.

V

OUT

When bipolar zero and full scale adjustment are not needed, R2
and R3 can be omitted, Pin 12 on the AD588 should be con­nected to Pin 11 and Pin 5 should be left floating. If a user
wants a +5 V output range, there are two choices. By tying Pin
6 (R

) of the AD7846 to V

IN

(Pin 5), the output stage gain is

OUT

reduced to unity and the output range is ±5 V. If only a positive
+5 V reference is available, bipolar ±5 V operation is still pos­sible. Tie V

to 0 V and connect RIN to V

REF–

. This will also

REF+

give a ±5 V output range. However, the linearity, gain, and
offset error specifications will be the same as the unipolar 0 V to
+5 V range.

Other Output Voltage Ranges

In some cases, users may require output voltage ranges other
than those already mentioned. One example is systems which
need the output voltage to be a whole number of millivolts (i.e.,
1 mV, 2 mV, etc.). If the AD689 (8.192 V reference) is used
with the AD7846 as in Figure 20, then the LSB size is 125 µV.
This makes it possible to program whole millivolt values at the
Output. Table V shows the code table for Figure 20.

AD689

SIGNAL GROUND

*ADDITIONAL PINS
OMITTED FOR CLARITY

V

V

+15V

REF+

REF–

V

DD

AD7846*

V

–15V

+5V

V

CC

V

OUT

R

IN

DGND

SS

V

OUT

(0V TO 8.192V)

Figure 20. Unipolar Output with AD689

Table V. Code Table for Figure 20

Binary Number Analog Output
in DAC Latch (V

OUT

)

MSB LSB
1111 1111 1111 1111 8.192 V (65535/65536) = 8.1919 V
1000 0000 0000 0000 8.192 V (32768/65536) = 4.096 V
0000 0000 0000 1000 8.192 V (8/65536) = 0.001 V
0000 0000 0000 0100 8.192 V (4/65536) = 0.0005 V
0000 0000 0000 0010 8.192 V (2/65536) = 0.00025 V
0000 0000 0000 0001 8.192 V (1/65536) = 0.000125 V

NOTE
1 LSB = 8.192 V/2l6 = 125 µV.

Multiplying Operation

The AD7846 is a full multiplying DAC. To get four-quadrant
multiplication, tie V
tie R

IN

to V

. Figure 6 shows the Large Signal Frequency

REF+

to 0 V, apply the ac input to V

REF–

REF+

and

Response when the DAC is used in this fashion.

REV. E

–9–

AD7846

TEST APPLICATION

Figure 21 shows the AD7846 in an Automatic Test Equipment
application. The readback feature of the AD7846 is very useful
in these systems. It allows the designer to eliminate phantom
memory used for storing DAC contents and increases system
reliability since the phantom memory is now effectively on chip
with the DAC. The readback feature is used in the following
manner to control a data transfer. First, write the desired 16-bit
word to the DAC input latch using the CS and R/W inputs.
Verify that correct data has been received by reading back the
latch contents. Now, the data transfer can be completed by
bringing the asynchronous LDAC control line low. The analog
equivalent of the digital word now appears at the DAC output.
In Figure 21, each pin on the Device Under Test can be an

V

H

INH

INH

V

D

D

L

AD9687

AD7846

V

REF+

V

REF–

STORED DATA

AND INHIBIT

PATTERN

PERIOD

GENERATION

AND DELAY

COMPARE DATA

AND DON'T
CARE DATA

+15V

R1
39k⍀

AD588

FORMATTER

COMPARE
REGISTER

DAC1

AD7846

V

OUT

V

REF+

R

V

REF–

DGND

DB0DB15

IN

input or output. The AD345 is the pin driver for the digital
inputs, and the AD9687 is the receiver for the digital outputs.
The digital control circuitry determines the signal timing and
format.

DACs 1 and 2 set the pin driver voltage levels (V

and VL), and

H

DACs 3 and 4 set the receiver voltage levels. The pin drivers
used in ATE systems normally have a nonlinearity between
input and output. The 16-bit resolution of the AD7846 allows
compensation for these input/output nonlinearities. The dc
parametrics shown in Figure 21 measure the voltage at the
device pin and feed this back to the system processor. The pin
voltage can thus be fine-tuned by incrementing or decrementing
DACs 1 and 2 under system processor control.

DC PARAMETRICS

OUT

R

DUT

DAC4

AD7846

V

OUT

V

REF+

IN

V

REF–

R

DGND

DB0DB15

IN

AD345

DAC2

V

DGND

DB0DB15

OUT

R

DAC3

AD7846

V

V

REF+

IN

V

REF–

DGND

DB0DB15

–15V

Figure 21. Digital Test System with 16-Bit Performance

–10–

REV. E

AD7846

POSITION MEASUREMENT APPLICATION

Figure 22 shows the AD7846 in a position measurement appli­cation using an LVDT (Linear Variable Displacement Trans­ducer), an AD630 synchronous demodulator and a comparator
to make a 16-bit LVDT-to-Digital Converter. The LVDT is
excited with a fixed frequency and fixed amplitude sine wave
(usually 2.5 kHz, 2 V pk-pk). The outputs of the secondary coil
are in antiphase and their relative amplitudes depend on the
position of the core in the LVDT. The AD7846 output interpo­lates between these two inputs in response to the DAC input
code. The AD630 is set up so that it rectifies the DAC output
signal. Thus, if the output of the DAC is in phase with the

input, the inverting input to the comparator will be posi-

V

REF+

tive, and if it is in phase with V

the output will be negative.

REF–,

By turning on each bit of the DAC in succession starting with
the MSB, and deciding to leave it on or turn it off based on the
comparator output, a 16-bit measurement of the core position is
obtained.

ASIN ␻ t

*ADDITIONAL PINS
OMITTED FOR CLARITY

LVDT

–(1–x)ASIN ␻ t

x ASIN ␻ t

R1

100k⍀

C1
1␮F

V

V

OUT

REF+

R

IN

AD7846*

V

REF–

DGND

DB0DB15

SIGNAL
GROUND

PROCESSOR DATA BUS

AD630*

TO
PROCESSOR PORT

Figure 22. AD7846 in Position Measurement Application

MICROPROCESSOR INTERFACING
AD7846-to-8086 Interface

Figure 23 shows the 8086 16-bit processor interfacing to the
AD7846. The double buffering feature of the DAC is not used
in this circuit since LDAC is permanently tied to 0 V. AD0–
AD15 (the 16-bit data bus) are connected to the DAC data bus
(DB0–DB15). The 16-bit word is written to the DAC in one
MOV instruction and the analog output responds immediately.
In this example, the DAC address is D000H.

ADDRESS BUS

ALE

8086

DEN

RD

WR

AD0–AD15

16-BIT

LATCH

DATA BUS

*LINEAR CIRCUITRY
OMITTED FOR CLARITY

ADDRESS

DECODE

+5V

CS

LDAC

CLR

AD7846*

R/W

DB0–DB15

In a multiple DAC system, the double buffering of the AD7846
allows the user to simultaneously update all DACs. In Figure
24, a 16-bit word is loaded to the input latches of each of the
DACs in sequence. Then, with one instruction to the appropri­ate address, CS4 (i.e., LDAC) is brought low, updating all the
DACs simultaneously.

ADDRESS BUS

ALE

8086

DEN

RD

WR

AD0–AD15

16-BIT

LATCH

DATA BUS

ADDRESS

DECODE

CS

AD7846*

LDAC

R/W

CLR

DB0–DB15

CS

+5V

AD7846*

LDAC

R/W

DB0–DB15

CS

CLR

+5V

AD7846*

LDAC

*LINEAR CIRCUITRY
OMITTED FOR CLARITY

R/W

DB0–DB15

CLR

+5V

Figure 24. AD7846-to-8086 Interface: Multiple DAC System

AD7846-to-MC68000 Interface

Interfacing between the AD7846 and MC68000 is accom­plished using the circuit of Figure 25. The following routine
writes data to the DAC latches and then outputs the data via the
DAC latch.

1000 MOVE.W #W, D0 The desired DAC data, W,

is loaded into Data Regis­ter 0. W may be any value
between 0 and 65535
(decimal) or 0 and FFFF
(hexadecimal).

MOVE.W D0, $E000 The data, W, is transferred

between D0 and the DAC
register.

MOVE.W #228, D7 Control is returned to the
TRAP #14 System Monitor using

these two instructions.

REV. E

Figure 23. AD7846-to-8086 Interface Circuit

–11–

AD7846

A1–A23

MC68000

DS

DTACK

ADDRESS BUS

ADDRESS

DECODE

+5V

CS
CLR
LDAC

AD7846*

R/W

D0–D15

DATA BUS

*LINEAR CIRCUITRY
OMITTED FOR CLARITY

R/W

DB0–DB15

Figure 25. AD7846-to-MC68000 Interface

DIGITAL FEEDTHROUGH

In the preceding interface configurations, most digital inputs to
the AD7846 are directly connected to the microprocessor bus.
Even when the device is not selected, these inputs will be con­stantly changing. The high frequency logic activity on the bus
can feed through the DAC package capacitance to show up as
noise on the analog output. To minimize this Digital Feed­through isolate the DAC from the noise source. Figure 26 shows
an interface circuit which isolates the DAC from the bus.

A1–A15

MICRO-

PROCESSOR

R/W

D0–D15

ADDRESS BUS

ADDRESS

DECODE

DATA BUS

*LINEAR CIRCUITRY
OMITTED FOR CLARITY

G

DIR

B BUS A BUS

2 ⴛ

74LS245

+5V

CS

CLR

LDAC

R/W

AD7846*

DB0–DB15

Figure 26. AD7846 Interface Circuit Using Latches to Mini­mize Digital Feedthrough

Note that to make use of the AD7846 readback feature using
the isolation technique of Figure 26, the latch needs to be
bidirectional.

APPLICATION HINTS
Noise

In high resolution systems, noise is often the limiting factor.
With a 10 volt span, a 16-bit LSB is 152 µV (–96 dB). Thus, the
noise floor must stay below –96 dB in the frequency range of
interest. Figure 7 shows the noise spectral density for the AD7846.

Grounding

As well as noise, the other prime consideration in high resolu­tion DAC systems is grounding. With an LSB size of 152 µV
and a load current of 5 mA, 1 LSB of error can be introduced
by series resistance of only 0.03 Ω.

Figure 27 below shows recommended grounding for the AD7846
in a typical application.

ANALOG SUPPLY

+15V 0V –15V +5V DGND

R1

SIGNAL

GROUND

R2

AD588*

R3

R5

*ADDITIONAL PINS
OMITTED FOR CLARITY

DIGITAL SUPPLY

AD7846*

R4

R

L

V

OUT

(+5V TO –5V)

Figure 27. AD7846 Grounding

R1 to R5 represent lead and track resistances on the printed
circuit board. R1 is the resistance between the Analog Power
Supply ground and the Signal Ground. Since current flowing in
R1 is very low (bias current of AD588 sense amplifier), the
effect of R1 is negligible. R2 and R3 represent track resistance
between the AD588 outputs and the AD7846 reference inputs.
Because of the Force and Sense outputs on the AD588, these
resistances will also have a negligible effect on accuracy.

R4 is the resistance between the DAC output and the load. If

is constant, then R4 will introduce a gain error only which

R

L

can be trimmed out in the calibration cycle. R5 is the resistance
between the load and the analog common. If the output voltage
is sensed across the load, R5 will introduce a further gain error
which can be trimmed out. If, on the other hand, the output
voltage is sensed at the analog supply common, R5 appears as
part of the load and therefore introduces no errors.

Printed Circuit Board Layout

Figure 28 shows the AD7846 in a typical application with the
AD588 reference, producing an output analog voltage in the
±10 volts range. Full scale and bipolar zero adjustment are
provided by potentiometers R2 and R3. Latches (2 × 74LS245)
isolate the DAC digital inputs from the active microprocessor
bus and minimize digital feedthrough.

The printed circuit board layout for Figure 28 is shown in Fig­ures 29 and 30. Figure 29 is the component side layout while
Figure 30 is the solder side layout. The component overlay is
shown in Figure 31.

In the layout, the general grounding guidelines given in Figure
27 are followed. The AD588 and AD7846 are as close as pos­sible, and the decoupling capacitors for these are also kept as
close to the device pins as possible.

–12–

REV. E

R2
100k⍀

100k⍀

C12

1␮F

R3

39k⍀

AD588

AD7846

+15V

C5

DB15

DB14

DB13

DB12

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

R/W

CS

CLR

10␮F

18

19

26

27

28

1

2

3

C1

10␮F

R1

C2

0.1␮F

V

REF+

AD7846

V

–15V

C4

0.1␮F

V

(+10V TO –10V)

OUT

C3
10␮F

REF–

V

SS

DGND

R

IN

V

OUT

LDAC

C6

0.1␮F

2

3
4

5
6

7

8

9

2

3
4

5
6

7

8

9

10

10

74LS245

119

+5V

74LS245

119

+5V

C7

0.1␮F

20

18

17
16

15
14

13

12

11

20

18

17
16

15
14

13

12

11

J1

C31/A31

C4/A4

C5/A5

C6/A6

C7/A7
C8/A8

C9/A9

C10/A10

C11/A11

C12/A12

C13/A13

C14/A14

C15/A15
C16/A16

C17/A17

C18/A18

C19/A19

C20/A20

C21/A21

C22/A22

C23/A23

C32/A32

Figure 28. Schematic for AD7846 Board

REV. E

–13–

AD7846

Figure 29. PCB Component Side Layout for Figure 28

Figure 30. PCB Solder Side Layout for Figure 30

–14–

REV. E

AD7846

Figure 31. Component Overlay for Circuit of Figure 28

REV. E

–15–

AD7846

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

28-Lead Ceramic DIP (Q-28)

0.005 (0.13) MIN

28

114

0.225
(5.72)

MAX

0.200 (5.08)

0.125 (3.18)

0.200

(5.080)

MAX

SEATING

PLANE

0.100 (2.54) MAX

15

PIN 1

1.490 (37.85) MAX

0.026 (0.66)

0.014 (0.36)

0.110 (2.79)

0.090 (2.29)

0.070 (1.78)

0.030 (0.76)

28-Lead Plastic DIP (N-28A)

1.450 (36.83)

1.440 (35.576)

28

1

PIN 1

0.020 (0.508)

0.015 (0.381)

0.100
(2.54)

BSC

0.065 (1.65)

0.045 (1.14)

0.610 (15.49)

0.500 (12.70)

0.015
(0.38)
MIN

0.150
(3.81)
MIN

SEATING
PLANE

15

0.550 (13.97)

0.530 (13.462)

14

0.160 (4.06)

0.140 (3.56)

0.620 (15.75)

0.590 (14.99)

0.018 (0.46)

0.008 (0.20)

15°

0°

0.606 (15.39)

0.594 (15.09)

15°

0°

C1245c–1–6/00 (rev. E) 01201

0.012 (0.306)

0.008 (0.203)

28-Lead Plastic Leaded Chip Carrier (PLCC)

(P-28A)

0.180 (4.57)

0.050
(1.27)
BSC

0.165 (4.19)

0.110 (2.79)

0.085 (2.16)

0.048 (1.21)

0.042 (1.07)

0.020
(0.50)

0.048 (1.21)

0.042 (1.07)

4

5

11

12

0.456 (11.58)

R

0.450 (11.43)

0.495 (12.57)

0.485 (12.32)

PIN 1

IDENTIFIER

TOP VIEW

(PINS DOWN)

0.056 (1.42)

0.042 (1.07)

26

25

19

18

SQ

SQ

–16–

0.025 (0.63)

0.015 (0.38)

0.021 (0.53)

0.013 (0.33)

0.032 (0.81)

0.026 (0.66)

0.040 (1.01)

0.025 (0.64)

0.430 (10.92)

0.390 (9.91)

PRINTED IN U.S.A.

REV. E