ANALOG DEVICES AD7834, AD7835 Service Manual

LC2MOS

V

VCCVDDVSSV

A

V

A

FEATURES

Four 14-bit DACs in one package AD7834—serial loading AD7835—parallel 8-bit/14-bit loading Voltage outputs Power-on reset function Maximum/minimum output voltage range of ±8.192 V Maximum output voltage span of 14 V Common voltage reference inputs User-assigned device addressing Clear function to user-defined voltage Surface-mount packages AD7834—28-lead SOIC and PDIP AD7835—44-lead MQFP and PLCC

APPLICATIONS

Process control Automatic test equipment General-purpose instrumentation

GENERAL DESCRIPTION

The AD7834 and AD7835 contain four 14-bit DACs on one monolithic chip. The AD7834 and AD7835 have output voltages in the range ±8.192 V with a maximum span of 14 V.

The AD7834 is a serial input device. Data is loaded in 16-bit format from the external serial bus, MSB first after two leading 0s,

Quad 14-Bit DACs

AD7834/AD7835

into one via DIN, SCLK, and dedicated package address pins, PA0 to PA4, that can be wired to AGND or V

to permit up to 32 AD7834s to be individually

CC

addressed in a multipackage application.

The AD7835 can accept either 14-bit parallel loading or doublebyte loading, where right-justified data is loaded in one 8-bit byte and one 6-bit byte. Data is loaded from the external bus into one of the input latches under the control of the BYSHF

, and DAC channel address pins, A0 to A2.

With each device, the DAC outputs simultaneously, or individually, on reception of new data. In addition, for each device, the asynchronous input can be used to set all signal outputs, V the user-defined voltage level on the device sense ground pin, DSG. On power-on, before the power supplies have stabilized, internal circuitry holds the DAC output voltage levels to within ±2 V of the DSG potential. As the supplies stabilize, the DAC output levels move to the exact DSG potential (assuming exercised).

The AD7834 is available in a 28-lead 0.3" SOIC package and a 28-lead 0.6" PDIP package, and the AD7835 is available in a 44-lead MQFP package and a 44-lead PLCC package.

FSYNC

. The AD7834 has five

LDAC

signal is used to update all four

OUT

1 to V

WR

OUT

, CS,

CLR

4, to

CLR

is

FUNCTIONAL BLOCK DIAGRAMS

(–)

VDDV

PAE N

PA0

PA1

PA2

PA3

PA4

FSYNC

DIN

SCLK

AD7834

CONTROL

LOGIC

AND

ADDRESS

DECODE

SERIAL-TO-

PARALLEL

CONVERTER

CC

AGND DGND DSG

INPUT

REGI STER

1

INPUT

REGISTER

2

INPUT

REGISTER

3

INPUT

REGISTER

4

SS

DAC 1

LATCH

DAC 2

LATCH

DAC 3

LATCH

DAC 4

LATCH

LDAC

Figure 1. AD7834 Figure 2. AD7835

Rev. D

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

REF

DAC 1

DAC 2

DAC 3

DAC 4

V

(+)

REF

×1

V

OUT

×1

V

OUT

V

×1

OUT

×1

V

OUT

CLR

(–)

REF

AD7835

1

2

3

4

BYSHF

DB13

01006-001

DB0

WR

CS

INPUT

BUFFER

A0

ADDRESS

A1

DECODE

A2

INPUT

REGISTER

1

14

INPUT

REGISTER

2

INPUT

REGISTER

3

INPUT

REGISTER

4

AGND DGND

DAC 1

LATCH

DAC 2

LATCH

DAC 3

LATCH

DAC 4

LATCH

LDAC

V

REF

DAC 3

(–)B

DAC 1

DAC 2

DAC 4

(+)

DSGA

REF

×1

V

1

OUT

×1

V

2

OUT

×1

V

3

OUT

×1

DSGB

(+)B

V

REF

V

OUT

CLR

4

01006-002

www.analog.com

AD7834/AD7835

REVISION HISTORY

7/07—Rev. C to Rev. D

Changes to Table 5 ........................................................................... 7

Added Table 6.................................................................................... 7

Changes to Table 8............................................................................ 9

Updated Outline Dimensions....................................................... 25

Changes to Ordering Guide.......................................................... 27

7/05—Rev. B to Rev. C

Updated Format..................................................................Universal

Changes to Figure 40...................................................................... 25

Changes to Ordering Guide.......................................................... 27

7/03—Rev. A to Rev. B

Revision 0: Initial Version

Rev. D | Page 2 of 28

AD7834/AD7835

SPECIFICATIONS

1

= T

VCC = 5 V ± 5%; VDD = 15 V ± 5%; VSS = −15 V ± 5%; AGND = DGND = 0 V; T

A

MIN

to T

Table 1.

Parameter

A B S Unit Test Conditions/Comments

ACCURACY

Resolution 14 14 14 Bits Relative Accuracy ±2 ±1 ±2 LSB max Differential Nonlinearity ±0.9 ±0.9 ±0.9 LSB max Guaranteed monotonic over temperature. Full-Scale Error V

T

to T

MIN

±5 ±5 ±8 mV max

MAX

Zero-Scale Error ±4 ±4 ±5 mV max V Gain Error ±0.5 ±0.5 ±0.5 mV typ V Gain Temperature

Coefficient

2

4 4 4 ppm FSR/°C typ

20 20 20 ppm FSR/°C max DC Crosstalk2 50 50 50 μV max See the Terminology section. RL = 10 kΩ.

REFERENCE INPUTS

DC Input Resistance 30 30 30 MΩ typ Input Current ±1 ±1 ±1 μA max Per input. V

(+) Range 0/8.192 0/8.192 0/8.192 V min/max

REF

V

(−) Range −8.192/0 −8.192/0 −8.192/0 V min/max

REF

V

REF

(+) − V

(−) 5/14 7/14 5/14 V min/max

REF

DEVICE SENSE GROUND INPUTS

Input Current ±2 ±2 ±2 μA max Per input. V

DIGITAL INPUTS

V

, Input High Voltage 2.4 2.4 2.4 V min

INH

V

, Input Low Voltage 0.8 0.8 0.8 V max

INL

I

, Input Current ±10 ±10 ±10 μA max

INH

CIN, Input Capacitance 10 10 10 pF max

POWER REQUIREMENTS

VCC 5.0 5.0 5.0 V nom ±5% for specified performance. VDD 15.0 15.0 15.0 V nom ±5% for specified performance. VSS −15.0 −15.0 −15.0 V nom ±5% for specified performance. Power Supply Sensitivity

ΔFull Scale/ΔVDD 110 110 110 dB typ

ΔFull Scale/ΔVSS 100 100 100 dB typ ICC 0.2 0.2 0.5 mA max V 3 3 3 mA max AD7834: V 6 6 6 mA max AD7835: V IDD 13 13 15 mA max AD7834: outputs unloaded. 15 15 15 mA max AD7835: outputs unloaded. ISS 13 13 15 mA max Outputs unloaded.

1

Temperature range for A, B, and C versions is −40°C to +85°C.

2

Guaranteed by design.

, unless otherwise noted.

MAX

(+) = +7 V, V

REF

(+) = +7 V, V

REF

(+) = +7 V, V

REF

(−) = −7 V.

REF

(−) = −7 V.

REF

(−) = −7 V.

REF

For specified performance. Can go as low as 0 V, but performance is not guaranteed.

= −2 V to +2 V.

DSG

= VCC, V

INH

= DGND.

INL

= 2.4 V min, V

INH

= 2.4 V min, V

INH

= 0.8 V max.

INL

= 0.8 V max.

INL

Rev. D | Page 3 of 28

AD7834/AD7835

VCC = 5 V ± 5%; VDD = 12 V ± 5%; VSS = −12 V ± 5%; AGND = DGND = 0 V; T

1

= T

to T

MIN

A

, unless otherwise noted.

MAX

Table 2.

Parameter

A B S Unit Test Conditions/Comments

ACCURACY

Resolution 14 14 14 Bits Relative Accuracy ±2 ±1 ±2 LSB max Differential Nonlinearity ±0.9 ±0.9 ±0.9 LSB max Guaranteed monotonic over temperature. Full-Scale Error V

T

to T

MIN

±5 ±5 ±8 mV max

MAX

Zero-Scale Error ±4 ±4 ±5 mV max V Gain Error ±0.5 ±0.5 ±0.5 mV typ V

(+) = +5 V, V

REF

(+) = +5 V, V

REF

(+) = +5 V, V

REF

(−) = –5 V.

REF

(−) = −5 V.

REF

(−) = −5 V.

REF

Gain Temperature Coefficient2 4 4 4 ppm FSR/°C typ 20 20 20 ppm FSR/°C max DC Crosstalk2 50 50 50 μV max See the Terminology section. RL = 10 kΩ.

REFERENCE INPUTS

DC Input Resistance 30 30 30 MΩ typ Input Current ±1 ±1 ±1 μA max Per input. V

(+) Range 0/8.192 0/8.192 0/8.192 V min/max

REF

V

(−) Range −5/0 −5/0 −5/0 V min/max

REF

V

REF

(+) − V

(−) 5/13.192 7/13.192 5/13.192 V min/max

REF

For specified performance. Can go as low as 0 V, but performance is not guaranteed.

DEVICE SENSE GROUND INPUTS

Input Current ±2 ±2 ±2 μA max Per input. V

= −2 V to +2 V.

DSG

DIGITAL INPUTS

V

, Input High Voltage 2.4 2.4 2.4 V min

INH

V

, Input Low Voltage 0.8 0.8 0.8 V max

INL

I

, Input Current ±10 ±10 ±10 μA max

INH

CIN, Input Capacitance 10 10 10 pF max

POWER REQUIREMENTS

VCC 5.0 5.0 5.0 V nom ±5% for specified performance. VDD 15.0 15.0 15.0 V nom ±5% for specified performance. VSS −15.0 −15.0 −15.0 V nom ±5% for specified performance. Power Supply Sensitivity

ΔFull Scale/ΔVDD 110 110 110 dB typ

ΔFull Scale/ΔVSS 100 100 100 dB typ ICC 0.2 0.2 0.5 mA max V 3 3 3 mA max AD7834: V 6 6 6 mA max AD7835: V

= VCC, V

INH

= DGND.

INL

= 2.4 V min, V

INH

= 2.4 V min, V

INH

= 0.8 V max.

INL

= 0.8 V max.

INL

IDD 13 13 15 mA max AD7834: outputs unloaded. 15 15 15 mA max AD7835: outputs unloaded. ISS 13 13 15 mA max Outputs unloaded.

1

Temperature range for A, B, and C versions is −40°C to +85°C.

2

Guaranteed by design.

Rev. D | Page 4 of 28

AD7834/AD7835

AC PERFORMANCE CHARACTERISTICS

These characteristics are included for design guidance and are not subject to production testing.

Table 3.

Parameter

DYNAMIC PERFORMANCE

Output Voltage Settling Time 10 10 10 μs

Digital-to-Analog Glitch Impulse 120 120 120 nV-s

DC Output Impedance 0.5 0.5 0.5 Ω See the Terminology section. Channel-to-Channel Isolation 100 100 100 dB See the Terminology section; applies to the AD7835 only. DAC-to-DAC Crosstalk 25 25 25 nV-s See the Terminology section. Digital Crosstalk 3 3 3 nV-s

Digital Feedthrough—AD7834 0.2 0.2 0.2 nV-s Effect of input bus activity on DAC output under test. Digital Feedthrough—AD7835 1.0 1.0 1.0 nV-s Output Noise Spectral Density at 1 kHz 40 40 40 nV/√Hz All 1s loaded to DAC. V

A B S Unit (typ) Test Conditions/Comments

Full-scale change to ±1/2 LSB. DAC latch contents alternately loaded with all 0s and all 1s.

Measured with V

(+) = V

REF

alternately loaded with all 0s and all 1s.

Feedthrough to DAC output under test due to change in digital input code to another converter.

(+) = V

REF

(−) = 0 V. DAC latch

(−) = 0 V.

REF

Rev. D | Page 5 of 28

AD7834/AD7835

)

TIMING SPECIFICATIONS

VCC = 5 V ± 5%; VDD = 11.4 V to 15.75 V; VSS = −11.4 V to −15.75 V; AGND = DGND = 0 V1.

Table 4.

Parameter Limit at T

MIN

AD7834-SPECIFIC

2

t

1

2

t

2

t

30 ns min SCLK high time

3

30 ns min

t4

100 ns min SCLK cycle time 50 ns min SCLK low

t5 40 ns min t6 30 ns min Data setup time

10 ns min Data hold time

t7

0 ns min

t8 t9 40 ns min t21 20 ns min Delay between write operations

AD7835-SPECIFIC

t11 15 ns min t12 15 ns min t13 0 ns min t14 0 ns min t15 40 ns min t16 40 ns min Data setup time

10 ns min Data hold time

t17

0 ns min

t18 t19 0 ns min t20 0 ns min

GENERAL

t10 40 ns min

1

All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and time from a voltage level of 1.6 V.

2

Rise and fall times should be no longer than 50 ns.

1ST

SCLK

FSYNC

DIN

(SIMULTANEOUS

LDAC

UPDATE)

LDAC

(PER-CHANNE L

UPDATE

2ND

CLK

t

4

t

6

t

MSB LSB

7

D23 D2 2

t

8

Figure 3. AD7834 Timing Diagram Figure 4. AD7835 Timing Diagram

t

1

t

2

Unit Description

, T

MAX

24TH

CLK

t

3

t

5

t

21

D0

D1

t

10

t

9

01006-003

(SIMULTANEOUS

(PER-CHANNEL

, PAEN setup time

FSYNC

, PAEN hold time

FSYNC

LDAC

to FSYNC setup time to FSYNC hold time

LDAC

A0, A1, A2, BYSHF A0, A1, A2, BYSHF CS

to WR setup time

CS

to WR hold time

WR

pulse width

LDAC

to CS setup time

CS

to LDAC setup time

to CS hold time

LDAC

, CLR pulse width

A0 A1 A2

BYSHF

CS

WR

DB0 TO DB13

LDAC

UPDATE)

LDAC

UPDATE)

to CS setup time to CS hold time

t

11

t

13

t

18

t

15

t

16

t

12

t

14

t

17

t

10

t

19

t

20

01006-004

Rev. D | Page 6 of 28

AD7834/AD7835

ABSOLUTE MAXIMUM RATINGS

TA = 25°C unless otherwise noted. Transient currents of up to 100 mA do not cause SCR latch-up. VCC must not exceed VDD by more than

0.3 V. If it is possible for this to happen during power supply sequencing, the diode protection scheme shown in

provide protection.

V

Table 5.

Parameter Rating

VCC to DGND −0.3 V to +7 V, or VDD + 0.3 V

(whichever is lower)

VDD to AGND −0.3 V to +17 V

DD

IN4148

SD103C

V

DD

AD7834/

AD7835

VSS to AGND +0.3 V to –17 V

AGND to DGND −0.3 V to +0.3 V

Figure 5. Diode Protection

−0.3 V to VCC + 0.3 V Digital Inputs to DGND

V

(+) to V

REF

V

(+) to AGND VSS – 0.3 V to VDD + 0.3 V

REF

V

(–) to AGND VSS – 0.3 V to VDD + 0.3 V

REF

(–) −0.3 V to +18 V

REF

VSS – 0.3 V to VDD + 0.3 V DSG to AGND

V

(1–4) to AGND VSS – 0.3 V to VDD + 0.3 V

OUT

Operating Temperature Range, T

A

−40°C to +85°C Industrial (A Version)

−65°C to +150°C Storage Temperature Range

150°C Junction Temperature, TJ (max) Power Dissipation, PD (max) (TJ − TA)/θJA Lead Temperature JEDEC Industry Standard

Soldering J-STD-020

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages.

Table 6. Thermal Resistance

Package Type θJA Unit

PDIP 75 °C/W SOIC 75 MQFP 95 PLCC 55 °C/W

ESD CAUTION

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Figure 5 can be used to

V

CC

V

CC

01006-005

°C/W °C/W

Rev. D | Page 7 of 28

AD7834/AD7835

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

28

27

26

25

24

23

22

21

20

19

18

17

16

15

AGND

NC

V

DD

V

OUT

V

OUT

CLR

LDAC

FSYNC

PAEN

PA4

PA3

1

3

01006-006

V

REF

V

REF

V

DGND

SCLK

V

DSG

OUT

V

DIN

PA0

PA1

PA2

SS

(–)

(+)

NC

2

4

CC

1

2

3

4

5

AD7834

6

TOP VIEW

(Not to Scale)

7

8

9

10

11

12

13

14

NC = NO CONNECT

Figure 6. AD7834 PDIP and SOIC Pin Configuration

Table 7. AD7834 Pin Function Descriptions

Pin No. Pin Mnemonic Description

1 VSS Negative Analog Power Supply: −15 V ± 5% or −12 V ± 5%. 2 DSG

3 V 4 V

(−) Negative Reference Input. The negative reference voltage is referred to AGND.

REF

Positive Reference Input. The positive reference voltage is referred to AGND.

(+)

REF

5, 24, 25, 26, 27 NC

V

OUT

1 to V

OUT

4 8 DGND 9 VCC

Logic Power Supply: 5 V ± 5%.

10 SCLK

Device Sense Ground Input. Used in conjunction with the CLR the DACs. When CLR

is low, the DAC outputs are forced to the potential on the DSG pin.

No Connect.

22, 6, 21, 7 DAC Outputs.

Digital Ground.

Clock Input. Used for writing data to the device; data is clocked into the input register on the

falling edge of SCLK. 11 DIN 12,13,14,15,16 PA0 to PA4

Serial Data Input.

Package Address Inputs. These inputs are hardwired high (VCC) or low (DGND) to assign dedicated

package addresses in a multipackage environment. 17

PAEN

Package Address Enable Input. When low, this input allows normal operation of the device. When

high, the device ignores the package address, but not the channel address, in the serial data

stream and loads the serial data into the input registers. This feature is useful in a multipackage

application where it can be used to load the same data into the same channel in each package. 18

Frame Sync Input. Active low logic input used, in conjunction with DIN and SCLK, to write data to

FSYNC

the device with serial data expected after the falling edge of this signal. The contents of the 24-bit

serial-to-parallel input register are transferred on the rising edge of this signal. 19

Load DAC Input (Level Sensitive). This input signal, in conjunction with the FSYNC input signal,

LDAC

determines how the analog outputs are updated. If

is maintained high while new data is being loaded into the device’s input registers, no change occurs on the analog outputs. Subsequently, when

LDAC

is brought low, the contents of all four input registers are transferred

into their respective DAC latches, updating all of the analog outputs simultaneously.

20

CLR

Asynchronous Clear Input (Level Sensitive, Active Low). When this input is brought low, all analog outputs are switched to the externally set potential on the DSG pin. When CLR signal outputs remain at the DSG potential until LDAC

is brought low. When LDAC is brought low,

the analog outputs are switched back to reflect their individual DAC output levels. As long as CLR

LDAC

remains low, the potential on the DSG pin.

signals are ignored, and the signal outputs remain switched to the

23 VDD Positive Analog Power Supply: 15 V ± 5% or 12 V ± 5%. 28 AGND Analog Ground.

input for power-on protection of

is brought high, the

Rev. D | Page 8 of 28

AD7834/AD7835

AGND

DB2

NC

DB3

(+)B

V

DB4

NC

1

DSGA

2

1

V

3

OUT

2

V

4

OUT

NC

5

A2

6

A1

7

8

A0

CLR

9

LDAC

10

11

BYSHF

NC = NO CONNECT

(+)A

(–)A

REF

NC

V

PIN 1 IDENTIFIER

REF

V

DD

SS

V

NC

40 39 3841424344 36 35 3437

AD7835

TOP VIEW

(Not to Scale)

12 13 14 15 16 17 18 192021 22

CC

CS

WR

V

DB0

DGND

DB1

Figure 7. AD7835 MQFP Pin Configuration Figure 8. AD7835 PLCC Pin Configuration

Table 8. AD7835 Pin Function Descriptions

Pin No. MQFP

1, 5, 33, 34, 37, 41, 44

Pin No. PLCC Pin Mnemonic Description

3, 6, 7, 11, 39,

NC No Connect.

40, 43

(–)A

(–)B

REF

V

NC

DSGA

V

OUT

V

OUT

CLR

LDAC

BYSHF

NC

A0

7

8

1

9

10

2

11

A2

12

13

A1

14

15

16

17

DB5

DB6

NC

33

32

DSGB

3

V

31

OUT

4

30

V

OUT

DB13

29

DB12

28

27

DB11

DB10

26

25

DB9

24

DB8

23

DB7

01006-007

NC = NO CONNECT

(+)A

REF

NC

V

SS

DD

V

AGND

V

244345642414043

1

PIN 1 IDENTIFIER

NC

REF

V

AD7835

TOP VIEW

(Not to Scale)

181920 21 22 23 24 252627 28

CC

CS

WR

V

DGND

DB0

DB1

DB2

NC

DB3

(+)B

REF

V

DB4

(–)B

REF

V

DB5

NC

DB6

NC

39

38

DSGB

3

V

37

OUT

36

4

V

OUT

DB13

35

34

DB12

33

DB11

DB10

32

31

DB9

DB8

30

29

DB7

01006-008

2 8 DSGA

Device Sense Ground A Input. Used in conjunction with the CLR protection of the DACs. When

V

1 to V

OUT

8, 7, 6 14, 13, 12 A0, A1, A2

potential on the DSGA pin.

4 3, 4, 31, 30 9, 10, 37, 36 DAC Outputs.

OUT

Address Inputs. A0 and A1 are decoded to select one of the four input latches for a data transfer. A2 is used to select all four DACs simultaneously.

9 15

CLR

Asynchronous Clear Input (Level Sensitive, Active Low). When this input is brought low,

all analog outputs are switched to the externally set potentials on the DSG pins (V and V

2 follow DSGA, and V

OUT

signal outputs remain at the DSG potentials until LDAC brought low, the analog outputs are switched back to reflect their individual DAC output levels. As long as

remains low, the LDAC signals are ignored, and the signal outputs

CLR

remain switched to the potential on the DSG pins.

10 16

Load DAC Input (Level Sensitive). This input signal, in conjunction with the WR and CS

LDAC

input signals, determines how the analog outputs are updated. If high while new data is being loaded into the device’s input registers, no change occurs on the analog outputs. Subsequently, when input registers are transferred into their respective DAC latches, updating the analog outputs simultaneously. Alternatively, if entered, the addressed DAC latch and corresponding analog output are updated immediately on the rising edge of

11 17

Byte Shift Input. When low, it shifts the data on DB0 to DB7 into the DB8 to DB13 half of

BYSHF

the input register.

12 18

CS

Level-Triggered Chip Select Input (Active Low). The device is selected when this input is

low.

13 19

Level-Triggered Write Input (Active Low). When active, it is used in conjunction with CS

WR

to write data over the input databus. 14 20 VCC Logic Power Supply: 5 V ± 5%. 15 21 DGND Digital Ground.

CLR

is low, DAC outputs V

OUT

3 and V

4 follow DSGB). When CLR

OUT

LDAC

.

WR

input for power-on

1 and V

OUT

2 are forced to the

OUT

is brought high, the

is brought low. When LDAC is

LDAC

is maintained

is brought low, the contents of all four

is brought low while new data is being

1

Rev. D | Page 9 of 28

ANALOG DEVICES AD7834, AD7835 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAMS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

AC PERFORMANCE CHARACTERISTICS

TIMING SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS