Datasheet AD7824, AD7828 Datasheet (ANALOG DEVICES)

LC2MOS High Speed

www.BDTIC.com/ADI

a

FEATURES
4 or 8 Analog Input Channels
Built-In Track-and-Hold Function
10 kHz Signal Handling on Each Channel
Fast Microprocessor Interface
Single 5 V Supply
Low Power: 50 mW
Fast Conversion Rate: 2.5 ␮s/Channel
Tight Error Specification: 1/2 LSB

GENERAL DESCRIPTION

The AD7824 and AD7828 are high speed, multichannel, 8-bit
ADCs with a choice of four (AD7824) or eight (AD7828)
plexed analog inputs. A half-flash conversion technique gives a fast
conversion rate of 2.5 µs per channel, and the parts have a built-in
track-and-hold function capable of digitizing full-scale signals of
10 kHz (157 mV/µs slew rate) on all channels. The AD7824 and
AD7828 operate from a single 5 V supply and have an analog input
range of 0 V to 5 V, using an external 5 V reference.

Microprocessor interfacing of the parts is simple, using standard
Chip Select (CS) and Read (RD) signals to initiate the conversion
and read the data from the three-state data outputs. The half-flash
conversion technique means that there is no need to generate a
clock signal for the ADC. The AD7824 and AD7828 can be
interfaced easily to most popular microprocessors.

The AD7824 and AD7828 are fabricated in an advanced, all
ion-implanted, linear compatible CMOS process (LC2MOS) and
have low power dissipation of 40 mW (typ). The AD7824 is
available in a 0.3" wide, 24-lead “skinny” DIP, while the AD7828
is available in a 0.6" wide, 28-lead DIP and in 28-terminal
mount packages.

multi-

surface-

4- and 8-Channel 8-Bit ADCs

AD7824/AD7828

FUNCTIONAL BLOCK DIAGRAM

(+)

V

REF

(–)

V

REF

AIN1

AIN4

MUX*

AIN8

ADDRESS

LATCH

DECODE

A0 A1 A2**

*AD7824 – 4-CHANNEL MUX
**AD7828 – 8-CHANNEL MUX

A2 – AD7828 ONLY

V

REF

4-BIT

FLASH

ADC

(4MSB)

CS

THREE-

STATE

DRIVERS

4-BIT

DAC

(+)

4-BIT

16

FLASH

ADC

(4LSB)

TIMING AND CONTROL

CIRCUITRY

RDY

PRODUCT HIGHLIGHTS

1. 4- or 8-channel input multiplexer gives cost effective,
space-saving multichannel ADC system.

2. Fast conversion rate of 2.5 µs/channel features a per-channel
sampling frequency of 100 kHz for the AD7824 or 50 kHz
for the AD7828.

3.

Built-in track-and-hold function allows handling of four or
eight channels up to 10 kHz bandwidth (157 mV/µs slew rate).

4. Tight total unadjusted error spec and channel-to-channel
matching eliminate the need for user trims.

5. Single 5 V supply simplifies system power requirements.

6. Fast, easy-to-use digital interface allows connection to most
popular microprocessors with minimal external components.
No clock signal is required for the ADC.

RD

DB7
DB6
DB5
DB4

DB3
DB2
DB1
DB0

INT

REV. F

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

AD7824/AD7828–SPECIFICATIONS

www.BDTIC.com/ADI

noted. All specifications T

MIN

to T

, unless otherwise noted. Specifications apply to Mode 0.)

MAX

(VDD = 5 V, V

(+) = 5 V, V

REF

(–) = GND = O V, unless otherwise

REF

Parameter K Version1L Version B, T Versions C, U Versions Unit Conditions/Comments

ACCURACY

Resolution 8 8 8 8 Bits
Total Unadjusted Error

2

± 1 ± 1/2 ± 1 ± 1/2 LSB max

Minimum Resolution for which

No Missing Codes Are Guaranteed 8 8 8 8 Bits

Channel-to-Channel Mismatch ± 1/4 ± 1/4 ± 1/4 ± 1/4 LSB max

REFERENCE INPUT

Input Resistance 1.0/4.0 1.0/4.0 1.0/4.0 1.0/4.0 kΩ min/kΩ max

(+) Input Voltage Range V

V

REF

V

(–) Input Voltage Range GND/ GND/ GND/ GND/ V min/V max

REF

REF

V

DD

V

REF

(–)/ V

(+) V

REF

V

DD

REF

(–)/ V

(+) V

(–)/ V

REF

V

DD

(+) V

REF

(–)/ V min/V max

REF

V

DD

(+)

REF

ANALOG INPUT

Input Voltage Range V

Input Leakage Current ± 3 ± 3 ± 3 ± 3 µA max Analog Input Any Channel
Input Capacitance

3

REF

V

REF

(–)/ V
(+) V

REF

REF

(–)/ V
(+) V

(–)/ V

REF

(+) V

REF

(–)/ V min/V max

REF

(+)

REF

45 45 45 45 pF typ 0 V to 5 V

LOGIC INPUTS

RD, CS, A0, A1, and A2

V

INH

V

INL

I

INH

I

INL

Input Capacitance

3

2.4 2.4 2.4 2.4 V min

0.8 0.8 0.8 0.8 V max
111 1 µA max
–1 –1 –1 –1 µA max
8888pF max Typically 5 pF

LOGIC OUTPUTS

DB0–DB7 and INT

V

OH

V

OL

(DB0–DB7) ± 3 ± 3 ± 3 ± 3 µA max Floating State Leakage

I

OUT

Output Capacitance
RDY

4

V

OL

I

OUT

3

4.0 4.0 4.0 4.0 V min I

0.4 0.4 0.4 0.4 V max I

8888pF max Typically 5 pF

0.4 0.4 0.4 0.4 V max I
± 3 ± 3 ± 3 ± 3 µA max Floating State Leakage

SOURCE

= 1.6 mA

SINK

= 2.6 mA

SINK

= 360 µA

Output Capacitance 8 8 8 8 pF max Typically 5 pF

SLEW RATE, TRACKING

3

0.7 0.7 0.7 0.7 V/µs typ

0.157 0.157 0.157 0.157 V/µs max

POWER SUPPLY

V

DD

5

I

DD

555 5 V ± 5% for Specified

Performance

16 16 20 20 mA max CS = RD = 2.4 V

Power Dissipation 50 50 50 50 mW typ

80 80 100 100 mW max

Power Supply Sensitivity ± 1/4 ±1/4 ± 1/4 ±1/4 LSB max ± 1/16 LSB typ

VDD = 5 V ± 5%

NOTES

1

Temperature ranges are as follows: K, L Versions: 0°C to 70°C

2

Total Unadjusted Error includes offset, full-scale and linearity errors.

3

Sample tested at 25°C by Product Assurance to ensure compliance.

4

RDY is an open-drain output.

5

See Typical Performance Characteristics.

Specifications subject to change without notice.

B, C Versions: –40°C to +85°C
T, U Versions: –55°C to +125°C

–2–

REV. F

AD7824/AD7828

www.BDTIC.com/ADI

1

TIMING CHARACTERISTICS

Limit at 25ⴗC Limit at T

(VDD = 5 V; V

, T

MIN

Parameter (All Grades) (K, L, B, C Grades) (T, U Grades) Unit Conditions/Comments

t

CSS

t

CSH

t

AS

t

AH

t

RDY

t

CRD

t

ACC1

t

ACC2

t

lNTH

t

DH

t

P

t

RD

2

3

3

2

4

00 0 ns min CS to RD Setup Time
00 0 ns min CS to RD Hold Time
00 0 ns min Multiplexer Address Setup Time
30 35 40 ns min Multiplexer Address Hold Time
40 60 60 ns max CS to RDY Delay. Pull-Up

2.0 2.4 2.8 µs max Conversion Time, Mode 0
85 110 120 ns max Data Access Time after RD
50 60 70 ns max Data Access Time after INT, Mode 0
40 65 70 ns typ RD to INT Delay
75 100 100 ns max
60 70 70 ns max Data Hold Time
500 500 600 ns min Delay Time between Conversions
60 80 80 ns min Read Pulsewidth, Mode 1
600 500 400 ns max

NOTES

1

Sample tested at 25°C to ensure compliance. All input control signals are specified with t

2

CL = 50 pF.

3

Measured with load circuits of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.

4

Defined as the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 2.

Specifications subject to change without notice.

REF

MAX

(+) = 5 V; V

Limit at T

(–) = GND = 0 V, unless otherwise noted.)

REF

, T

MIN

MAX

Resistor 5 kΩ.

= t

RISE

= 20 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.

FALL

Test Circuits

DBN

3k⍀ 100pF

DGND

a. High-Z to V

DBN

b. High-Z to V

Figure 1. Load Circuits for Data Access Time Test

OH

5V

3k⍀

100pF

DGND

OL

DBN

3k⍀ 10pF

DGND

a. VOH to High-Z

5V

3k⍀

DBN

10pF

DGND

b. VOL to High-Z

Figure 2. Load Circuits for Data Hold Time Test

REV. F

–3–

AD7824/AD7828

www.BDTIC.com/ADI

ABSOLUTE MAXIMUM RATINGS*

(TA = 25°C, unless otherwise noted.)

VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, 7 V

Digital Input Voltage to GND

(RD, CS, A0, A1, and A2) . . . . . . . . . –0.3 V, V

+ 0.3 V

DD

Digital Output Voltage to GND

(DB0, DB7, RDY, and INT) . . . . . . . –0.3 V, V

V

(+) to GND . . . . . . . . . . . . . . . . . V

REF

(–) to GND . . . . . . . . . . . . . . . . . . . . . . . . 0 V, V

V

REF

(–), VDD + 0.3 V

REF

Analog Input (Any Channel) . . . . . . . . . . –0.3 V, V

+ 0.3 V

DD

REF

+ 0.3 V

DD

(+)

Operating Temperature Range

Commercial (K, L Versions) . . . . . . . . . . . . . . 0°C to 70°C

Industrial (B, C Versions) . . . . . . . . . . . . . –40°C to +85°C

Extended (T, U Versions) . . . . . . . . . . . . –55°C to +125°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . 300°C

Power Dissipation (Any Package) to 75°C . . . . . . . . . 450 mW

Derates above 75°C by . . . . . . . . . . . . . . . . . . . . . . 6 mW/°C

*Stresses above those listed under Absolute Maximum Ratings may cause

permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although AD7824/AD7828 feature proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

PIN CONFIGURATIONS

ORDERING GUIDE

DIP/SOIC/SSOP

Temperature Unadjusted Package

1

AIN4 V

2

AIN3 NC

3

AIN2 A0

4

AIN1 A1

5

NC DB7

AD7824

6

DB0 DB6

TOP VIEW

(Not to Scale)

7

DB1 DB5

8

DB2 DB4

9

DB3

10

RD

11

INT

12

GND V

NC = NO CONNECT

24

23

22

21

20

19

18

17

16

CS

15

RDY

14

V

13

PLCC

DD

REF

REF

1

AIN6

2

AIN5

3

AIN4

4

AIN3

5

AIN2

6

AIN1

DB0

DB1

DB2

(+)

(–)

DB3

GND

AD7828

7

NC

TOP VIEW

(Not to Scale)

8

9

10

11

12

RD

13

INT

14

NC = NO CONNECT

28

AIN7

27

AIN8

26

V

DD

25

A0

24

A1

23

A2

22

DB7

21

DB6

20

DB5

19

DB4

18

CS

17

RDY

16

V

(+)

REF

15

V

(–)

REF

Model Range Error (LSBs) Option

AD7824KN 0°C to 70°C ± 1 N-24
AD7824LN 0°C to 70°C ± 1/2 N-24
AD7824KR 0°C to 70°C ± 1 R-24
AD7824BQ –40°C to +85°C ± 1 Q-24
AD7824CQ –40°C to +85°C ± 1/2 Q-24
AD7824TQ* –55°C to +125°C ± 1 Q-24
AD7824UQ* –55°C to +125°C ± 1/2 Q-24

AD7828KN 0°C to 70°C ± 1 N-28
AD7828LN 0°C to 70°C ± 1/2 N-28
AD7828KP 0°C to 70°C ± 1 P-28A
AD7828LP 0°C to 70°C ± 1/2 P-28A
AD7828BQ –40°C to +85°C ± 1 Q-28
AD7828CQ –40°C to +85°C ± 1/2 Q-28
AD7828BR –40°C to +85°C+1 R-28
AD7828LRS 0°C to 70°C ± 1/2 RS-28
AD7828TQ* –55°C to +125°C ± 1 Q-28
AD7828UQ* –55°C to +125°C ± 1/2 Q-28
AD7828TE* –55°C to +125°C ± 1 E-28A
AD7828UE* –55°C to +125°C ± 1/2 E-28A

*Available to /883B processing only. Contact our local sales office for military

data sheet. For U.S. Standard Military Drawing (SMD) see DESC Drawing
#5692-88764.

AIN2

AIN1

NC

DB0

DB1

DB2

DB3

AIN5

AIN4

AIN3

4 3 2 1 28 27 26

5

6

7

8

9

10

11

AD7828

TOP VIEW

(Not to Scale)

12 13 14 15 16 17 18

RD

INT

GND

NC = NO CONNECT

AIN7

AIN6

PIN 1
IDENTIFIER

(–)

(+)

REF

REF

V

V

AIN8

RDY

DD

V

25

A0

24

A1

23

A2

22

DB7

21

DB6

20

DB5

19

DB4

CS

5

AIN2

6

AIN1

7

NC A2

8

DB0 DB7

9

DB1

10

DB2

11

DB3 DB4

LCCC

AIN6

AIN5

AIN4

AIN3

2

28 271

3426

AD7828

TOP VIEW

(Not to Scale)

AIN7

AIN8

DD

V

25

A0

24

A1

23

22

21

DB6

20

DB5

19

WARNING!

ESD SENSITIVE DEVICE

Total

12

13 14 15 16 17 18

REF

(+)

V

REF

CS

RDY

RD

(–)

INT

GND

V

NC = NO CONNECT

–4–

REV. F

Typical Performance Characteristics–AD7824/AD7828

TA – AMBIENT TEMPERATURE – ⴗC

14

12

10

–100 150–50

I

DD

– SUPPLY CURRENT – mA

050100

13

11

9

8

VDD = 5.25V

VDD = 4.75V

VDD = 5V

t

P

– ns

2.0

1.0

0

300

LINEARITY ERROR – LSB

1.5

0.5

VDD = 5V
V

REF

= 5V

T

A

= 25ⴗC

400 500 600 700 800 900

www.BDTIC.com/ADI

3

2

– CONVERSION TIME – ␮s

CRD

t

1
–100 150–50

TA – AMBIENT TEMPERATURE – ⴗC

050100

= 5V

V

DD

TPC 1. Conversion Time vs. Temperature

2.0

1.5

1.0

0.5

LINEARITY ERROR – LSB*

0

051

V

REF

*1LSB =

256

TPC 2. Accuracy vs. V

234

V

– V

REF

[V

REF

= V

REF

REF

VDD = 5V

= 25ⴗC

T

A

(+) – V

REF

(–)]

TPC 4. Power Supply Current vs. Temperature
(Not Including Reference Ladder)

TPC 5. Accuracy vs. t

P

–36

ENCODE RATE = 400kHz
INPUT SIGNAL = 5V p-p

–38

MEASUREMENT BANDWIDTH = 80kHz

–40

–42

–44

SNR – dB

–46

REV. F

–48

–50

–52

TPC 3. Signal Noise Ratio vs. Input Frequency

234

51

INPUT FREQUENCY – kHz

20 30 40 50 70 100710

–5–

10

8

6

4

OUTPUT CURRENT – mA

2

0

–100 150–50

TA – AMBIENT TEMPERATURE – ⴗC

TPC 6. Output Current vs. Temperature

V

DD

I

, V

SOURCE

I

SINK

050100

= 2.4V

OUT

, V

= 0.4V

OUT

= 5V

AD7824/AD7828

www.BDTIC.com/ADI

OPERATIONAL DIAGRAM

The AD7824 is a 4-channel 8-bit ADC and the AD7828 is an
8-channel 8-bit ADC. Operational diagrams for both of these
devices are shown in Figures 3 and 4. The addition of just a 5 V
reference allows the devices to perform the analog-to-digital function.

ANALOG INPUTS

0V TO 5V

P 4LSB

␮

DATA BU S

P CONTROL INPUT

␮

STATUS OUTPUT

AIN4

1

AIN3

2

AIN2

3

AIN1

4

AD7824

NC

5

DB0

6

DB1

7

DB2

8

DB3

9

10

RD

11

INT

GND

12

NC = NO CONNECT

24

23

22

21

20

19

18

17

16

15

14

13

5V

P ADDRESS

␮

BUS

P 4MSB

␮

DATA BU S

P CONTROL INPUT

␮

STATUS OUTPUT

5V

V

DD

NC

A0

A1

DB7

DB6

DB5

DB4

CS

RDY

V

(+)

REF

V

(–)

REF

Figure 3. AD7824 Operational Diagram

ANALOG INPUTS

0V TO 5V

␮P 4LSB

DATA BU S

␮P CONTROL INPUT

STATUS OUTPUT

1

AIN6

2

AIN5

3

AIN4

4

AIN3

5

AIN2

6

AIN1

AD7828

7

NC

8

DB0

9

DB1

10

DB2

11

DB3

12

RD

13

INT

14

GND

NC = NO CONNECT

28

AIN7

AIN8

V

DD

A0

A1

A2

DB7

DB6

DB5

DB4

CS

RDY

V

(+)

REF

V

(–)

REF

27

5V

26

25

24

23

22

21

20

19

␮P CONTROL INPUT

18

STATUS OUTPUT

17

5V

16

15

ANALOG INPUTS
0V TO 5V

␮P ADDRESS
BUS

␮P 4MSB
DATA BU S

Figure 4. AD7828 Operational Diagram

CIRCUIT INFORMATION BASIC DESCRIPTION

The AD7824/AD7828 uses a half-flash conversion technique
whereby two 4-bit flash ADCs are used to achieve an 8-bit result.
Each 4-bit flash ADC contains 15 comparators that compare
the unknown input to a reference ladder to get a 4-bit result.
For a full 8-bit reading to be realized, the upper 4-bit flash, the
most significant (MS) flash, performs a conversion to provide
the four most significant data bits. An internal DAC, driven by
the four MSBs, then recreates an analog approximation of the
input voltage. This analog result is subtracted from the input,
and the difference is converted by the lower flash ADC, the least
significant (LS) flash, to provide the four least significant bits of
the output data. The most significant flash ADC also has one
additional comparator to detect overrange on the analog input.

APPLYING THE AD7824/AD7828 REFERENCE AND INPUT

The two reference inputs on the AD7824/AD7828 are fully differ­ential and define the zero to full-scale input range of the ADC.
As a result, the span of the analog input voltage for all channels
can easily be varied. By reducing the reference span, V
V

(–), to less than 5 V, the sensitivity of the converter can be

REF

increased (e.g., if V

= 2 V then 1 LSB = 7.8 mV). The input/

REF

REF

(+) to

reference arrangement also facilitates ratiometric operation.

This reference flexibility also allows the input channel voltage
span to be offset from zero. The voltage at V

(–) sets the

REF

input level for all channels, which produces a digital output of
all zeroes. Therefore, although the analog inputs are not them­selves differential, they have nearly differential input capability
in most measurement applications because of the reference
design. Figures 5 to 7 show some of the configurations that are
possible.

V

(+)

IN

V

(–)

IN

5V

ADDITIONAL PINS OMITTED FOR CLARITY.

*

ONLY CHANNEL 1 SHOWN.

47␮F0.1␮F

AIN1

GND

V

DD

V

REF

V

REF

AD7824*
AD7828*

(+)

(–)

Figure 5. Power Supply as Reference

V

(+)

IN

VIN (–)

5V

47␮F0.1␮F

AD580

10␮F

ADDITIONAL PINS OMITTED FOR CLARITY.

*

ONLY CHANNEL 1 SHOWN.

0.1␮F

AIN1

GND

V

DD

V

REF

V

REF

AD7824*
AD7828*

(+)

(–)

Figure 6. External Reference Using the AD580, Full-Scale
Input is 2.5 V

VIN (+)

5V

47␮F0.1␮F

ADDITIONAL PINS OMITTED FOR CLARITY.

*

ONLY CHANNEL 1 SHOWN.

(+)

V

IN

DATA = ⴛ 256 (FOR ALL CHANNELS)

V1 – V2

AIN1

AD7824*

GND

AD7828*

V

DD

V1

V

(+)

REF

V

V2

REF

(–)

DB7

DATA

DB0

Figure 7. Input Not Referenced to GND

–6–

REV. F

AD7824/AD7828

www.BDTIC.com/ADI

INPUT CURRENT

Due to the novel conversion techniques employed by the AD7824/
AD7828, the analog input behaves somewhat differently than in
conventional devices. The ADC’s sampled-data comparators
take varying amounts of input current depending on which cycle
the conversion is in.

The equivalent input circuit of the AD7824/AD7828 is shown
in Figure 8. When a conversion starts (CS and RD going low),
all input switches close, and the selected input channel is con­nected to the most significant and least significant comparators.
Therefore, the analog input is simultaneously connected to
31 input capacitors of 1 pF each.

C

S

2pF

R

S

AIN1

V

IN

AD7824/

AD7828

R MUX

C

S

12pF

R

ON

TO LS

LADDER

R

ON

TO MS

LADDER

1pF

•

•

•

15LSB

COMPARATORS

1pF

•

•

•

16MSB

COMPARATORS

1pF

1pF

Figure 8. AD7824/AD7828 Equivalent Input Circuit

The input capacitors must charge to the input voltage through
the on resistance of the analog switches (about 3 kΩ to 6 kΩ). In
addition, about 14 pF of input stray capacitance must be charged.
The analog input for any channel can be modelled as an RC
network, as shown in Figure 9. As R

increases, it takes longer

S

for the input capacitance to charge.

interest. It is important that the amplifier driving the AD7824/
AD7828 analog inputs have sufficient loop gain at the input signal
frequency as to make the output impedance low.

Suitable op amps for driving the AD7824/AD7828 are the AD544
or AD644.

INHERENT SAMPLE-HOLD

A major benefit of the AD7824’s and AD7828’s analog input
structure is its ability to measure a variety of high speed signals
without the help of an external sample-and-hold. In a conven­tional SAR type converter, regardless of its speed, the input
must remain stable to at least 1/2 LSB throughout the conversion
process if rated accuracy is to be maintained. Consequently, for
many high speed signals, this signal must be externally sampled
and held stationary during the conversion. The AD7824/AD7828
input comparators, by nature of their input switching, inherently
accomplish this sample-and-hold function. Although the conver­sion time for AD7824/AD7828 is 2 µs, the time for which any
selected analog input must be 1/2 LSB stable is much smaller.
The AD7824/AD7828 tracks the selected input channel for
approximately 1 µs after conversion start. The value of the analog
input at that instant (1 µs from conversion start) is the measured
value. This value is then used in the least significant flash to
generate the lower four bits of data.

SINUSOIDAL INPUTS

The AD7824/AD7828 can measure input signals with slew rates
as high as 157 mV/µs to the rated specifications. This means that
the analog input frequency can be up to 10 kHz without the aid
of an external sample-and-hold. Furthermore, the AD7828 can
measure eight 10 kHz signals without a sample-and-hold. The
Nyquist criterion requires that the sampling rate be twice the
input frequency (i.e., 2 × 10 kHz). This requires an ideal anti-
aliasing filter with an infinite roll-off. To ease the problem of
antialiasing filter design, the sampling rate is usually much greater
than the Nyquist criterion. The maximum sampling rate (F

MAX

)

for the AD7824/AD7828 can be calculated as follows:

1

=

tt

+

CRD P

=

EE

26056

–.–

C
2pF

R

350⍀

S2

ON

31pF

R

S

AIN1

V

IN

R MUX

800⍀

C

S1

12pF

Figure 9. RC Network Model

The time for which the input comparators track the analog input
is approximately 1 µs at the start of conversion. Because of input
transients on the analog inputs, it is recommended that a source

F

MAX

F

MAX

t

= AD7824/AD7828 Conversion Time

CRD

= Minimum Delay Between Conversion

t

P

This permits a maximum sampling rate of 50 kHz for each of
the eight channels when using the AD7828 and 100 kHz for
each of the four channels when using the AD7824.

impedance no greater than 100 Ω be connected to the analog
inputs. The output impedance of an op amp is equal to the open
loop output impedance divided by the loop gain at the frequency of

REV. F

–7–

1

+

kHz

=

400

AD7824/AD7828

www.BDTIC.com/ADI

UNIPOLAR OPERATION

The analog input range for any channel of the AD7824/AD7828 is
0 V to 5 V as shown in the unipolar operational diagram of
Figure 10. Figure 11 shows the designed code transitions that
occur midway between successive integer LSB values (i.e., 1/2 LSB,
3/2 LSB, 5/2 LSB, FS 3/2 LSBs). The output code is natural
binary with 1 LSB = FS/256 = (5/256) V = 19.5 mV.

REF

V

V

DD

V

(+)

REF

5V

IN

AIN1

V

REF

GND

AD7824*
AD7828*

(–)

DB7

DB0

5V

47␮F0.1␮F

V

0V TO 5V

ADDITIONAL PINS OMITTED FOR CLARITY.

*

ONLY CHANNEL 1 SHOWN.

Figure 10. AD7824/AD7828 Unipolar 0 V to 5 V Operation

FULL-SCALE

TRANSITION

11111111

11111110

11111101

FS

1LSB =

OUTPUT CODE

00000011

00000010

00000001

00000000

0

1LSB 2LSB 3LSB

AIN, INPUT VOLTAGE – LSB

256

FS

FS – 1LSB

Figure 11. Ideal Input/Output Transfer Characteristic for
Unipolar 0 V to 5 V Operation

BIPOLAR OPERATION

The circuit of Figure 12 is designed for bipolar operation. An
AD544 op amp conditions the signal input (V

) so that only

IN

positive voltages appear at AIN1. The closed loop transfer func­tion of the op amp for the resistor values shown is given below:

AIN V Volts

1 =−

25 0625..

()

IN

The analog input range is ±4 V and the LSB size is 31.25 mV.
The output code is complementary offset binary. The ideal
input/output characteristic is shown in Figure 13.

25k⍀

40k⍀

V

IN

27k⍀

5V

5V

ADDITIONAL PINS OMITTED FOR CLARITY.

*

ONLY CHANNEL 1 SHOWN.

12k⍀

AD544

47␮F0.1␮F

AIN1

AD7824*
AD7828*

V

REF

V

DD

V

REF

GND

(+)

(–)

DB7

DB0

5V

Figure 12. AD7824/AD7828 Bipolar ±4 V Operation

11111111

11111110

11111101

10000010

10000001

10000000

01111111

OUTPUT CODE

01111110

00000010

00000001

00000000

–FS

2

+ 1LSB

0V

AIN, INPUT VOLTAGE – LSB

FS = 8V
1LSB = FS/256

+FS

2

Figure 13. Ideal Input/Output Transfer Characteristic for

±

4 V Operation

TIMING AND CONTROL

The AD7824/AD7828 has two digital inputs for timing and
control. These are Chip Select (CS) and Read (RD). A READ
operation brings CS and RD low, which starts a conversion on
the channel selected by the multiplexer address inputs (see
Table I). There are two modes of operation as outlined by the
timing diagrams of Figures 14 and 15. Mode 0 is designed for
microprocessors that can be driven into a WAIT state. A
READ operation (i.e., CS and RD are taken low) starts a con­version and data is read when conversion is complete. Mode l
does not require microprocessor WAIT states. A READ operation
initiates a conversion and reads the previous conversion results.

Table I. Truth Table for Input Channel Selection

AD7824 AD7828

A1 A0 A2 A1 A0 Channel

00 000 AIN1
01 001 AIN2
10 010 AIN3
11 011 AIN4

100 AIN5
101 AIN6
110 AIN7
111 AIN8

–8–

REV. F

AD7824/AD7828

www.BDTIC.com/ADI

MODE 0

Figure 14 shows the timing diagram for Mode 0 operation. This
mode can only be used for microprocessors that have a WAIT
state facility, whereby a READ instruction cycle can be extended
to accommodate slow memory devices. A READ operation brings
CS and RD low, which starts a conversion. The analog multiplexer
address inputs must remain valid while CS and RD are low. The
data bus (DB7–DB0) remains in the three-state condition until
conversion is complete. There are two converter status outputs on
the AD7824/AD7828, interrupt (INT) and ready (RDY), which
can be used to drive the microprocessor READY/WAIT input.
The RDY is an open-drain output (no internal pull-up device) that
goes low on the falling edge of CS and goes high impedance at the
end of conversion when the 8-bit conversion result appears on the
data outputs. If the RDY status is not required, the external
pull-up resistor can be omitted and the RDY output tied to GND.
The INT goes low when conversion is complete and returns high
on the rising edge of CS or RD.

CS

t

CSS

RD

t

t

AS

RDY

t

CRD

HIGH IMPEDANCE

ADDRESS

VA LI D

t

ACC2

ANALOG
CHANNEL
ADDRESS

RDY

INT

DATA

MODE 1

Mode 1 operation is designed for applications where the micropro­cessor is not forced into a WAIT state. A READ operation takes
CS and RD low, which triggers a conversion (see Figure 15). The
multiplexer address inputs are latched on the rising edge of RD.
Data from the previous conversion is read from the three-state
data outputs (DB7–DB0). This data may be disregarded if not
required. Note that the RDY output (open drain output) does
not provide any status information in this mode and must be
connected to GND. At the end of conversion, INT goes low. A
second READ operation is required to access the new conversion
result. This READ operation latches a new address into the multi­plexer inputs and starts another conversion. INT returns high at the
end of the second READ operation, when CS or RD returns high.
A delay of 2.5 µs must be allowed between READ operations.

t

t

t

AH

INTH

DH

t

CSS

t

P

t

AS

ADDRESS

VA LI D

t

CSH

DATA

VA LI D

CS

RD

ANALOG
CHANNEL
ADDRESS

INT

DATA

t

CSS

t

ACC1

Figure 14. Mode 0 Timing Diagram

t

RD

t

AS

ADDRESS

VA LI D

t

INTH

OLD

VA LI D

t

CRD

t

CSH

t

AH

t

DH

t

CSS

t

t

ACC1

P

Figure 15. Mode 1 Timing Diagram

t

RD

t

AS

ADDRESS

VA LI D

t

INTH

NEW

VA LI D

t

CSH

t

AH

t

DH

REV. F

–9–

AD7824/AD7828

www.BDTIC.com/ADI

MICROPROCESSOR INTERFACING

The AD7824/AD7828 is designed to interface to microprocessors
as Read Only Memory (ROM). Analog channel selection, con­version start, and data read operations are controlled by CS, RD,
and the channel address inputs. These signals are common to
all memory peripheral devices.

Z80 MICROPROCESSOR

Figure 16 shows a typical AD7824/AD7828–Z80 interface. The
AD7824/AD7828 is operating in Mode 0. Assume the ADC is
assigned a memory block starting at address C000. The follow­ing LOAD instruction to any of the addresses listed in Table II
will start a conversion of the selected channel and read the
conversion result.

LD B, (C000)

At the beginning of the instruction cycle when the ADC
address is selected, RDY asserts the WAIT input so that the
Z80 is forced into a WAIT state. At the end of conversion,
RDY returns high and the conversion result is placed in the B
register of the microprocessor.

A15

ADDRESS BUS

A0

ADDRESS

EN

DECODE

5V

5k⍀

DATA BU S

LINEAR CIRCUITRY OMITTED FOR CLARITY.
FOR THE AD7828 ONLY

Z80

MREQ

WAIT

RD

D7

D0

*

**

A0 A1 A2**

CS

RDY

RD

DB7

DB0

A0

AD7824*
AD7828*

A2

A1

Figure 16. AD7824/AD7828–Z80 lnterface

Table II. Address Channel Selection

AD7824 AD7828

Address Channel Channel

C000 1 1
C001 2 2
C002 3 3
C003 4 4
C004 5
C005 6
C006 7
C007 8

to any of the addresses in Table II starts a conversion and reads
the conversion result.

MOVE × B $C000, D0

Once conversion has begun, the MC68000 inserts WAIT states
until INT goes low, asserting DTACK at the end of conversion.
The microprocessor then places the conversion results into the
D0 register.

MC68000

DTACK

A23

ADDRESS BUS

A1

AS

R/W

D7

D0

*

LINEAR CIRCUITRY OMITTED FOR CLARITY.

**

FOR THE AD7828 ONLY

ADDRESS

EN

DECODE

CLR

7474

D

CK

Q

DATA BU S

5V

5k⍀

A0

A0 A1 A2**

CS

RD

RDY

DB7

DB0

A1

AD7824*
AD7828*

A2

Figure 17. AD7824/AD7828–MC68000 Interface

TMS32010 MICROCOMPUTER

A TMS32010 interface is shown in Figure 18. The AD7824/
AD7828 is operating in Mode 1 (i.e., no µP WAIT states). The
ADC is mapped at a port address. The following I/O instruction
starts a conversion and reads the previous conversion result into
the accumulator.

IN, A PA (PA = PORT ADDRESS)

The port address (000 to 111) selects the analog channel to be
converted. When conversion is complete, a second I/O instruc­tion (IN, A PA) reads the up-to-date data into the accumulator
and starts another conversion. A delay of 2.5 µs must be allowed
between conversions.

TMS32010

PA 2

PA 1

PA 0

MEN

DEN

D7

DATA BU S

D0

A2**

A1

A0

CS

RD

DB7

DB0

AD7824*
AD7828*

MC68000 MICROPROCESSOR

Figure 17 shows an MC68000 interface. The AD7824/AD7828
is operating in Mode 0. Assume the ADC is again assigned a
memory block starting at address C000. A MOVE instruction

*

LINEAR CIRCUITRY OMITTED FOR CLARITY.

**

FOR THE AD7828 ONLY

Figure 18. AD7824/AD7828–TMS32010 Interface

–10–

REV. F

AD7824/AD7828

www.BDTIC.com/ADI

5V

SPEECH

INPUT

AMP

BAND-PASS

FILTER 1

BAND-PASS

FILTER 2

BAND-PASS

FILTER 7

BAND-PASS

FILTER 8

5V

AIN1

AIN2

AIN7

AIN8

V

REF

AD7828

(+)

V

REF

V

DD

CS
RD

DB7

DATA

DB0

A2
A1
A0

GND

(–)

Figure 19. Speech Analysis Using Real-Time Filtering

OUTLINE DIMENSIONS

24-Lead Plastic Dual-in-Line Package [PDIP]

Dimensions shown in inches and (millimeters)

1.185 (30.01)

1.165 (29.59)

1.145 (29.08)

24

1

0.180

(4.57)

MAX

0.150 (3.81)

0.130 (3.30)

0.110 (2.79)

0.022 (0.56)

0.018 (0.46)

0.014 (0.36)

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

0.100
(2.54)

BSC

COMPLIANT TO JEDEC STANDARDS MO-095AG

(N-24)

13

12

0.015 (0.38) MIN

0.060 (1.52)

0.050 (1.27)

0.045 (1.14)

5V

V

AIN1
AIN2
AIN3
AIN4

V

REF

V

REF

GND

DD

CS

AD7824

(+)
(–)

RD

INT

DB7

DB0

SAMPLE

PULSE

A1

A0

WR

DB7

DB0

A1

A0

15V

V

DD

AD7226

V

SS

V

V

OUT

V

OUT

V

OUT

V

OUT

DGND
AGND

REF

10V

A

1

V

O

B

2

V

O

C

3

V

O

V

D

4

O

Figure 20. 4-Channel Fast Infinite Sample-and-Hold

0.295 (7.49)

0.285 (7.24)

0.275 (6.99)

0.325 (8.26)

0.310 (7.87)

SEATING
PLANE

0.300 (7.62)

0.015 (0.38)

0.010 (0.25)

0.008 (0.20)

0.150 (3.81)

0.135 (3.43)

0.120 (3.05)

28-Lead Plastic Dual-in-Line Package [PDIP]

(N-28)

Dimensions shown in inches and (millimeters)

1.565 (39.7)

1.380 (35.1)

REV. F

0.250 (6.35)
MAX

0.200 (5.05)

0.115 (2.93)

28

1

0.100 (2.54)
BSC

0.022 (0.558)

0.014 (0.356)

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

COMPLIANT TO JEDEC STANDARDS MS-011AB

0.015 (0.39)
MIN

0.70 (1.77)

0.30 (0.77)

–11–

15

14

0.580 (14.73)

0.485 (12.32)

SEATING
PLANE

0.625 (15.87)

0.600 (15.24)

0.015 (0.381)

0.008 (0.204)

0.195 (4.95)

0.125 (3.18)

AD7824/AD7828

www.BDTIC.com/ADI

OUTLINE DIMENSIONS

24-Lead Standard Small Outline Package [SOIC]

Wide Body

(R-24)

Dimensions shown in millimeters and (inches)

15.60 (0.6142)

15.20 (0.5984)

24 13

1

0.30 (0.0118)

0.10 (0.0039)

COPLANARITY

0.10

1.27 (0.0500)
BSC

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

COMPLIANT TO JEDEC STANDARDS MS-013AD

0.51 (0.020)

0.33 (0.013)

7.60 (0.2992)

7.40 (0.2913)

12

2.65 (0.1043)

2.35 (0.0925)

SEATING
PLANE

10.65 (0.4193)

10.00 (0.3937)

0.32 (0.0126)

0.23 (0.0091)

28-Lead Standard Small Outline Package [SOIC]

Wide Body

(R-28)

Dimensions shown in millimeters and (inches)

18.10 (0.7126)

17.70 (0.6969)

0.75 (0.0295)

0.25 (0.0098)

8ⴗ
0ⴗ

ⴛ 45ⴗ

1.27 (0.0500)

0.40 (0.0157)

28 15

1

0.30 (0.0118)

0.10 (0.0039)

COPLANARITY

0.10

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

1.27 (0.0500)

COMPLIANT TO JEDEC STANDARDS MS-013AE

BSC

0.51 (0.0201)

0.33 (0.0130)

14

2.65 (0.1043)

2.35 (0.0925)

SEATING
PLANE

7.60 (0.2992)

7.40 (0.2913)

10.65 (0.4193)

10.00 (0.3937)

0.32 (0.0126)

0.23 (0.0091)

0.75 (0.0295)

0.25 (0.0098)

8ⴗ
0ⴗ

ⴛ 45ⴗ

1.27 (0.0500)

0.40 (0.0157)

–12–

REV. F

OUTLINE DIMENSIONS

www.BDTIC.com/ADI

24-Lead Ceramic DIP - Glass Hermetic Seal [CERDIP]

(Q-24)

Dimensions shown in inches and (millimeters)

AD7824/AD7828

0.005 (0.13)
MIN

24

PIN 1

112

0.200 (5.08)
MAX

0.200 (5.08)

0.125 (3.18)

0.023 (0.58)

0.014 (0.36)

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

0.098 (2.49)
MAX

1.280 (32.51) MAX

0.100

(2.54)

BSC

13

0.070 (1.78)

0.030 (0.76)

0.310 (7.87)

0.220 (5.59)

0.060 (1.52)

0.015 (0.38)

0.150 (3.81)
MIN

SEATING
PLANE

28-Lead Ceramic DIP - Glass Hermetic Seal [CERDIP]

(Q-28)

Dimensions shown in inches and (millimeters)

0.100
(2.54)

BSC

0.100 (2.54)
MAX

0.070 (1.78)

0.030 (0.76)

15

0.610 (15.49)

0.500 (12.70)

0.015 (0.38)
MIN

0.150 (3.81)
MIN

SEATING
PLANE

0.005 (0.13)
MIN

28

PIN 1

114

0.225(5.72)
MAX

0.200 (5.08)

0.125 (3.18)

0.026 (0.66)

0.014 (0.36)

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

1.490 (37.85) MAX

0.320 (8.13)

0.290 (7.37)

0.015 (0.38)

0.008 (0.20)

15

0

0.620 (15.75)

0.590 (14.99)

0.018 (0.46)

15

0

0.008 (0.20)

28-Terminal Ceramic Leaded Chip Carrier [LCC]

(E-28A)

Dimensions shown in inches and (millimeters)

0.300 (7.62)

1

REF

25

26

28

4 12

5

0.020 (0.51)
MIN

0.095 (2.41)

0.075 (1.90)

REV. F

0.458 (11.63)

0.442 (11.23)

0.100 (2.54)

0.064 (1.63)

0.458

(11.63)

SQ

MAX

SQ

0.088 (2.24)

0.054 (1.37)

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

0.05 (1.27)

0.075 (1.91)
REF

0.055 (1.40)

0.045 (1.14)

0.075
(1.91)

REF

BSC

19

11

18

BOTTOM

VIEW

–13–

0.028 (0.71)

0.022 (0.56)

0.15 (3.81)
REF

AD7824/AD7828

www.BDTIC.com/ADI

OUTLINE DIMENSIONS

28-Lead Shrink Small Outline Package [SSOP]

(RS-28)

Dimensions shown in millimeters

10.50

10.20

9.90

28 15

5.60

8.20

5.30

7.80

5.00

7.40

0.10
COPLANARITY

0.25

0.09

0.05
MIN

1

2.00 MAX

0.65

BSC

14

1.85

1.75

1.65

0.38

0.22

COMPLIANT TO JEDEC STANDARDS MO-150AH

SEATING

PLANE

8ⴗ
4ⴗ
0ⴗ

0.95

0.75

0.55

0.048 (1.22)

0.042 (1.07)

0.048 (1.22)

0.042 (1.07)

4

5

11

12

0.456 (11.582)

0.450 (11.430)

0.495 (12.57)

0.485 (12.32)

28-Lead Plastic Leaded Chip Carrier [PLCC]

(P-28A)

Dimensions shown in inches and (millimeters)

0.180 (4.57)

0.120 (3.05)

0.090 (2.29)

0.165 (4.19)

0.020 (0.51)
MIN

0.021 (0.53)

0.013 (0.33)

0.032 (0.81)

0.026 (0.66)

0.040 (1.02)

0.025 (0.64)

0.430 (10.9)

0.390 (9.9)

0.056 (1.42)

0.042 (1.07)

26

25

TOP VIEW

(PINS DOWN)

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

0.050
(1.27)
BSC

19

18

SQ

SQ

COMPLIANT TO JEDEC STANDARDS MO-047AB

BOTTOM

VIEW

(PINS UP)

–14–

REV. F

AD7824/AD7828

www.BDTIC.com/ADI

Revision History

Location Page

1/03—Data Sheet changed from REV. E to REV. F.

Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Edits to DIP/SOIC/SSOP, LCCC, AND PLCC Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Edit to Figure 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Edits to Circuit Information Basic Description section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Edits to Input Current section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Edit to Figure 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Edit to Figure 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4/02—Data Sheet changed from REV. D to REV. E.

Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

REV. F

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C01323–0–1/03 (F)

www.BDTIC.com/ADI

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PRINTED IN U.S.A.