ANALOG DEVICES AD7795 Service Manual

6-Channel, Low Noise, Low Power, 24-/16-Bit

Y

A

A

VDDA

∑-Δ ADC with On-Chip In-Amp and Reference

FEATURES

Up to 23 effective bits
RMS noise: 40 nV @ 4.17 Hz, 85 nV @ 16.7 Hz
Current: 400 μA typical
Power-down: 1 μA maximum
Low noise, programmable gain, instrumentation amp
Band gap reference with 4 ppm/°C drift typical
Update rate: 4.17 Hz to 470 Hz
Six differential analog inputs
Internal clock oscillator
Simultaneous 50 Hz/60 Hz rejection
Reference detect
Programmable current sources
On-chip bias voltage generator
Burnout currents
Low-side power switch
Power supply: 2.7 V to 5.25 V
Temperature range:

B grade: –40°C to +105°C

C grade: –40°C to +125°C
Independent interface power supply
24-lead TSSOP
3-wire serial interface

SPI®, QSPI™, MICROWIRE™, and DSP compatible

Schmitt trigger on SCLK

APPLICATIONS

Temperature measurement
Pressure measurement
Weigh scales
Strain gage transducers
Gas analysis

FUNCTIONAL BLOCK DIAGRAM

GND A

Industrial process control
Instrumentation
Blood analysis
Smart transmitters
Liquid/gas chromatography
6-digit DVM

GENERAL DESCRIPTION

The AD7794/AD7795 are low power, low noise, complete
analog front ends for high precision measurement applications.
They contain a low noise, 24-/16-bit ∑-Δ ADC with six
differential inputs. The on-chip low noise instrumentation
amplifier means that signals of small amplitude can be
interfaced directly to the ADC.

Each device contains a precision, low noise, low drift internal
band gap reference, and can also accept up to two external
differential references. Other on-chip features include
programmable excitation current sources, burnout currents,
and a bias voltage generator that is used to set the common­mode voltage of a channel to AV
switch can be used to power down bridge sensors between
conversions, minimizing the system’s power consumption. The
AD7794/AD7795 can operate with either an internal clock or
an external clock. The output data rate from each part can vary
from 4.17 Hz to 470 Hz.

Both parts operate with a power supply from 2.7 V to 5.25 V.
The B-grade parts (AD7794 and AD7795) are specified for a
temperature range of −40°C to +105°C while the C-grade part
(AD7794) is specified for a temperature range of −40°C to
+125°C. They consume a current of 400 μA typical and are
housed in a 24-lead TSSOP.

IN4(+)/REFIN2( +) REFIN1(+)AIN4(–)/REFIN2(–) REFIN1(–)

AD7794/AD7795

/2. The low-side power

DD

V

AIN1(+)
AIN1(–)
AIN2(+)
AIN2(–)
AIN3(+)

AIN3(–)
IN5(+)/IOUT2
IN5(–)/IOUT1

AIN6(+)/P1
AIN6(–)/P2

PSW

GND

BIAS

MUX

V

GND

DD

V

DD

TEMP

SENSOR

BAND GAP

REFERENCE

IN-AMPBUF

INTERNAL

CLOCK

ADC

CLK

GND

Σ-Δ

Figure 1.

Rev. D

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
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Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2004–2007 Analog Devices, Inc. All rights reserved.

REFERENCE

DETECT

SERIAL

INTERFACE

AND

LOGIC

CONTROL

AD7794/AD7795

AD7794: 24-BIT ADC
AD7795: 16-BIT ADC

DOUT/RD

DIN

SCLK

CS

DV

DD

04854-001

AD7794/AD7795

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Characteristics..................................................................... 8

Timing Diagrams.............................................................................. 9

Absolute Maximum Ratings.......................................................... 10

ESD Caution................................................................................ 10

Pin Configuration and Function Descriptions........................... 11

RMS Noise and Resolution Specifications ..................................13

Chop Enabled.............................................................................. 13

Chop Disabled ............................................................................ 15

Typical Performance Characteristics ........................................... 16

On-Chip Registers.......................................................................... 17

Communications Register......................................................... 17

Status Register ............................................................................. 18

Mode Register ............................................................................. 19

Configuration Register .............................................................. 22

Data Register ............................................................................... 24

ID Register................................................................................... 24

IO Register................................................................................... 24

Offset Register............................................................................. 25

Full-Scale Register ...................................................................... 25

ADC Circuit Information.............................................................. 26

Overview ..................................................................................... 26

Digital Interface.......................................................................... 28

Circuit Description......................................................................... 31

Analog Input Channel ............................................................... 31

Instrumentation Amplifier........................................................ 31

Bipolar/Unipolar Configuration .............................................. 31

Data Output Coding .................................................................. 32

Burnout Currents....................................................................... 32

Excitation Currents .................................................................... 32

Bias Voltage Generator .............................................................. 32

Reference ..................................................................................... 32

Reference Detect......................................................................... 33

Reset ............................................................................................. 33

AV

Monitor ............................................................................. 33

DD

Calibration................................................................................... 33

Grounding and Layout .............................................................. 34

Applications Information.............................................................. 35

Flowmeter.................................................................................... 35

Outline Dimensions ....................................................................... 36

Ordering Guide .......................................................................... 36

REVISION HISTORY

3/07—Rev. C to Rev. D

Changes to Specifications Endnote 1............................................. 7

Changes to Status Register Section .............................................. 18

Changes to Ordering Guide.......................................................... 36

10/06—Rev. B to Rev. C

Updated Format..................................................................Universal

Added AD7794 C-Grade Part...........................................Universal

Changes to Specifications................................................................ 3

Changes to Ordering Guide.......................................................... 36

6/06—Rev. A to Rev. B

Added AD7795 ...................................................................Universal

Changes to Features.......................................................................... 1

Changes to Table 1............................................................................ 3

Changes to RMS Noise and Resolution

Specifications Section..................................................................... 12

Changes to Table 19........................................................................ 20

Changes to ADC Circuit Information Section........................... 25

Changes to Ordering Guide.......................................................... 35

Rev. D | Page 2 of 36

4/05—Rev. 0 to Rev. A

Changes to Absolute Maximum Ratings........................................9

Changes to Figure 21...................................................................... 25

Changes to Data Output Coding Section.................................... 28

Changes to Calibration Section.................................................... 30

Changes to Ordering Guide.......................................................... 33

10/04—Revision 0: Initial Version

AD7794/AD7795

SPECIFICATIONS

AVDD = 2.7 V to 5.25 V, DVDD = 2.7 V to 5.25 V, GND = 0 V, all specifications T

Table 1.

Parameter1 AD7794/AD7795 Unit Test Conditions/Comments
CHOP ENABLED

Output Update Rate 4.17 to 470 Hz nom Settling time = 2/output update rate
No Missing Codes

2

AD7794 24 Bits min f

AD7795 16 Bits min
Resolution See the RMS Noise and Resolution Specifications section
RMS Noise and Update Rates See the RMS Noise and Resolution Specifications section
Integral Nonlinearity ±15

ppm of FSR
max

Offset Error

3

±1 μV typ
Offset Error Drift vs. Temperature4±10 nV/°C typ
Full-Scale Error3, 5 ±10 μV typ
Gain Drift vs. Temperature

4

±1 ppm/°C typ Gain = 1 to 16, external reference
±3 ppm/°C typ Gain = 32 to 128, external reference
Power Supply Rejection 100 dB min AIN = 1 V/gain, gain ≥ 4, external reference

ANALOG INPUTS

Differential Input Voltage Ranges ±VREF/gain V nom

Absolute AIN Voltage Limits

2

Unbuffered Mode GND − 30 mV V min Gain = 1 or 2
AVDD + 30 mV V max
Buffered Mode GND + 100 mV V min Gain = 1 or 2
AVDD − 100 mV V max
In-Amp Active GND + 300 mV V min Gain = 4 to 128

AVDD − 1.1 V max

Common-Mode Voltage, V

CM

0.5 V min VCM = (AIN(+) + AIN(−))/2, gain = 4 to 128

Analog Input Current

Buffered Mode or In-Amp
Active

Average Input Current

2

AD7794B/AD7795B ±1 nA max Gain = 1 or 2, update rate < 100 Hz
±250 pA max Gain = 4 to 128, update rate < 100 Hz
±1 nA max AIN6(+)/AIN6(−)

AD7794C ±3 nA max Gain = 1 or 2, update rate < 100 Hz
±2 nA max Gain = 4 to 128, update rate < 100 Hz
±3 nA max AIN6(+)/AIN6(−)
Average Input Current Drift ±2 pA/°C typ

Unbuffered Mode Gain = 1 or 2

Average Input Current ±400 nA/V typ Input current varies with input voltage
Average Input Current Drift ±50 pA/V/°C typ

Normal Mode Rejection2,

6

Internal Clock

@ 50 Hz, 60 Hz 65 dB min 80 dB typ, 50 ± 1 Hz, 60 ± 1 Hz, FS[3:0] = 1010
@ 50 Hz 80 dB min 90 dB typ, 50 ± 1 Hz, FS[3:0] = 1001
@ 60 Hz 90 dB min 100 dB typ, 60 ± 1 Hz, FS[3:0] = 1000

External Clock

@ 50 Hz, 60 Hz 80 dB min 90 dB typ, 50 ± 1 Hz, 60 ± 1 Hz, FS[3:0] = 1010
@ 50 Hz 94 dB min 100 dB typ, 50 ± 1 Hz, FS[3:0] = 1001
@ 60 Hz 90 dB min 100 dB typ, 60 ± 1 Hz, FS[3:0] = 1000

Rev. D | Page 3 of 36

to T

MIN

MAX

ADC

V

REF

gain = 1 to 128

, unless otherwise noted.

≤ 242 Hz

= REFIN(+) − REFIN(−), or internal reference,

AD7794/AD7795

Parameter1 AD7794/AD7795 Unit Test Conditions/Comments

Common-Mode Rejection

AD7794B/AD7795B

@ DC 100 dB min AIN = 1 V/gain, gain ≥ 4
@ 50 Hz, 60 Hz
@ 50 Hz, 60 Hz

AD7794C

@ DC 97 dB min AIN = 1 V/gain, gain ≥ 4
@ 50 Hz, 60 Hz
@ 50 Hz, 60 Hz

CHOP DISABLED

Output Update Rate 4.17 to 470 Hz nom Settling time = 1/output update rate
No Missing Codes
AD7794 24 Bits min f
AD7795 16 Bits min
Resolution See the RMS Noise and Resolution Specifications section
RMS Noise and Update Rates See the RMS Noise and Resolution Specifications section
Integral Nonlinearity ±15

Offset Error

3

Offset Error Drift vs. Temperature4±100/gain nV/°C typ Gain = 1 to 16
10 nV/°C typ Gain = 32 to 128
Full-Scale Error3,
Gain Drift vs. Temperature
±3 ppm/°C typ Gain = 32 to 128, external reference
Power Supply Rejection 100 dB typ AIN = 1 V/gain, gain ≥ 4, external reference

ANALOG INPUTS

Differential Input Voltage Ranges ±V

Absolute AIN Voltage Limits

Unbuffered Mode GND − 30 mV V min Gain = 1 or 2
AVDD + 30 mV V max
Buffered Mode GND + 100 mV V min Gain = 1 or 2
AVDD − 100 mV V max
In-Amp Active GND + 300 mV V min Gain = 4 to 128
AVDD − 1.1 V max
Common-Mode Voltage, V

Analog Input Current

Buffered Mode or In-Amp
Active

Average Input Current

AD7794B/AD7795B ±1 nA max Gain = 1 or 2
±250 pA max Gain = 4 to 128
±1 nA max AIN6(+)/AIN6(−)

AD7794C ±3 nA max Gain = 1 or 2
±2 nA max Gain = 4 to 128
±3 nA max AIN6(+)/AIN6(−)
Average Input Current Drift ±2 pA/°C typ

Unbuffered Mode Gain = 1 or 2

Average Input Current ±400 nA/V typ Input current varies with input voltage
Average Input Current Drift ±50 pA/V/°C typ

2

2

2

2

100 dB min 50 ± 1 Hz, 60 ± 1 Hz, FS[3:0] = 1010
100 dB min 50 ± 1 Hz, FS[3:0] = 1001; 60 ± 1 Hz, FS[3:0] = 1000

97 dB min 50 ± 1 Hz, 60 ± 1 Hz, FS[3:0] = 1010
97 dB min 50 ± 1 Hz, FS[3:0] = 1001; 60 ± 1 Hz, FS[3:0] = 1000

2

≤ 123 Hz

ADC

ppm of FSR
max

±100/gain μV typ Without calibration

5

4

±10 μV typ
±1 ppm/°C typ Gain = 1 to 16, external reference

/gain V nom

REF

= REFIN(+) − REFIN(−), or internal reference,

V

REF

gain = 1 to 128

2

CM

0.2 + (gain/2 × (AIN(+) −

V min AMP − CM = 1, VCM = (AIN(+) + AIN(–))/2, gain = 4 to 128

AIN(−)))

− 0.2 − (gain/2 ×

AV

DD

V max

(AIN(+) − AIN(−)))

2

Rev. D | Page 4 of 36

AD7794/AD7795

Parameter1 AD7794/AD7795 Unit Test Conditions/Comments

Normal Mode Rejection2,

Internal Clock

@ 50 Hz, 60 Hz 60 dB min 70 dB typ, 50 ± 1 Hz, 60 ± 1 Hz, FS[3:0] = 1010
@ 50 Hz 78 dB min 90 dB typ, 50 ± 1 Hz, FS[3:0] = 1001
@ 60 Hz 86 dB min 100 dB typ, 60 ± 1 Hz, FS[3:0] = 1000

External Clock

@ 50 Hz, 60 Hz 60 dB min 70 dB typ, 50 ± 1 Hz, 60 ± 1 Hz, FS[3:0] = 1010
@ 50 Hz 94 dB min 100 dB typ, 50 ± 1 Hz, FS[3:0] = 1001
@ 60 Hz 90 dB min 100 dB typ, 60 ± 1 Hz, FS[3:0] = 1000

Common-Mode Rejection

AD7794B/AD7795B

@ DC 100 dB min AIN = 1 V/gain, with gain = 4, AMP-CM Bit = 1
@ 50 Hz, 60 Hz
@ 50 Hz, 60 Hz

AD7794C

@ DC 97 dB min AIN = 1 V/gain, with gain = 4, AMP-CM Bit = 1
@ 50 Hz, 60 Hz

@ 50 Hz, 60 Hz
CHOP ENABLED or DISABLED
REFERENCE INPUT

Internal Reference

Internal Reference Initial
Accuracy

Internal Reference Drift
15 ppm/°C max
Power Supply Rejection 85 dB typ

External Reference

External REFIN Voltage 2.5 V nom REFIN = REFIN(+) − REFIN(−)
Reference Voltage Range
AV

Absolute REFIN Voltage Limits2GND − 30 mV V min
AVDD + 30 mV V max
Average Reference Input

Current
Average Reference Input

Current Drift
Normal Mode Rejection
Common-Mode Rejection 100 dB typ
Reference Detect Levels 0.3 V min

0.65 V max NOXREF bit active if V
EXCITATION CURRENT SOURCES
(IEXC1 and IEXC2)

Output Current 10/210/1000 μA nom
Initial Tolerance at 25°C ±5 % typ
Drift 200 ppm/°C typ
Current Matching ±0.5 % typ Matching between IEXC1 and IEXC2, V
Drift Matching 50 ppm/°C typ
Line Regulation (AVDD) 2 %/V typ AVDD = 5 V ± 5%
Load Regulation 0.2 %/V typ

Output Compliance AVDD − 0.65 V max Current sources programmed to 10 μA or 210 μA
AVDD − 1.1 V max Current sources programmed to 1 mA
GND − 30 mV V min

6

2

2

2

2

100 dB min 50 ± 1 Hz, 60 ± 1 Hz, FS[3:0] = 1010
100 dB min 50 ± 1 Hz, FS[3:0] = 1001; 60 ± 1 Hz, FS[3:0] = 1000

97 dB min 50 ± 1 Hz, 60 ± 1 Hz, FS[3:0] = 1010
97 dB min 50 ± 1 Hz, FS[3:0] = 1001; 60 ± 1 Hz, FS[3:0] = 1000

1.17 ± 0.01% V min/max AV

2

2

4 ppm/°C typ

0.1 V min

DD

V max

= 4 V, TA = 25°C

DD

When V

= AVDD, the differential input must be

REF

limited to 0.9 × V

/gain if the in-amp is active

REF

400 nA/V typ

±0.03 nA/V/°C typ

2

Same as for analog inputs

< 0.3 V

REF

OUT

= 0 V

Rev. D | Page 5 of 36

AD7794/AD7795

Parameter1 AD7794/AD7795 Unit Test Conditions/Comments

BIAS VOLTAGE GENERATOR

V

BIAS

V

Generator Start-Up Time ms/nF typ

BIAS

TEMPERATURE SENSOR

Accuracy ±2 °C typ Applies if user calibrates the temperature sensor
Sensitivity 0.81 mV/°C typ

LOW-SIDE POWER SWITCH

R

ON

9 Ω max AVDD = 3 V
Allowable Current

2

DIGITAL OUTPUTS (P1 and P2)

VOH, Output High Voltage
VOL, Output Low Voltage
VOH, Output High Voltage
VOL, Output Low Voltage

2

2

2

2

INTERNAL/EXTERNAL CLOCK

Internal Clock

Frequenc y

2

Duty Cycle 50:50 % typ

External Clock

Frequency 64 kHz nom

Duty Cycle 45:55 to 55:45 % typ

LOGIC INPUTS

2

CS

V

, Input Low Voltage 0.8 V max DVDD = 5 V

INL

0.4 V max DVDD = 3 V
V

, Input High Voltage 2.0 V min DVDD = 3 V or 5 V

INH

SCLK (Schmitt-Triggered Input),
CLK, and DIN

2

AD7794B/AD7795B

VT(+) 1.4/2 V min/max DVDD = 5 V
VT(−) 0.8/1.7 V min/max DVDD = 5 V
VT(+) to VT(−) 0.1/0.17 V min/max DVDD = 5 V
VT(+) 0.9/2 V min/max DVDD = 3 V
VT(−) 0.4/1.35 V min/max DVDD = 3 V
VT(+) to VT(−) 0.06/0.13 V min/max DVDD = 3 V

AD7794C

VT(+) 1.35/2.05 V min/max DVDD = 5 V
VT(−) 0.8/1.9 V min/max DVDD = 5 V
VT(+) to VT(−) 0.1/0.19 V min/max DVDD = 5 V
VT(+) 0.9/2 V min/max DVDD = 3 V
VT(−) 0.4/1.35 V min/max DVDD = 3 V

VT(+) to VT(−) 0.06/0.15 V min/max DVDD = 3 V
Input Currents ±10 μA max VIN = DVDD or GND
Input Capacitance 10 pF typ All digital inputs

AVDD/2 V nom

Dependent on the capacitance connected to AIN;

Figure 11

See

7 Ω max AVDD = 5 V

30 mA max Continuous current

AVDD − 0.6 V min AVDD = 3 V, I

0.4 V max AVDD = 3 V, I
4 V min AVDD = 5 V, I

0.4 V max AVDD = 5 V, I

64 ± 3%

kHz

= 100 μA

SOURCE

= 100 μA

SINK

= 200 μA

SOURCE

= 800 μA

SINK

min/max

A 128 kHz external clock can be used if the divide-by-2
function is used (Bit CLK1 = CLK0 = 1)

Applies for external 64 kHz clock, a 128 kHz clock can
have a less stringent duty cycle

Rev. D | Page 6 of 36

AD7794/AD7795

Parameter1 AD7794/AD7795 Unit Test Conditions/Comments

LOGIC OUTPUT (INCLUDING CLK)

VOH, Output High Voltage
VOL, Output Low Voltage
VOH, Output High Voltage
VOL, Output Low Voltage
Floating-State Leakage Current ±10 μA max
Floating-State Output Capacitance 10 pF typ
Data Output Coding Offset binary

SYSTEM CALIBRATION

Full-Scale Calibration Limit 1.05 × FS V max
Zero-Scale Calibration Limit −1.05 × FS V min
Input Span 0.8 × FS V min

2.1 × FS V max
POWER REQUIREMENTS

Power Supply Voltage

AVDD to GND 2.7/5.25 V min/max
DVDD to GND 2.7/5.25 V min/max

Power Supply Currents

IDD Current 140 μA max

185 μA max

400 μA max

500 μA max

IDD (Power-Down Mode) 1 μA max AD7794B, AD7795B

2 μA max AD7794C

1

Temperature range: B Grade: −40°C to +105°C, C Grade: −40°C to +125°C. At the 19.6 Hz and 39.2 Hz update rates, the INL, power supply rejection (PSR), common-

mode rejection (CMR), and normal mode rejection (NMR) do not meet the data sheet specification if the voltage on the AIN(+) or AIN(−) pins exceeds AVDD – 1.6 V
typically. In addition, the offset error and offset error drift degrade at these update rates when chopping is disabled. When this voltage is exceeded, the INL, for
example, is reduced to 18 ppm of FS typically while the PSR is reduced to 69 dB typically. Therefore, for guaranteed performance at these update rates, the absolute
voltage on the analog input pins needs to be below AVDD − 1.6 V.

2

Specification is not production tested but is supported by characterization data at initial product release.

3

Following a calibration, this error is in the order of the noise for the programmed gain and update rate selected.

4

Recalibration at any temperature removes these errors.

5

Full-scale error applies to both positive and negative full-scale, and applies at the factory calibration conditions (AVDD = 4 V, gain = 1, TA = 25°C).

6

FS[3:0] are the four bits used in the mode register to select the output word rate.

7

Digital inputs equal to DVDD or GND with excitation currents and bias voltage generator disabled.

2

2

2

2

2

7

DVDD − 0.6 V min DVDD = 3 V, I

0.4 V max DVDD = 3 V, I
4 V min DVDD = 5 V, I

0.4 V max

DV

= 5 V, I

DD

= 100 μA

SOURCE

= 100 μA

SINK

= 200 μA

SOURCE

= 1.6 mA (DOUT/RDY), 800 μA (CLK)

SINK

110 μA typ @ AV

= 3 V, 125 μA typ @ AVDD = 5 V,

DD

unbuffered mode, external reference
130 μA typ @ AV

= 3 V, 165 μA typ @ AVDD = 5 V,

DD

buffered mode, gain = 1 or 2, external reference
300 μA typ @ AV

= 3 V, 350 μA typ @ AVDD = 5 V,

DD

gain = 4 to 128, external reference
400 μA typ @ AV

= 3 V, 450 μA typ @ AVDD = 5 V,

DD

gain = 4 to 128, internal reference

Rev. D | Page 7 of 36

AD7794/AD7795

TIMING CHARACTERISTICS

AVDD = 2.7 V to 5.25 V, DVDD = 2.7 V to 5.25 V, GND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DVDD, unless otherwise noted.

Table 2.

Parameter1,

t

3

t

4

2

Limit at T

MIN

, T

(B Version) Unit Conditions/Comments

MAX

100 ns min SCLK high pulse width
100 ns min SCLK low pulse width

Read Operation

t

1

0 ns min

CS falling edge to DOUT/RDY active time
60 ns max DVDD = 4.75 V to 5.25 V
80 ns max DVDD = 2.7 V to 3.6 V

3

t

2

0 ns min SCLK active edge to data valid delay

4

60 ns max DVDD = 4.75 V to 5.25 V
80 ns max DVDD = 2.7 V to 3.6 V

6

t

55,

10 ns min

Bus relinquish time after

CS inactive edge
80 ns max
t

6

t

7

0 ns min
10 ns min

SCLK inactive edge to

CS inactive edge

SCLK inactive edge to DOUT/

RDY high

Write Operation

t

8

t

9

t

10

t

11

1

Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V.

2

See Figure 3 and Figure 4.

3

These numbers are measured with the load circuit shown in Figure 2 and defined as the time required for the output to cross the VOL or VOH limits.

4

SCLK active edge is falling edge of SCLK.

5

These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit shown in Figure 2. The measured number

is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the
true bus relinquish times of the part and, therefore, are independent of external bus loading capacitances.

6

RDY

returns high after a read of the ADC. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while
although care should be taken to ensure that subsequent reads do not occur close to the next output update. In continuous read mode, the digital word can be read
only once.

0 ns min

CS falling edge to SCLK active edge setup time
30 ns min Data valid to SCLK edge setup time
25 ns min Data valid to SCLK edge hold time
0 ns min

CS rising edge to SCLK edge hold time

4

RDY

is high,

I

(1.6mA WITH DVDD=5V,

SINK

100µA WITH DV

=3V)

DD

TO

OUTPUT

PIN

50pF

I

SOURCE

100µA WITH DV

1.6V

(200µA WI TH DVDD=5V,

=3V)

DD

Figure 2. Load Circuit for Timing Characterization

Rev. D | Page 8 of 36

04854-002

AD7794/AD7795

TIMING DIAGRAMS

CS (I)

t

t

1

DOUT/RDY (O)

SCLK (I)

t

2

I= INPUT, O= OUTPUT

MSB LSB

t

3

t

4

Figure 3. Read Cycle Timing Diagram

CS (I)

6

t

5

t

7

4854-003

t

11

4854-004

SCLK (I)

DIN (I)

I = INPUT, O = OUTPUT

t

8

t

9

t

10

MSB LSB

Figure 4. Write Cycle Timing Diagram

Rev. D | Page 9 of 36

AD7794/AD7795

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

AVDD to GND −0.3 V to +7 V
DVDD to GND −0.3 V to +7 V
Analog Input Voltage to GND −0.3 V to AVDD + 0.3 V
Reference Input Voltage to GND −0.3 V to AVDD + 0.3 V
Digital Input Voltage to GND −0.3 V to DVDD + 0.3 V
Digital Output Voltage to GND −0.3 V to DVDD + 0.3 V
AIN/Digital Input Current 10 mA
Operating Temperature Range

B Grade −40°C to +105°C

C Grade −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Maximum Junction Temperature 150°C
TSSOP

θJA Thermal Impedance 97.9°C/W

θJC Thermal Impedance 14°C/W
Lead Temperature, Soldering

Vapor Phase (60 sec) 215°C

Infrared (15 sec) 220°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. D | Page 10 of 36

AD7794/AD7795

A

A

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

SCLK

1

CLK

2

CS

3

NC

4

AD7794/

AIN1(+)

AIN1(–)

AIN2(+)

AIN2(–)

AIN3(+)

AIN3(–)

5

AD7795

6

TOP VIEW

7

(Not to Scale)

8

9

10

11

12

NC = NO CONNECT

IN6(+)/P1

IN6(–)/P2

Figure 5. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 SCLK

Serial Clock Input. This serial clock input is for data transfers to and from the ADC. The SCLK has a Schmitt­triggered input, making the interface suitable for opto-isolated applications. The serial clock can be
continuous with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous
clock with the information being transmitted to or from the ADC in smaller batches of data.

2 CLK

Clock In/Clock Out. The internal clock can be made available at this pin. Alternatively, the internal clock can
be disabled, and the ADC can be driven by an external clock. This allows several ADCs to be driven from a
common clock, allowing simultaneous conversions to be performed.

3

CS Chip Select Input. This is an active low logic input used to select the ADC. CS can be used to select the ADC in

systems with more than one device on the serial bus or as a frame synchronization signal in communicating
with the device. CS can be hardwired low, allowing the ADC to operate in 3-wire mode with SCLK, DIN, and

DOUT used to interface with the device.
4 NC No Connect.
5 AIN6(+)/P1

Analog Input/Digital Output Pin. AIN6(+) is the positive terminal of the differential analog input pair,

AIN6(+)/AIN6(−). This pin can also function as a general-purpose output bit referenced between AV
6 AIN6(−)/P2

Analog Input/Digital Output Pin. AIN6(−) is the negative terminal of the differential analog input pair,

AIN6(+)/AIN6(−). This pin can also function as a general-purpose output bit referenced between AV
7 AIN1(+) Analog Input. AIN1(+) is the positive terminal of the differential analog input pair, AIN1(+)/AIN1(−).
8 AIN1(−) Analog Input. AIN1(−) is the negative terminal of the differential analog input pair, AIN1(+)/AIN1(−).
9 AIN2(+) Analog Input. AIN2(+) is the positive terminal of the differential analog input pair, AIN2(+)/AIN2(−).
10 AIN2(−) Analog Input. AIN2(−) is the negative terminal of the differential analog input pair, AIN2(+)/AIN2(−).
11 AIN3(+) Analog Input. AIN3(+) is the positive terminal of the differential analog input pair, AIN3(+)/AIN3(−).
12 AIN3(−) Analog Input. AIN3(−) is the negative terminal of the differential analog input pair, AIN3(+)/AIN3(−).
13 REFIN1(+)

Positive Reference Input. An external reference can be applied between REFIN1(+) and REFIN1(−). REFIN1(+)

can lie anywhere between AV

and GND + 0.1 V. The nominal reference voltage, (REFIN1(+) − REFIN1(−)), is

DD

2.5 V, but the part functions with a reference from 0.1 V to AV
14 REFIN1(−) Negative Reference Input. This reference input can lie anywhere between GND and AVDD − 0.1 V.
15 AIN5(+)/IOUT2

Analog Input/Output of Internal Excitation Current Source. AIN5(+) is the positive terminal of the differential
analog input pair AIN5(+)/AIN5(−). Alternatively, the internal excitation current source can be made available at
this pin and is programmable so that the current can be 10 μA, 210 μA, or 1 mA. Either IEXC1 or IEXC2 can be
switched to this output.

16 AIN5(−)/IOUT1

Analog Input/Output of Internal Excitation Current Source. AIN5(−) is the negative terminal of the
differential analog input pair, AIN5(+)/AIN5(−). Alternatively, the internal excitation current source can be
made available at this pin and is programmable so that the current can be 10 μA, 210 μA, or 1 mA. Either
IEXC1 or IEXC2 can be switched to this output.

17 AIN4(+)/REFIN2(+)

Analog Input/Positive Reference Input. AIN4(+) is the positive terminal of the differential analog input pair
AIN4(+)/AIN4(−). This pin also functions as a positive reference input for REFIN2. REFIN2(+) can lie anywhere
between AV

and GND + 0.1 V. The nominal reference voltage (REFIN2(+) to REFIN2(−)) is 2.5 V, but the part

DD

functions with a reference from 0.1 V to AV

DIN

24

DOUT/RDY

23

DV

22

DD

AV

21

DD

20

GND

19

PSW

AIN4(–)/REFIN2(–)

18

AIN4(+)/REF IN2(+)

17

AIN5(–)/IO UT1

16

AIN5(+)/IOUT2

15

14

REFIN1(–)

13

REFIN1(+)

.

DD

4854-005

and GND.

DD

and GND.

DD

.

DD

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