ANALOG DEVICES AD7788 Service Manual

V

查询AD7788供应商

Low Power, 16-/24-Bit

FEATURES

AD7788: 16-bit resolution
AD7789: 24-bit resolution
Power

Supply: 2.5 V to 5.25 V operation
Normal: 75 µA maximum

Power-down: 1 µA maximum
RMS noise: 1.5 µV
AD7788: 16-bit p-p resolution
AD7789: 19-bit p-p resolution (21.5 bits effective)
Integral nonlinearity: 3.5 ppm typical
Simultaneous 50 Hz and 60 Hz rejection
Internal clock oscillator

monitor channel

V

DD

10-lead MSOP

INTERFACE

3-wire serial
SPI®, QSPI™, MICROWIRE™, and DSP compatible
Schmitt trigger on SCLK

APPLICATIONS

Smart transmitters
Battery applications
Portable instrumentation
Sensor measurement
Temperature measurement
Pressure measurement
Weigh scales
4 to 20 mA loops

Sigma-Delta ADC

AD7788/AD7789

FUNCTIONAL BLOCK DIAGRAM

REFIN(+) REFIN(–)

AD7788/
AD7789

AIN(+)

AIN(–)

*AD7788: 16-BIT ADC
AD7789: 24-BIT ADC

Σ-∆

ADC*

Figure 1.

GENERAL DESCRIPTION

The AD7788/AD7789 are low power, low noise, analog front
ends for low frequency measurement applications. The AD7789
contains a low noise 24-bit ∑-∆ ADC with one differential input.
The AD7788 is a 16-bit version of the AD7789.

The device operates from an internal clock. Therefore, the user
does not have to supply a clock source to the device. The output
data rate is 16.6 Hz, which gives simultaneous 50 Hz/60 Hz
rejection.

The part operates with a single power supply from 2.5 V to

5.25 V. When operating from a 3 V supply, the power dissipation
for the part is 225 µW maximum. The AD7788/AD7789 is
housed in a 10-lead MSOP.

GND

CLOCK

SERIAL

INTERFACE

AND

CONTROL

LOGIC

DD

DOUT/RDY

DIN

SCLK

CS

03539-0-001

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

www.analog.com

AD7788/AD7789

TABLE OF CONTENTS

AD7789—Specifications.................................................................. 3

ADC Circuit Information.............................................................. 14

AD7788—Specifications.................................................................. 4

AD7788/AD7789 Specifications..................................................... 5

Timing Characteristics..................................................................... 6

Absolute Maximum Ratings............................................................ 8

Pin Configuration and Function Descriptions............................. 9

Typical Performance Characteristics ...........................................10

On-Chip Registers.......................................................................... 11

Communications Register

(RS1, RS0 = 0, 0) ......................................................................... 11

Status Register
(RS1, RS0 = 0, 0; Power-on/Reset = 0x88 [AD7788]

and 0x8C [AD7789]).................................................................. 12

Mode Register

(RS1, RS0 = 0, 1; Power-on/Reset = 0x02)............................... 12

Data Register
(RS1, RS0 = 1, 1; Power-on/Reset = 0x0000 [AD7788]

and 0x000000 [AD7789]).......................................................... 13

Overview ..................................................................................... 14

Noise Performance ..................................................................... 14

Digital Interface.......................................................................... 14

Single Conversion Mode....................................................... 15

Continuous Conversion Mode............................................. 15

Continuous Read Mode ........................................................ 16

Circuit Description......................................................................... 17

Analog Input Channel ............................................................... 17

Bipolar/Unipolar Configuration .............................................. 17

Data Output Coding .................................................................. 17

Reference Input........................................................................... 17

VDD Monitor................................................................................ 18

Grounding and Layout .............................................................. 18

Outline Dimensions....................................................................... 19

REVISION HISTORY

Revision 0: Initial Version

Rev. 0 | Page 2 of 20

AD7788/AD7789

AD7789—SPECIFICATIONS1

Table 1. (VDD = 2.5 V to 5.25 V; REFIN(+) = 2.5 V; REFIN(–) = GND; GND = 0 V;
all specifications T

MIN

to T

Parameter AD7789B Unit Test Conditions/Comments

ADC CHANNEL SPECIFICATION

Output Update Rate 16.6 Hz nom
ADC CHANNEL

No Missing Codes2 24 Bits min

Resolution 19 Bits p-p

Output Noise 1.5 µV rms typ

Integral Nonlinearity ±15 ppm of FSR max

Offset Error ±3 µV typ

Offset Error Drift vs. Temperature ±10 nV/°C typ

Full-Scale Error3 ±10 µV typ

Gain Drift vs. Temperature ±0.5 ppm/°C typ

Power Supply Rejection 90 dB min 100 dB typ, AIN = 1 V
ANALOG INPUTS

Differential Input Voltage Ranges ±REFIN V nom REFIN = REFIN(+) – REFIN(–)

Absolute AIN Voltage Limits2 GND – 30 mV V min
V

Analog Input Current Input current varies with input voltage.

Average Input Current2 ±400 nA/V typ
Average Input Current Drift ±50 pA/V/°C typ

Normal Mode Rejection2

@ 50 Hz, 60 Hz 65 dB min 50 ± 1 Hz, 60 ± 1 Hz

Common Mode Rejection AIN = 1 V

@ DC 90 dB min 100 dB typ
@ 50 Hz, 60 Hz2 100 dB min 50 ± 1 Hz, 60 ± 1 Hz

REFERENCE INPUT

REFIN Voltage 2.5 V nom REFIN = REFIN(+) – REFIN(–)

Reference Voltage Range2 0.1 V min
V

Absolute REFIN Voltage Limits2 GND – 30 mV V min
V

Average Reference Input Current 0.5 µA/V typ

Average Reference Input Current Drift ±0.03 nA/V/°C typ

Normal Mode Rejection2

@ 50 Hz, 60 Hz 65 dB min 50 ± 1 Hz, 60 ± 1 Hz

Common Mode Rejection AIN = 1 V

@ DC 110 dB typ
@ 50 Hz, 60 Hz 110 dB typ 50 ± 1 Hz, 60 ± 1 Hz

1

Temperature Range –40°C to +105°C.

2

Specification is not production tested, but is supported by characterization data at initial product release.

3

Full-scale error applies to both positive and negative full scale and applies at the factory calibration conditions (VDD = 4 V).

, unless otherwise noted.)

MAX

DD

DD

DD

+ 30 mV V max

V max

+ 30 mV V max

Rev. 0 | Page 3 of 20

AD7788/AD7789

AD7788—SPECIFICATIONS1

Table 2. (VDD = 2.5 V to 5.25 V (B Grade); VDD = 2.7 V to 5.25 V (A Grade); REFIN(+) = 2.5 V; REFIN(–) = GND; GND = 0 V;
all specifications T

MIN

to T

Parameter AD7788A, B Unit Test Conditions/Comments

ADC CHANNEL SPECIFICATION

Output Update Rate 16.6 Hz nom

ADC CHANNEL

No Missing Codes2 16 Bits min
Resolution 16 Bits p-p
Output Noise 1.5 µV rms typ
Integral Nonlinearity ±15 ppm of FSR max B Grade
±50 ppm of FSR max A Grade
Offset Error ±3 µV typ
Offset Error Drift vs. Temperature ±10 nV/°C typ
Full-Scale Error3 ±10 µV typ
Gain Drift vs. Temperature ±0.5 ppm/°C typ
Power Supply Rejection 90 dB min B Grade
90 dB typ A Grade

ANALOG INPUTS

Differential Input Voltage Ranges ±REFIN V nom REFIN = REFIN(+) – REFIN(–)
Absolute AIN Voltage Limits2 GND – 30 mV V min

V

Analog Input Current Input current varies with input voltage.

Average Input Current2 ±400 nA/V typ
Average Input Current Drift ±50 pA/V/°C typ

Normal Mode Rejection2

@ 50 Hz, 60 Hz 65 dB min B Grade, 50 ± 1 Hz, 60 ± 1 Hz
60 dB min A Grade, 50 ± 1 Hz, 60 ± 1 Hz

Common Mode Rejection AIN = 1 V

@ DC 90 dB min B Grade, 100 dB typ
90 dB typ A Grade
@ 50 Hz, 60 Hz2 100 dB min B Grade, 50 ± 1 Hz, 60 ± 1 Hz
100 dB typ A Grade, 50 ± 1 Hz, 60 ± 1 Hz

REFERENCE INPUT

REFIN Voltage 2.5 V nom REFIN = REFIN(+) – REFIN(–)
Reference Voltage Range2 0.1 V min

V

Absolute REFIN Voltage Limits2 GND – 30 mV V min

V

Average Reference Input Current 0.5 µA/V typ
Average Reference Input Current Drift ±0.03 nA/V/°C typ
Normal Mode Rejection2

@ 50 Hz, 60 Hz 65 dB min B Grade, 50 ± 1 Hz, 60 ± 1 Hz
60 dB min A Grade

Common Mode Rejection AIN = 1 V

@ DC 100 dB typ
@ 50 Hz, 60 Hz 110 dB typ 50 ± 1 Hz, 60 ± 1 Hz

1

Temperature Range: B Grade, –40°C to +105°C; A Grade, –40°C to +85°C.

2

Specification is not production tested but is supported by characterization data at initial product release.

3

Full-scale error applies to both positive and negative full scale and applies at the factory calibration conditions (VDD = 4 V).

, unless otherwise noted.)

MAX

DD

DD

DD

+ 30 mV V max

V max

+ 30 mV V max

Rev. 0 | Page 4 of 20

AD7788/AD7789

AD7788/AD7789 SPECIFICATIONS

Table 3.

Parameter

LOGIC INPUTS

All Inputs Except SCLK1

V

, Input Low Voltage 0.8 V max VDD = 5 V

INL

0.4 V max VDD = 3 V

V

, Input High Voltage 2.0 V min VDD = 3 V or 5 V

INH

SCLK Only (Schmitt-Triggered Input)1
VT(+) 1.4/2 V min/V max VDD = 5 V
VT(–) 0.8/1.4 V min/V max VDD = 5 V
VT(+) – VT(–) 0.3/0.85 V min/V max VDD = 5 V
VT(+) 0.9/2 V min/V max VDD = 3 V
VT(–) 0.4/1.1 V min/V max VDD = 3 V

VT(+) - VT(–) 0.3/0.85 V min/V max VDD = 3 V
Input Currents ±1 µA max VIN = VDD
Input Capacitance 10 pF typ All Digital Inputs

LOGIC OUTPUTS

VOH, Output High Voltage1 V
VOL, Output Low Voltage1 0.4 V max VDD = 3 V, I
VOH, Output High Voltage1 4 V min VDD = 5 V, I
VOL, Output Low Voltage1 0.4 V max VDD = 5 V, I
Floating-State Leakage Current ±1 µA max
Floating-State Output Capacitance 10 pF typ
Data Output Coding Offset Binary

POWER REQUIREMENTS2

Power Supply Voltage

VDD – GND 2.5/5.25 V min/max AD7789, AD7788B Grade

2.7/5.25 V min/max AD7788A Grade

Power Supply Currents

IDD Current 75 µA max 65 µA typ, VDD = 3.6 V

80 µA max 73 µA typ, VDD = 5.25 V

IDD (Power-Down Mode) 1 µA max

1

Specification is not production tested but is supported by characterization data at initial product release.

2

Digital inputs equal to VDD or GND.

AD7788A, B/
AD7789B Unit Test Conditions/Comments

– 0.6 V min VDD = 3 V, I

DD

= 100 µA

SOURCE

= 100 µA

SINK

= 200 µA

SOURCE

= 1.6 mA

SINK

Rev. 0 | Page 5 of 20

AD7788/AD7789

MIN

1, 2

, T

MAX

, unless otherwise noted.)

DD

Unit Conditions/Comments

Falling Edge to DOUT/RDY Active Time

CS

Bus Relinquish Time after CS

SCLK Inactive Edge to CS
SCLK Inactive Edge to DOUT/RDY

Falling Edge to SCLK Active Edge Setup Time4

CS

Rising Edge to SCLK Edge Hold Time

CS

Inactive Edge

Inactive Edge

High

RDY

is high,

TIMING CHARACTERISTICS

Table 4. (VDD = 2.5 V to 5.25 V (AD7788B and AD7789), VDD = 2.7 V to 5.25 V (AD7788A); GND = 0 V, REFIN(+) = 2.5 V,
REFIN(–) = GND, Input Logic 0 = 0 V, Input Logic 1 = V

Limit at T

Parameter

t3 100 ns min SCLK High Pulsewidth
t4 100 ns min SCLK Low Pulsewidth
Read Operation
t1 0 ns min
60 ns max VDD = 4.75 V to 5.25 V
80 ns max VDD = 2.7 V to 3.6 V

3

t

0 ns min SCLK Active Edge to Data Valid Delay4

2

60 ns max VDD = 4.75 V to 5.25 V
80 ns max VDD = 2.7 V to 3.6 V

5, 6

t

10 ns min

5

80 ns max
t6 100 ns max
t7 10 ns min

Write Operation
t8 0 ns min

t9 30 ns min Data Valid to SCLK Edge Setup Time
t10 25 ns min Data Valid to SCLK Edge Hold Time
t11 0 ns min

1

Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.

2

See Figure 3 and Figure 4.

3

These numbers are measured with the load circuit of Figure 2 and defined as the time required for the output to cross the VOL or VOH limits.

4

SCLK active edge is falling edge of SCLK.

5

These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then

extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and, as such, are independent of external bus loading capacitances.

6

RDY

returns high after a read of the ADC. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while
although care should be taken to ensure that subsequent reads do not occur close to the next output update. In continuous read mode, the digital word can be read
only once.

(B Version)

Rev. 0 | Page 6 of 20