ANALOG DEVICES AD7788 Service Manual

V

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Low Power, 16-/24-Bit

FEATURES

AD7788: 16-bit resolution
AD7789: 24-bit resolution
Power

Supply: 2.5 V to 5.25 V operation
Normal: 75 µA maximum

Power-down: 1 µA maximum
RMS noise: 1.5 µV
AD7788: 16-bit p-p resolution
AD7789: 19-bit p-p resolution (21.5 bits effective)
Integral nonlinearity: 3.5 ppm typical
Simultaneous 50 Hz and 60 Hz rejection
Internal clock oscillator

monitor channel

V

DD

10-lead MSOP

INTERFACE

3-wire serial
SPI®, QSPI™, MICROWIRE™, and DSP compatible
Schmitt trigger on SCLK

APPLICATIONS

Smart transmitters
Battery applications
Portable instrumentation
Sensor measurement
Temperature measurement
Pressure measurement
Weigh scales
4 to 20 mA loops

Sigma-Delta ADC

AD7788/AD7789

FUNCTIONAL BLOCK DIAGRAM

REFIN(+) REFIN(–)

AD7788/
AD7789

AIN(+)

AIN(–)

*AD7788: 16-BIT ADC
AD7789: 24-BIT ADC

Σ-∆

ADC*

Figure 1.

GENERAL DESCRIPTION

The AD7788/AD7789 are low power, low noise, analog front
ends for low frequency measurement applications. The AD7789
contains a low noise 24-bit ∑-∆ ADC with one differential input.
The AD7788 is a 16-bit version of the AD7789.

The device operates from an internal clock. Therefore, the user
does not have to supply a clock source to the device. The output
data rate is 16.6 Hz, which gives simultaneous 50 Hz/60 Hz
rejection.

The part operates with a single power supply from 2.5 V to

5.25 V. When operating from a 3 V supply, the power dissipation
for the part is 225 µW maximum. The AD7788/AD7789 is
housed in a 10-lead MSOP.

GND

CLOCK

SERIAL

INTERFACE

AND

CONTROL

LOGIC

DD

DOUT/RDY

DIN

SCLK

CS

03539-0-001

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

www.analog.com

AD7788/AD7789

TABLE OF CONTENTS

AD7789—Specifications.................................................................. 3

ADC Circuit Information.............................................................. 14

AD7788—Specifications.................................................................. 4

AD7788/AD7789 Specifications..................................................... 5

Timing Characteristics..................................................................... 6

Absolute Maximum Ratings............................................................ 8

Pin Configuration and Function Descriptions............................. 9

Typical Performance Characteristics ...........................................10

On-Chip Registers.......................................................................... 11

Communications Register

(RS1, RS0 = 0, 0) ......................................................................... 11

Status Register
(RS1, RS0 = 0, 0; Power-on/Reset = 0x88 [AD7788]

and 0x8C [AD7789]).................................................................. 12

Mode Register

(RS1, RS0 = 0, 1; Power-on/Reset = 0x02)............................... 12

Data Register
(RS1, RS0 = 1, 1; Power-on/Reset = 0x0000 [AD7788]

and 0x000000 [AD7789]).......................................................... 13

Overview ..................................................................................... 14

Noise Performance ..................................................................... 14

Digital Interface.......................................................................... 14

Single Conversion Mode....................................................... 15

Continuous Conversion Mode............................................. 15

Continuous Read Mode ........................................................ 16

Circuit Description......................................................................... 17

Analog Input Channel ............................................................... 17

Bipolar/Unipolar Configuration .............................................. 17

Data Output Coding .................................................................. 17

Reference Input........................................................................... 17

VDD Monitor................................................................................ 18

Grounding and Layout .............................................................. 18

Outline Dimensions....................................................................... 19

REVISION HISTORY

Revision 0: Initial Version

Rev. 0 | Page 2 of 20

AD7788/AD7789

AD7789—SPECIFICATIONS1

Table 1. (VDD = 2.5 V to 5.25 V; REFIN(+) = 2.5 V; REFIN(–) = GND; GND = 0 V;
all specifications T

MIN

to T

Parameter AD7789B Unit Test Conditions/Comments

ADC CHANNEL SPECIFICATION

Output Update Rate 16.6 Hz nom
ADC CHANNEL

No Missing Codes2 24 Bits min

Resolution 19 Bits p-p

Output Noise 1.5 µV rms typ

Integral Nonlinearity ±15 ppm of FSR max

Offset Error ±3 µV typ

Offset Error Drift vs. Temperature ±10 nV/°C typ

Full-Scale Error3 ±10 µV typ

Gain Drift vs. Temperature ±0.5 ppm/°C typ

Power Supply Rejection 90 dB min 100 dB typ, AIN = 1 V
ANALOG INPUTS

Differential Input Voltage Ranges ±REFIN V nom REFIN = REFIN(+) – REFIN(–)

Absolute AIN Voltage Limits2 GND – 30 mV V min
V

Analog Input Current Input current varies with input voltage.

Average Input Current2 ±400 nA/V typ
Average Input Current Drift ±50 pA/V/°C typ

Normal Mode Rejection2

@ 50 Hz, 60 Hz 65 dB min 50 ± 1 Hz, 60 ± 1 Hz

Common Mode Rejection AIN = 1 V

@ DC 90 dB min 100 dB typ
@ 50 Hz, 60 Hz2 100 dB min 50 ± 1 Hz, 60 ± 1 Hz

REFERENCE INPUT

REFIN Voltage 2.5 V nom REFIN = REFIN(+) – REFIN(–)

Reference Voltage Range2 0.1 V min
V

Absolute REFIN Voltage Limits2 GND – 30 mV V min
V

Average Reference Input Current 0.5 µA/V typ

Average Reference Input Current Drift ±0.03 nA/V/°C typ

Normal Mode Rejection2

@ 50 Hz, 60 Hz 65 dB min 50 ± 1 Hz, 60 ± 1 Hz

Common Mode Rejection AIN = 1 V

@ DC 110 dB typ
@ 50 Hz, 60 Hz 110 dB typ 50 ± 1 Hz, 60 ± 1 Hz

1

Temperature Range –40°C to +105°C.

2

Specification is not production tested, but is supported by characterization data at initial product release.

3

Full-scale error applies to both positive and negative full scale and applies at the factory calibration conditions (VDD = 4 V).

, unless otherwise noted.)

MAX

DD

DD

DD

+ 30 mV V max

V max

+ 30 mV V max

Rev. 0 | Page 3 of 20

AD7788/AD7789

AD7788—SPECIFICATIONS1

Table 2. (VDD = 2.5 V to 5.25 V (B Grade); VDD = 2.7 V to 5.25 V (A Grade); REFIN(+) = 2.5 V; REFIN(–) = GND; GND = 0 V;
all specifications T

MIN

to T

Parameter AD7788A, B Unit Test Conditions/Comments

ADC CHANNEL SPECIFICATION

Output Update Rate 16.6 Hz nom

ADC CHANNEL

No Missing Codes2 16 Bits min
Resolution 16 Bits p-p
Output Noise 1.5 µV rms typ
Integral Nonlinearity ±15 ppm of FSR max B Grade
±50 ppm of FSR max A Grade
Offset Error ±3 µV typ
Offset Error Drift vs. Temperature ±10 nV/°C typ
Full-Scale Error3 ±10 µV typ
Gain Drift vs. Temperature ±0.5 ppm/°C typ
Power Supply Rejection 90 dB min B Grade
90 dB typ A Grade

ANALOG INPUTS

Differential Input Voltage Ranges ±REFIN V nom REFIN = REFIN(+) – REFIN(–)
Absolute AIN Voltage Limits2 GND – 30 mV V min

V

Analog Input Current Input current varies with input voltage.

Average Input Current2 ±400 nA/V typ
Average Input Current Drift ±50 pA/V/°C typ

Normal Mode Rejection2

@ 50 Hz, 60 Hz 65 dB min B Grade, 50 ± 1 Hz, 60 ± 1 Hz
60 dB min A Grade, 50 ± 1 Hz, 60 ± 1 Hz

Common Mode Rejection AIN = 1 V

@ DC 90 dB min B Grade, 100 dB typ
90 dB typ A Grade
@ 50 Hz, 60 Hz2 100 dB min B Grade, 50 ± 1 Hz, 60 ± 1 Hz
100 dB typ A Grade, 50 ± 1 Hz, 60 ± 1 Hz

REFERENCE INPUT

REFIN Voltage 2.5 V nom REFIN = REFIN(+) – REFIN(–)
Reference Voltage Range2 0.1 V min

V

Absolute REFIN Voltage Limits2 GND – 30 mV V min

V

Average Reference Input Current 0.5 µA/V typ
Average Reference Input Current Drift ±0.03 nA/V/°C typ
Normal Mode Rejection2

@ 50 Hz, 60 Hz 65 dB min B Grade, 50 ± 1 Hz, 60 ± 1 Hz
60 dB min A Grade

Common Mode Rejection AIN = 1 V

@ DC 100 dB typ
@ 50 Hz, 60 Hz 110 dB typ 50 ± 1 Hz, 60 ± 1 Hz

1

Temperature Range: B Grade, –40°C to +105°C; A Grade, –40°C to +85°C.

2

Specification is not production tested but is supported by characterization data at initial product release.

3

Full-scale error applies to both positive and negative full scale and applies at the factory calibration conditions (VDD = 4 V).

, unless otherwise noted.)

MAX

DD

DD

DD

+ 30 mV V max

V max

+ 30 mV V max

Rev. 0 | Page 4 of 20

AD7788/AD7789

AD7788/AD7789 SPECIFICATIONS

Table 3.

Parameter

LOGIC INPUTS

All Inputs Except SCLK1

V

, Input Low Voltage 0.8 V max VDD = 5 V

INL

0.4 V max VDD = 3 V

V

, Input High Voltage 2.0 V min VDD = 3 V or 5 V

INH

SCLK Only (Schmitt-Triggered Input)1
VT(+) 1.4/2 V min/V max VDD = 5 V
VT(–) 0.8/1.4 V min/V max VDD = 5 V
VT(+) – VT(–) 0.3/0.85 V min/V max VDD = 5 V
VT(+) 0.9/2 V min/V max VDD = 3 V
VT(–) 0.4/1.1 V min/V max VDD = 3 V

VT(+) - VT(–) 0.3/0.85 V min/V max VDD = 3 V
Input Currents ±1 µA max VIN = VDD
Input Capacitance 10 pF typ All Digital Inputs

LOGIC OUTPUTS

VOH, Output High Voltage1 V
VOL, Output Low Voltage1 0.4 V max VDD = 3 V, I
VOH, Output High Voltage1 4 V min VDD = 5 V, I
VOL, Output Low Voltage1 0.4 V max VDD = 5 V, I
Floating-State Leakage Current ±1 µA max
Floating-State Output Capacitance 10 pF typ
Data Output Coding Offset Binary

POWER REQUIREMENTS2

Power Supply Voltage

VDD – GND 2.5/5.25 V min/max AD7789, AD7788B Grade

2.7/5.25 V min/max AD7788A Grade

Power Supply Currents

IDD Current 75 µA max 65 µA typ, VDD = 3.6 V

80 µA max 73 µA typ, VDD = 5.25 V

IDD (Power-Down Mode) 1 µA max

1

Specification is not production tested but is supported by characterization data at initial product release.

2

Digital inputs equal to VDD or GND.

AD7788A, B/
AD7789B Unit Test Conditions/Comments

– 0.6 V min VDD = 3 V, I

DD

= 100 µA

SOURCE

= 100 µA

SINK

= 200 µA

SOURCE

= 1.6 mA

SINK

Rev. 0 | Page 5 of 20

AD7788/AD7789

MIN

1, 2

, T

MAX

, unless otherwise noted.)

DD

Unit Conditions/Comments

Falling Edge to DOUT/RDY Active Time

CS

Bus Relinquish Time after CS

SCLK Inactive Edge to CS
SCLK Inactive Edge to DOUT/RDY

Falling Edge to SCLK Active Edge Setup Time4

CS

Rising Edge to SCLK Edge Hold Time

CS

Inactive Edge

Inactive Edge

High

RDY

is high,

TIMING CHARACTERISTICS

Table 4. (VDD = 2.5 V to 5.25 V (AD7788B and AD7789), VDD = 2.7 V to 5.25 V (AD7788A); GND = 0 V, REFIN(+) = 2.5 V,
REFIN(–) = GND, Input Logic 0 = 0 V, Input Logic 1 = V

Limit at T

Parameter

t3 100 ns min SCLK High Pulsewidth
t4 100 ns min SCLK Low Pulsewidth
Read Operation
t1 0 ns min
60 ns max VDD = 4.75 V to 5.25 V
80 ns max VDD = 2.7 V to 3.6 V

3

t

0 ns min SCLK Active Edge to Data Valid Delay4

2

60 ns max VDD = 4.75 V to 5.25 V
80 ns max VDD = 2.7 V to 3.6 V

5, 6

t

10 ns min

5

80 ns max
t6 100 ns max
t7 10 ns min

Write Operation
t8 0 ns min

t9 30 ns min Data Valid to SCLK Edge Setup Time
t10 25 ns min Data Valid to SCLK Edge Hold Time
t11 0 ns min

1

Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.

2

See Figure 3 and Figure 4.

3

These numbers are measured with the load circuit of Figure 2 and defined as the time required for the output to cross the VOL or VOH limits.

4

SCLK active edge is falling edge of SCLK.

5

These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then

extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and, as such, are independent of external bus loading capacitances.

6

RDY

returns high after a read of the ADC. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while
although care should be taken to ensure that subsequent reads do not occur close to the next output update. In continuous read mode, the digital word can be read
only once.

(B Version)

Rev. 0 | Page 6 of 20

AD7788/AD7789

I

(1.6mA WITH VDD = 5V,

SINK

TO OUTPUT

PIN

50pF

100µA WITH V

I

SOURCE

100µA WITH V

= 3V)

DD

1.6V

(200µA WITH VDD = 5V,

= 3V)

DD

03539-0-002

Figure 2. Load Circuit for Timing Characterization

CS (I)

t

6

t

5

7

03539-0-003

DOUT/RDY (O)

SCLK (I)

t

1

MSB LSB

t

2

I = INPUT, O = OUTPUT

t

t

3

t

4

Figure 3. Read Cycle Timing Diagram

CS (I)

t

11

03539-0-004

SCLK (I)

DIN (I)

I = INPUT, O = OUTPUT

t

8

t

9

t

10

MSB LSB

Figure 4. Write Cycle Timing Diagram

Rev. 0 | Page 7 of 20

AD7788/AD7789

ABSOLUTE MAXIMUM RATINGS

Table 5. (TA= 25°C, unless otherwise noted.)

Parameter Rating

VDD to GND –0.3 V to +7 V
Analog Input Voltage to GND –0.3 V to VDD + 0.3 V
Reference Input Voltage to GND –0.3 V to VDD + 0.3 V
Total AIN/REFIN Current (Indefinite) 30 mA
Digital Input Voltage to GND –0.3 V to VDD + 0.3 V
Digital Output Voltage to GND –0.3 V to VDD + 0.3 V
Operating Temperature Range

B Grade –40°C to +105°C

A Grade –40°C to +85°C
Storage Temperature Range –65°C to +150°C
Maximum Junction Temperature 150°C
MSOP

θJA Thermal Impedance 206°C/W

θJC Thermal Impedance 44°C/W
Lead Temperature, Soldering (10 sec) 300°C

IR Reflow, Peak Temperature 220°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Rev. 0 | Page 8 of 20

AD7788/AD7789

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

SCLK

1

AD7788/

CS

2

AIN(+)

AIN(–)

REF(+)

AD7789

3

TOP VIEW

(Not to Scale)

4

5

03539-0-005

Figure 5. Pin Configuration

Table 6. Pin Function Descriptions

Pin
No. Mnemonic Function

1 SCLK

Serial Clock Input for Data Transfers to and
from the ADC. The SCLK has a Schmitt­triggered input, making the interface
suitable for opto-isolated applications. The
serial clock can be continuous with all data
transmitted in a continuous train of pulses.
Alternatively, it can be a noncontinuous
clock with the information being trans­mitted to or from the ADC in smaller
batches of data.

2

Chip Select Input. This is an active low logic

CS

input used to select the ADC. CS can be
used to select the ADC in systems with
more than one device on the serial bus or as
a frame synchronization signal in communi­cating with the device. CS
low, allowing the ADC to operate in 3-wire
mode with SCLK, DIN, and DOUT used to
interface with the device.

3 AIN(+)

Analog Input. AIN(+) is the positive terminal
of the fully differential analog input.

4 AIN(–)

Analog Input. AIN(–) is the negative termi­nal of the fully differential analog input.

5 REFIN(+)

Positive Reference Input. REFIN(+) can lie
anywhere between V
The nominal reference voltage (REFIN(+) –
REFIN(–)) is 2.5 V, but the part functions
with a reference from 0.1 V to V

DIN

10

9

DOUT/RDY

8

V

DD

GND

7

6

REF(–)

can be hardwired

and GND + 0.1 V.

DD

.

DD

Pin
No.

Mnemonic Function

6 REFIN(–)

Negative Reference Input. This reference
input can lie anywhere between GND and

– 0.1 V.

V

DD

7 GND Ground Reference Point.
8 VDD Supply Voltage, 3 V or 5 V Nominal.
9

DOUT/RDY

Serial Data Output/Data Ready Output.

DOUT/RDY

serves a dual purpose. It functions
as a serial data output pin to access the out­put shift register of the ADC. The output shift
register can contain data from any of the
on-chip data or control registers. In addition,
DOUT/RDY

operates as a data ready pin,
going low to indicate the completion of a
conversion. If the data is not read after the
conversion, the pin will go high before the
next update occurs.

The DOUT/RDY

falling edge can be used as an
interrupt to a processor, indicating that valid
data is available. With an external serial clock,
the data can be read using the DOUT/RDY
With CS low, the data/control word informa­tion is placed on the DOUT/RDY pin on the
SCLK falling edge and is valid on the SCLK

rising edge.
The end of a conversion is also indicated by

the RDY bit in the status register. When CS is
high, the DOUT/RDY pin is three-stated but

10 DIN

the RDY

Serial Data Input to the Input Shift Register

bit remains active.

on the ADC. Data in this shift register is
transferred to the control registers within
the ADC, the register selection bits of the
communications register identifying the
appropriate register.

pin.

Rev. 0 | Page 9 of 20

AD7788/AD7789

8

8

TYPICAL PERFORMANCE CHARACTERISTICS

0

–10

–20

–30

–40

–50

–60

dB

–70

–80

–90

–100

–110

–120

0408020 60 100 120 140

FREQUENCY (Hz)

Figure 6. Frequency Response with 16.6 Hz Update Rate

03539-0-007

160

388625

CODE

VDD = 3V, V
T

= 25°C, RMS NOISE = 1.25µV

388591

0 200 400 600 800

A

= 2.048V,

REF

READ NO.

Figure 8. AD7789 Noise Plot

03539-0-009

1000

VDD = 3V
V

REF

70

T

= 25°C

A

RMS NOISE = 1.25µV

60

50

40

30

OCCURENCE

20

10

0

8388591

= 2.048V

CODE

Figure 7. AD7789 Noise Histogram

8388625

03539-0-008

3.0
VDD = 5V

UPDATE RATE = 16.6Hz

= 25°C

T

A

2.5

2.0

1.5

RMS NOISE (µV)

1.0

0.5

0

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5

(V)

V

REF

Figure 9. AD7788/AD7789 Noise vs. V

5.0

03539-0-013

REF

Rev. 0 | Page 10 of 20

AD7788/AD7789

ON-CHIP REGISTERS

The ADC is controlled and configured via a number of on-chip registers, which are described on the following pages. In the following
descriptions, set implies a Logic 1 state and cleared implies a Logic 0 state, unless otherwise stated.

COMMUNICATIONS REGISTER (RS1, RS0 = 0, 0)

The communications register is an 8-bit write-only register. All communications to the part must start with a write operation to the com­munications register. The data written to the communications register determines whether the next operation is a read or write operation,
and to which register this operation takes place. For read or write operations, once the subsequent read or write operation to the selected
register is complete, the interface returns to where it expects a write operation to the communications register. This is the default state of
the interface and, on power-up or after a reset, the ADC is in this default state waiting for a write operation to the communications regis­ter. In situations where the interface sequence is lost, a write operation of at least 32 serial clock cycles with DIN high returns the ADC to
this default state by resetting the entire part. Table 7 outlines the bit designations for the communications register. CR0 through CR7 indi­cate the bit location, CR denoting the bits are in the communications register. CR7 denotes the first bit of the data stream. The number in
brackets indicates the power-on/reset default status of that bit.

CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0

WEN(0)

0(0) RS1(0) RS0(0)

R/W(0)

Table 7. Communications Register Bit Designations

Bit Location Bit Name Description

CR7

CR6 0 This bit must be programmed with a Logic 0 for correct operation.
CR5–CR4 RS1–RS0

CR3

CR2 CREAD

CR1–CR0 CH1–CH0

Write Enable Bit. A 0 must be written to this bit so that the write to the communications register actually

WEN

occurs. If a 1 is the first bit written, the part will not clock on to subsequent bits in the register. It will stay
at this bit location until a 0 is written to this bit. Once a 0 is written to the WEN
will be loaded to the communications register.

Register Address Bits. These address bits are used to select which of the ADC’s registers are being
selected during this serial interface communication. See Table 8.

A 0 in this bit location indicates that the next operation will be a write to a specified register. A 1 in this

R/W

position indicates that the next operation will be a read from the designated register.
Continuous Read of the Data Register. When this bit is set to 1 (and the data register is selected), the

serial interface is configured so that the data register can be continuously read, i.e., the contents of the
data register are placed on the DOUT pin automatically when the SCLK pulses are applied. The commu­nications register does not have to be written to for data reads. To enable continuous read mode, the
instruction 001111XX must be written to the communications register. To exit the continuous read
mode, the instruction 001110XX must be written to the communications register while the RDY
low. While in continuous read mode, the ADC monitors activity on the DIN line so that it can receive the
instruction to exit continuous read mode. Additionally, a reset will occur if 32 consecutive 1s are seen on
DIN. Therefore, DIN should be held low in continuous read mode until an instruction is to be written to
the device.

These bits are used to select the analog input channel. The differential channel can be selected
(AIN(+)/AIN(–)) or an internal short (AIN(–)/AIN(–)) can be selected. Alternatively, the power supply can
be selected, i.e., the ADC can measure the voltage on the power supply, which is useful for monitoring
power supply variation. The power supply voltage is divided by 5 and then applied to the modulator for
conversion. The ADC uses a 1.17 V ± 5% on-chip reference as the reference source for the analog to
digital conversion. Any change in channel resets the filter and a new conversion is started.

Table 8. Register Selection

RS1 RS0 Register Register Size

0 0

0 0

0 1 Mode Register 8-Bit
1 0 Reserved 8-Bit
1 1 Data Register 16-Bit (AD7788)

Communications Register
during a Write Operation

Status Register during a
Read Operation

8-Bit

8-Bit

24-Bit (AD7789)

CREAD(0) CH1(0) CH0(0)

bit, the next seven bits

pin is

Table 9. Channel Selection

CH1 CH0 Channel

0 0 AIN(+) – AIN(–)
0 1 Reserved
1 0 AIN(–) – AIN(–)
1 1 VDD Monitor

Rev. 0 | Page 11 of 20

AD7788/AD7789

STATUS REGISTER (RS1, RS0 = 0, 0; POWER-ON/RESET = 0x88 [AD7788] AND 0x8C [AD7789])

The status register is an 8-bit read-only register. To access the ADC status register, the user must write to the communications register,
select the next operation to be a read, and load bits RS1 and RS0 with 0. Table 10 outlines the bit designations for the status register. SR0
through SR7 indicate the bit locations, SR denoting the bits are in the status register. SR7 denotes the first bit of the data stream. The
number in brackets indicates the power-on/reset default status of that bit.

SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0

RDY(1)

Table 10. Status Register Bit Designations

Bit Location Bit Name Description

SR7

SR6 ERR

SR5 0 This bit is automatically cleared.
SR4 0 This bit is automatically cleared.
SR3 1 This bit is automatically set.
SR2 1/0

SR1–SR0 CH1–CH0 These bits indicate which channel is being converted by the ADC.

ERR(0) 0(0) 0(0) 1(1) WL(1/0) CH1(0) CH0(0)

Ready bit for ADC. Cleared when data is written to the ADC data register. The RDY bit is set automatically

RDY

after the ADC data register has been read or a period of time before the data register is updated with a
new conversion result to indicate to the user not to read the conversion data. It is also set when the part
is placed in powe-down mode. The end of a conversion is indicated by the DOUT/RDY
can be used as an alternative to the status register for monitoring the ADC for conversion data.

ADC Error Bit. This bit is written to at the same time as the RDY
to the ADC data register has been clamped to all 0s or all 1s. Error sources include overrange,
underrange. Cleared by a write operation to start a conversion.

This bit is automatically cleared if the device is an AD7788 and it is automatically set if the device is an
AD7789. This bit can be used to distinguish between the AD7788 and AD7789.

bit. Set to indicate that the result written

pin also. This pin

MODE REGISTER (RS1, RS0 = 0, 1; POWER-ON/RESET = 0x02)

The mode register is an 8-bit register from which data can be read or to which data can be written. This register is used to configure the
ADC for range, unipolar or bipolar mode, enable or disable the buffer, or place the device into power-down mode. Table 11 outlines the
bit designations for the mode register. MR0 through MR7 indicate the bit locations, MR denoting the bits are in the mode register. MR7
denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit. Any write to the
setup register resets the modulator and filter and sets the

MR7 MR6 MR5 MR4 MR3 MR2 MR1 MR0

MD1(0) MD0(0) 0(0) 0(0) 0(0)

Table 11. Mode Register Bit Designations

Bit Location Bit Name Description

MR7–MR6 MD1–MD0

Mode Select Bits. These bits select between continuous conversion mode, single conversion mode, and
standby mode. In continuous conversion mode, the ADC continuously performs conversions and places
the result in the data register. RDY
conversions by placing the device in continuous read mode whereby the conversions are automatically
placed on the DOUT line when SCLK pulses are applied. Alternatively, the user can instruct the ADC to
output the conversion by writing to the communications register. After power-on, the first conversion is
available after a period 2/ f
conversion mode, the ADC is placed in power-down mode when conversions are not being performed.
When single conversion mode is selected, the ADC powers up and performs a single conversion, which
occurs after a period 2/f

ADC returns to power-down mode. The conversion remains in the data register and RDY
(low) until the data is read or another conversion is performed. See Table 12.

bit.

RDY

(0)

U/B

goes low when a conversion is complete. The user can read these

while subsequent conversions are available at a frequency of f

ADC

. The conversion result in placed in the data register, RDY goes low, and the

ADC

1(1) 0(0)

ADC

remains active

. In single

Rev. 0 | Page 12 of 20

AD7788/AD7789

Bit Location Bit Name Description

MR5–MR3 0 This bit must be programmed with a Logic 0 for correct operation.
MR2

MR1 1 This bit must be programmed with a Logic 1 for correct operation.
MR0 0 This bit must be programmed with a Logic 0 for correct operation.

Table 12. Operating Modes

MD1 MD0 Mode

0 0

0 1 Reserved
1 0 Single Conversion Mode
1 1 Powerdown Mode

DATA REGISTER (RS1, RS0 = 1, 1; POWER-ON/RESET = 0x0000 [AD7788] AND 0x000000 [AD7789])

The conversion result from the ADC is stored in this data register. This is a read-only register. On completion of a read operation from
this register, the

Unipolar/Bipolar Bit. Set by user to enable unipolar coding, i.e., zero differential input will result in

U/B

000…000 output and a full-scale differential input will result in 111…111 output. Cleared by the user to
enable bipolar coding. Negative full-scale differential input will result in an output code of 000…000,
zero differential input will result in an output code of 100…000, and a positive full-scale differential
input will result in an output code of 111…111.

Continuous Conversion Mode
(Default)

bit/pin is set.

RDY

Rev. 0 | Page 13 of 20

AD7788/AD7789

ADC CIRCUIT INFORMATION

OVERVIEW

The AD7788/AD7789 is a low power ADC that incorporates a
∑-∆ modulator and on-chip digital filtering intended for the
measurement of wide dynamic range, low frequency signals
such as those in pressure transducers, weigh scales, and
temperature measurement applications.

The part has one unbuffered differential input. The device
requires an external reference voltage between 0.1 V and V
Figure 10 shows the basic connections required to operate
the part.

POWER
SUPPLY

10µF0.1µF

V

DD

IN+

OUT–

IN–

The output rate of the AD7788/AD7789 (f
the settling time equal to 2 × t

REFIN(+)

AD7788/

OUT+

Figure 10. Basic Connection Diagram

AD7789

AIN(+)

AIN(–)

REFIN(–)

CS

DOUT/RDY

SCLK

GND

ADC

(120.4 ms). Normal mode

ADC

MICROCONTROLLER

) is 16.6 Hz with

rejection is the major function of the digital filter. Simultaneous
50 Hz and 60 Hz rejection is optimized as notches are placed at
both 50 Hz and 60 Hz with this update rate (see Figure 6).

NOISE PERFORMANCE

The AD7788/AD7789 has an rms noise of 1.5 µV rms typically,
which corresponds to a peak-to-peak resolution of 16 bits for
the AD7788 and 19 bits (equivalent to an effective resolution of

21.5 bits) for the AD7789. The numbers given are for the bipo­lar input range with a reference of 2.5 V. The noise was
measured with a differential input voltage of 0 V. The peak-to­peak resolution figures represent the resolution for which there
will be no code flicker within a six-sigma limit. The output
noise comes from two sources. The first is the electrical noise in
the semiconductor devices (device noise) used in the imple­mentation of the modulator. The second is quantization noise,
which is added when the analog input is converted into the
digital domain.

DD

03539-0-006

.

DIGITAL INTERFACE

As previously outlined, the AD7788/AD7789’s programmable
functions are controlled using a set of on-chip registers. Data is
written to these registers via the part’s serial interface and read
access to the on-chip registers is also provided by this interface.
All communications with the part must start with a write to the
communications register. After power-on or reset, the device
expects a write to its communications register. The data written
to this register determines whether the next operation is a read
operation or a write operation and also determines to which
register this read or write operation occurs. Therefore, write
access to any of the other registers on the part begins with a
write operation to the communications register followed by a
write to the selected register. A read operation from any other
register (except when continuous read mode is selected) starts
with a write to the communications register followed by a read
operation from the selected register.

The AD7788/AD7789’s serial interface consists of four signals:

, DIN, SCLK, and D OUT/

CS
transfer data into the on-chip registers while DOUT/

used for accessing from the on-chip registers. SCLK is the serial
clock input for the device and all data transfers (either on DIN
or DOUT/

DOUT/

) occur with respect to the SCLK signal. The

RDY

pin operates as a Data Ready signal also, the line

RDY

going low when a new data-word is available in the output reg­ister. It is reset high when a read operation from the data
register is complete. It also goes high prior to the updating of
the data register to indicate when not to read from the device to
ensure that a data read is not attempted while the register is
being updated.

is used to select a device. It can be used to

CS

decode the AD7788/AD7789 in systems where several compo­nents are connected to the serial bus.

Figure 3 and Figure 4 show timing diagrams for interfacing to
the AD7788/AD7789 with

Figure 3 shows the timing for a read operation from the
AD7788/AD7789’s output shift register while Figure 4 shows
the timing for a write operation to the input shift register. In all
modes except continuous read mode, it is possible to read the
same word from the data register several times even though the
DOUT/

line returns high after the first read operation.

RDY

However, care must be taken to ensure that the read operations
have been completed before the next output update occurs. In
continuous read mode, the data register can be read only once.

. The DIN line is us ed to

RDY

RDY

being used to decode the part.

CS

is

Rev. 0 | Page 14 of 20

AD7788/AD7789

The serial interface can operate in 3-wire mode by tying CS low.
In this c ase, t he SCLK, DIN, and D OUT/

lines are used to

RDY

communicate with the AD7788/AD7789. The end of conversion
can be monitored using the

scheme is suitable for interfacing to microcontrollers. If

bit in the status register. This

RDY

CS

is

required as a decoding signal, it can be generated from a port
pin. For microcontroller interfaces, it is recommended that
SCLK idles high between data transfers.

The AD7788/AD7789 can be operated with

being used as a

CS

frame synchronization signal. This scheme is useful for DSP
interfaces. In t his case, the f irst bit (MSB) is ef fect ively clocked
out by

since CS would normally occur after the falling edge

CS

of SCLK in DSPs. The SCLK can continue to run between data
transfers, provided the timing numbers are obeyed.

The serial interface can be reset by writing a series of 1s on the
DIN input. If a Logic 1 is written to the AD7788/AD7789 line
for at least 32 serial clock cycles, the serial interface is reset. This
ensures that in 3-wire systems, the interface can be reset to a
known state if the interface gets lost due to a software error or
some glitch in the system. Reset returns the interface to the state
in which it is expecting a write to the communications register.
This operation resets the contents of all registers to their power­on values.

The AD7788/AD7789 can be configured to continuously con­vert or to perform a single conversion. See Figure 11 through
Figure 13.

Single Conversion Mode

In single conversion mode, the AD7788/AD7789 is placed in
shutdown mode between conversions. When a single conver­sion is initiated by setting MD1 to 1 and MD0 to 0 in the mode
register, the AD7788/AD7789 powers up, performs a single con­version, and then returns to shutdown mode. A conversion will
require a time period of 2 × t

. DOUT/

ADC

goes low to indi-

RDY

cate the completion of a conversion. When the data-word has
been read from the data register, DOUT/

is low, DOUT/

will remain high until another conversion is

RDY

will go high. If CS

RDY

initiated and completed. The data register can be read several
times, if required, even when DOUT/

has gone high.

RDY

Continuous Conversion Mode

This is the default power-up mode. The AD7788/AD7789 will
continuously convert, the

low each time a conversion is complete. If

DOUT/

line will also go low when a conversion is

RDY

pin in the status register going

RDY

is low, the

CS

complete. To read a conversion, the user can write to the
communications register, indicating that the next operation is a
read of the data register. The digital conversion will be placed
on the DOUT/

the ADC. DOUT/

pin as soon as SCLK pulses are applied to

RDY

will return high when the conversion is

RDY

read. The user can read this register additional times, if
required. However, the user must ensure that the data register is
not being accessed at the completion of the next conversion or
else the new conversion word will be lost.

CS

DIN

DOUT/RDY

SCLK

0x10 0x82

DATA

Figure 11. Single Conversion

0x10 0x82

DATA

03539-0-010

Rev. 0 | Page 15 of 20

AD7788/AD7789

Continuous Read Mode

Rather than write to the communications register each time a
conversion is complete to access the data, the AD7788/AD7789
can be placed in continuous read mode. By writing 001111XX
to the communications register, the user needs only to apply the
appropriate number of SCLK cycles to the ADC and the data
word will automatically be placed on the DOUT/

when a conversion is complete.

When DOUT/

goes low to indicate the end of a conver-

RDY
sion, sufficient SCLK cycles must be applied to the ADC and the
data conversion will be placed on the DOUT/
the conversion is read, DOUT/

will return high until the

RDY

RDY

next conversion is available. In this mode, the data can be read
only once. Also, the user must ensure that the data-word is read

CS

line

RDY

line. When

before the next conversion is complete. If the user has not read
the conversion before the completion of the next conversion or
if insufficient serial clocks are applied to the AD7788/AD7789
to read the word, the serial output register is reset when the next
conversion is complete and the new conversion is placed in the
output serial register.

To exit the continuous read mode, the instruction 001110XX
must be written to the communications register while the

pin is low. While in the continuous read mode, the ADC
monitors activity on the DIN line so that it can receive the
instruction to exit the continuous read mode. Additionally, a
reset will occur if 32 consecutive 1s are seen on DIN. Therefore,
DIN should be held low in continuous read mode until an
instruction is to be written to the device.

RDY

DIN

DOUT/RDY

SCLK

CS

DIN

DOUT/RDY

0x3C

0x38 0x38

DATA DATA

Figure 12. Continuous Conversion

DATA DATA DATA

03539-0-012

SCLK

03539-0-011

Figure 13. Continuous Read

Rev. 0 | Page 16 of 20

AD7788/AD7789

CIRCUIT DESCRIPTION

ANALOG INPUT CHANNEL

The AD7788/AD7789 has one differential analog input channel
that is connected to the modulator, i.e., the input is unbuffered.
Note that this unbuffered input path provides a dynamic load to
the driving source. Therefore, resistor/capacitor combinations
on the input pins can cause dc gain errors, depending on the
output impedance of the source that is driving the ADC input.
Table 13 shows the allowable external resistance/capacitance
values such that no gain error at the 16-bit level is introduced
(AD7788), while Table 14 shows the allowable external resis­tance/capacitance values such that no gain error at the 20-bit
level is introduced (AD7789).

Table 13. External R-C Combination for No 16-Bit Gain
Error (AD7788)

C (pF) R (Ω)

50 22.8K
100 13.1K
500 3.3K
1000 1.8K
5000 360

Table 14. External R-C Combination for No 20-Bit Gain
Error (AD7789)

C (pF) R (Ω)

50 16.7K
100 9.6K
500 2.2K
1000 1.1K
5000 160

The absolute input voltage includes the range between GND –
30 mV and V

+ 30 mV. The negative absolute input voltage

DD

limit does allow the possibility of monitoring small true bipolar
signals with respect to GND.

The absolute input voltage includes the range between GND –
30 mV and V

+ 30 mV. The negative absolute input voltage

DD

limit does allow the possibility of monitoring small true bipolar
signals with respect to GND.

BIPOLAR/UNIPOLAR CONFIGURATION

The analog input to the AD7788/AD7789 can accept either
unipolar or bipolar input voltage ranges. A bipolar input range
does not imply that the part can tolerate large negative voltages
with respect to system GND. Unipolar and bipolar signals on
the AIN(+) input are referenced to the voltage on the AIN(–)
input. For example, if AIN(–) is 2.5 V and the ADC is config­ured for unipolar mode, the input voltage range on the AIN(+)
pin is 2.5 V to 5 V. If the ADC is configured for bipolar mode,

the analog input range on the AIN(+) input is 0 V to 5 V. The
bipolar/unipolar option is chosen by programming the B/U bit
in the mode register.

DATA OUTPUT CODING

When the ADC is configured for unipolar operation, the output
code is natural (straight) binary with a zero differential input
voltage resulting in a code of 00...00, a midscale voltage result­ing in a code of 100...000, and a full-scale input voltage resulting
in a code of 111...111. The output code for any analog input
voltage can be represented as

Code = 2

× (AIN/V

REF

)

N

When the ADC is configured for bipolar operation, the output
code is offset binary with a negative full-scale voltage resulting
in a code of 000...000, a zero differential input voltage resulting
in a code of 100...000, and a positive full-scale input voltage
resulting in a code of 111...111. The output code for any analog
input voltage can be represented as

Code = 2

× [(AIN/V

REF

) + 1]

N – 1

where AIN is the analog input voltage and N = 16 for the
AD7788 and 24 for the AD7789.

REFERENCE INPUT

The AD7788/AD7789 has a fully differential input capability for
the channel. The common-mode range for these differential
inputs is from GND to V
and, therefore, excessive R-C source impedances will introduce
gain errors. The reference voltage REFIN (REFIN(+) –
REFIN(–)) is 2.5 V nominal, but the AD7788/AD7789 is func­tional with reference voltages from 0.1 V to V
where the excitation (voltage or current) for the transducer on
the analog input also drives the reference voltage for the part,
the effect of the low frequency noise in the excitation source
will be removed because the application is ratiometric. If the
AD7788/AD7789 is used in a nonratiometric application, a low
noise reference should be used.

Recommended 2.5 V reference voltage sources for the AD7788/
AD7789 include the ADR381 and ADR391, which are low noise,
low power references. If the analog circuitry uses a 2.5 V power
supply, the reference voltage source will require some head­room. In this case, a 2.048 V reference such as the ADR380 or
ADR390 can be used. Again, these are low power, low noise
references. Also note that the reference inputs provide a high
impedance, dynamic load. Because the input impedance of each
reference input is dynamic, resistor/capacitor combinations on
these inputs can cause dc gain errors, depending on the output
impedance of the source that is driving the reference inputs.

. The reference input is unbuffered

DD

. In applications

DD

Rev. 0 | Page 17 of 20

AD7788/AD7789

Reference voltage sources like those recommended above (e.g.,
ADR391) will typically have low output impedances and are,
therefore, tolerant to having decoupling capacitors on REFIN(+)
without introducing gain errors in the system. Deriving the
reference input voltage across an external resistor will mean that
the reference input sees a significant external source impedance.
External decoupling on the REFIN pins would not be
recommended in this type of circuit configuration.

VDD MONITOR

Along with converting external voltages, the analog input chan­nel can be used to monitor the voltage on the V
CH1 and CH0 bits in the communications register are set to 1,
the voltage on the V

pin is internally attenuated by 5 and the

DD

resultant voltage is applied to the ∑-∆ modulator using an inter­nal 1.17 V reference for analog to digital conversion. This is
useful because variations in the power supply voltage can be
monitored.

GROUNDING AND LAYOUT

Since the analog inputs and reference inputs of the ADC are
differential, most of the voltages in the analog modulator are
common-mode voltages. The excellent common-mode
rejection of the part will remove common-mode noise on these
inputs. The digital filter will provide rejection of broadband
noise on the power supply, except at integer multiples of the
modulator sampling frequency. The digital filter also removes
noise from the analog and reference inputs, provided that these
noise sources do not saturate the analog modulator. As a result,
the AD7788/AD7789 is more immune to noise interference
than a conventional high resolution converter. However,
because the resolution of the AD7788/AD7789 is so high, and
the noise levels from the AD7788/AD7789 are so low, care must
be taken with regard to grounding and layout.

pin. When the

DD

The printed circuit board that houses the AD7788/AD7789
should be designed such that the analog and digital sections are
separated and confined to certain areas of the board. A mini­mum etch technique is generally best for ground planes because
it gives the best shielding.

It is recommended that the AD7788/AD7789’s GND pin be tied
to the AGND plane of the system. In any layout, it is important
that the user keep in mind the flow of currents in the system,
ensuring that the return paths for all currents are as close as
possible to the paths the currents took to reach their destina­tions. Avoid forcing digital currents to flow through the AGND
sections of the layout.

The AD7788/AD7789’s ground plane should be allowed to run
under the AD7788/AD7789 to prevent noise coupling. The
power supply lines to the AD7788/AD7789 should use as wide a
trace as possible to provide low impedance paths and reduce the
effects of glitches on the power supply line. Fast switching sig­nals such as clocks should be shielded with digital ground to
avoid radiating noise to other sections of the board, and clock
signals should never be run near the analog inputs. Avoid cross­over of digital and analog signals. Traces on opposite sides of
the board should run at right angles to each other. This will
reduce the effects of feedthrough through the board. A micro­strip technique is by far the best, but it is not always possible
with a double-sided board. In this technique, the component
side of the board is dedicated to ground planes, while signals are
placed on the solder side.

Good decoupling is important when using high resolution
ADCs. V

should be decoupled with 10 µF tantalum in parallel

DD

with 0.1 µF capacitors to GND. To achieve the best from these
decoupling components, they should be placed as close as
possible to the device, ideally right up against the device. All
logic chips should be decoupled with 0.1 µF ceramic capacitors
to DGND.

Rev. 0 | Page 18 of 20

AD7788/AD7789

OUTLINE DIMENSIONS

3.00 BSC

6

10

3.00 BSC

1

PIN 1

0.50 BSC

0.95

0.85

0.75

0.15

0.00

0.27

0.17

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-187BA

Figure 14. 10-Lead Mini Small Outline Package [MSOP]

4.90 BSC

5

1.10 MAX

SEATING
PLANE

0.23

0.08

8°
0°

(RM-10)

Dimensions shown in millimeters

0.80

0.60

0.40

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Table 15. Ordering Guide

Model Temperature Range Package Description Package Option Branding

AD7788BRM –40°C to +105°C 10-Lead Mini Small Outline Package (MSOP) RM-10 COX
AD7788BRM-REEL –40°C to +105°C 10-Lead Mini Small Outline Package (MSOP) RM-10 COX
AD7788ARM –40°C to +85°C 10-Lead Mini Small Outline Package (MSOP) RM-10 COZ
AD7788ARM-REEL –40°C to +85°C 10-Lead Mini Small Outline Package (MSOP) RM-10 COZ
AD7789BRM –40°C to +105°C 10-Lead Mini Small Outline Package (MSOP) RM-10 COY
AD7789BRM-REEL –40°C to +105°C 10-Lead Mini Small Outline Package (MSOP) RM-10 COY

Rev. 0 | Page 19 of 20

AD7788/AD7789

NOTES

© 2003 Analog Devices, Inc. All rights reserved. Trademarks and regis­tered trademarks are the property of their respective companies.

C03539-0-8/03(0)

Rev. 0 | Page 20 of 20