ANALOG DEVICES AD7781 Service Manual
20-Bit, Pin-Programmable,
A
http://www.BDTIC.com/ADI
FEATURES
Pin-programmable filter response
Update rate: 10 Hz or 16.7 Hz
Pin-programmable in-amp gain
Pin-programmable power-down and reset
Status function
Internal clock oscillator
Internal bridge power-down switch
Current
115 μA typical (gain = 1)
330 μA typical (gain = 128)
Simultaneous 50 Hz/60 Hz rejection
Power supply: 2.7 V to 5.25 V
−40°C to +105°C temperature range
Independent interface power supply
Packages
14-lead, narrow body SOIC
16-lead TSSOP
2-wire serial interface (read-only device)
SPI compatible
Schmitt trigger on SCLK
APPLICATIONS
Weigh scales
Pressure measurement
Industrial process control
Portable instrumentation
Low Power Sigma-Delta ADC
AD7781
FUNCTIONAL BLOCK DIAGRAM
V
GND
DD
AIN(+)
AIN(–) SCLK
BPDSW
AD7781
G = 1
OR 128
Table 1.
Parameter Gain = 128 Gain = 1
Output Data Rate 10 Hz 16.7 Hz 10 Hz 16.7 Hz
RMS Noise
C Grade 44 nV 65 nV 2.4 V 2.7 V
B Grade 55 nV 90 nV 2.4 V 2.7 V
P-P Resolution
C Grade 17.6 17.1 18.8 18.7
B Grade 17.3 16.6 18.8 18.7
Settling Time 300 ms 120 ms 300 ms 120 ms
REFIN(+)GAIN REFIN(–)
20-BIT Σ-Δ
INTERNAL
CLOCK
Figure 1.
ADC
DOUT/RDY
DV
DD
FILTER
PDRST
08162-001
GENERAL DESCRIPTION
The AD7781 is a complete, low power front-end solution for
bridge sensor products, including weigh scales, strain gages,
and pressure sensors. It contains a precision, low power, 20-bit
sigma-delta (Σ-) ADC, an on-chip, low noise programmable
gain amplifier (PGA), and an on-chip oscillator.
Consuming only 330 µA, the AD7781 is particularly suitable for
portable or battery-operated products where very low power is
required. The AD7781 also has a power-down mode that allows
the user to switch off the power to the bridge sensor and power
down the AD7781 when not converting, thus increasing the
battery life of the product.
For ease of use, all the features of the AD7781 are controlled by
dedicated pins. Each time that a data read occurs, eight status bits
are appended to the 20-bit conversion. These status bits contain a
pattern sequence that can be used to confirm the validity of the
serial transfer.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
The on-chip PGA has a gain of 1 or 128, supporting a full-scale
differential input of ±5 V or ±39 mV. The device has two filter
response options. The filter response at the 16.7 Hz update rate
provides superior dynamic performance. The settling time is
120 ms at this update rate. At the 10 Hz update rate, the filter
response provides better than −45 dB of stop-band attenuation.
In load cell applications, this stop-band rejection is useful to
reject low frequency mechanical vibrations of the load cell. The
settling time is 300 ms at this update rate. Simultaneous 50 Hz/
60 Hz rejection occurs at both the 10 Hz and 16.7 Hz update rates.
The AD7781 operates with a power supply from 2.7 V to 5.25 V.
It is available in a narrow body, 14-lead SOIC package and in a
16-lead TSSOP package.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved.
AD7781
http://www.BDTIC.com/ADI
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings ............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution .................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ............................................. 8
Output Noise and Resolution........................................................ 10
Theory of Operation ...................................................................... 11
Filter, Data Rate, and Settling Time ......................................... 11
Gain .............................................................................................. 11
Power-Down/Reset (
Analog Input Channel ............................................................... 12
Bipolar Configuration ................................................................ 12
Data Output Coding .................................................................. 12
Reference ..................................................................................... 12
Bridge Power-Down Switch ...................................................... 12
Digital Interface .......................................................................... 13
Applications Information .............................................................. 14
Weigh Scales ................................................................................ 14
AD7781 Performance in a Weigh Scale System ......................... 14
EMI Recommendations ............................................................. 14
Grounding and Layout .............................................................. 15
Outline Dimensions ....................................................................... 16
Ordering Guide .......................................................................... 16
PDRST
) ................................................... 12
REVISION HISTORY
5/09—Revision 0: Initial Version
Rev. 0 | Page 2 of 16
AD7781
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SPECIFICATIONS
AVDD = 2.7 V to 5.25 V, V
Table 2.
Parameter Min Typ Max Unit Test Conditions/Comments
ADC CHANNEL
Output Update Rate (f
16.7 Hz FILTER = 0, settling time = 2/f
No Missing Codes
Resolution, Peak-to-Peak See Table 7 and Table 8
RMS Noise See Tab le 7 and Tabl e 8
Integral Nonlinearity ±6 ppm FSR
Offset Error ±6 µV Gain = 128 with FILTER = 1
±200 µV Gain = 1 with FILTER = 1
±1 µV Gain = 128 with FILTER = 0
±10 µV Gain = 1 with FILTER = 0
Offset Error Drift vs. Temperature ±10 nV/°C Gain = 128
±150 nV/°C Gain = 1 with FILTER = 1
±10 nV/°C Gain = 1 with FILTER = 0
Full-Scale Error ±0.25 % of FS
Gain Drift vs. Temperature ±2 ppm/°C
Power Supply Rejection 100 dB Gain = 128, FILTER = 1, AIN = 7.81 mV
120 dB Gain = 128, FILTER = 0, AIN = 7.81 mV
Normal Mode Rejection
50 Hz, 60 Hz 63 75 dB 50 Hz ± 1 Hz, 60 Hz ± 1 Hz, f
72 90 dB 50 Hz ± 1 Hz, 60 Hz ± 1 Hz, f
Common-Mode Rejection
DC 90 dB Gain = 1, AIN = 1 V
90 dB Gain = 128, AIN = 7.81 mV
50 Hz, 60 Hz 110 dB 50 Hz ± 1 Hz, 60 Hz ± 1 Hz
ANALOG INPUTS
Differential Input Voltage Range ±V
Absolute AIN Voltage Limits
GND + 450 mV AVDD − 1.1 V Gain = 128, FILTER = 0
GND + 1.1 AVDD − 1.1 V Gain = 128, FILTER = 1, AVDD ≤ 3.6 V
GND + 1.5 AVDD − 1.5 V Gain = 128, FILTER = 1, AVDD > 3.6 V
Average Input Current ±1 nA Gain = 1
±250 pA Gain = 128
Average Input Current Drift ±3 pA/°C
REFERENCE
External REFIN Voltage AVDD V REFIN = REFIN(+) − REFIN(−)
Reference Voltage Range
Absolute REFIN Voltage Limits
Average Reference Input Current 400 nA/V
Average Reference Input Current
Drift
Normal Mode Rejection Same as for analog inputs
Common-Mode Rejection 110 dB
BRIDGE POWER-DOWN SWITCH
(BPDSW)
RON 9 Ω
Allowable Current
= AVDD, DVDD = 2.7 V to 5.25 V, GND = 0 V, all specifications T
REF
) 10 Hz FILTER = 1, settling time = 3/f
ADC
2
2
20 Bits
/gain V
REF
MIN
to T
, unless otherwise noted.1
MAX
= REFIN(+) − REFIN(−),
V
REF
ADC
ADC
= 16.7 Hz
ADC
= 10 Hz
ADC
gain = 1 or 128
2
GND + 100 mV AV
2
0.5 AV
2
GND − 30 mV AV
− 100 mV V Gain = 1
DD
V
DD
+ 30 mV V
DD
±0.15 nA/V/°C
2
30 mA Continuous current
Controlled via the PDRST
pin
Rev. 0 | Page 3 of 16
AD7781
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Parameter Min Typ Max Unit Test Conditions/Comments
INTERNAL CLOCK
Frequency 64 − 3% 64 + 3% kHz
Duty Cycle 50:50 %
LOGIC INPUTS
SCLK, FILTER, GAIN, PDRST
Input Low Voltage, V
0.8 V DVDD = 5 V
Input High Voltage, V
2.4 V DVDD = 5 V
SCLK (Schmitt-Triggered Input)
Hysteresis
2
100 mV DV
140 mV DVDD = 5 V
Input Currents ±2 µA VIN = DVDD or GND
Input Capacitance 10 pF All digital inputs
LOGIC OUTPUT (DOUT/RDY)
Output High Voltage, V
4 V DVDD = 5 V, I
Output Low Voltage, V
0.4 V DVDD = 5 V, I
Floating-State Leakage Current ±2 µA
Floating-State Output Capacitance 10 pF
Data Output Coding Offset binary
POWER REQUIREMENTS
Power Supply Voltage
AVDD to GND 2.7 5.25 V
DVDD to GND 2.7 5.25 V
Power Supply Currents
IDD Current
Gain = 1 115 µA AVDD = 3 V
130 160 µA AVDD = 5 V
Gain = 128 (B Grade) 300 µA AVDD = 3 V
350 400 µA AVDD = 5 V
Gain = 128 (C Grade) 330 µA AVDD = 3 V
420 500 µA AVDD = 5 V
IDD (Power-Down/Reset Mode) 10 µA
1
Temperature range is −40°C to +105°C.
2
This specification is not production tested but is supported by characterization data at initial product release.
3
Digital inputs are equal to DVDD or GND.
2
0.4 V DVDD = 3 V
INL
1.8 V DVDD = 3 V
INH
2
DV
OH
2
0.4 V DV
OL
3
− 0.6 V DVDD = 3 V, I
DD
= 3 V
DD
= 3 V, I
DD
SOURCE
SOURCE
= 100 µA
SINK
= 1.6 mA
SINK
= 100 µA
= 200 µA
Rev. 0 | Page 4 of 16
AD7781
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TIMING CHARACTERISTICS
AVDD = 2.7 V to 5.25 V, DVDD = 2.7 V to 5.25 V, GND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DVDD, unless otherwise noted.
Table 3.
Parameter
Read
1
2
Limit at T
MIN
, T
Unit Test Conditions/Comments
MAX
t1 100 ns min SCLK high pulse width
t2 100 ns min SCLK low pulse width
3
t
3
0 ns min SCLK active edge to data valid delay
4
60 ns max DVDD = 4.75 V to 5.25 V
80 ns max DVDD = 2.7 V to 3.6 V
t4 10 ns min
SCLK inactive edge to DOUT/RDY
high
130 ns max
Reset
t5 100 ns min
5
t
6
FILTER/GAIN change to data valid delay
low pulse width
PDRST
120 ms typ Update rate = 16.7 Hz
300 ms typ Update rate = 10 Hz
1
Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V.
2
See Figure 3.
3
The values of t3 are measured using the load circuit of Figure 2 and are defined as the time required for the output to cross the VOL or VOH limits.
4
SCLK active edge is falling edge of SCLK.
5
PDRST
The
high to data valid delay is typically 1 ms longer than t6 because the internal oscillator requires time to power up and settle.
Circuit and Timing Diagrams
DOUT/RDY
(OUTPUT)
SCLK
(INPUT)
I
(1.6mA WITH DVDD = 5V,
TO
OUTPUT
PIN
50pF
SINK
100µA WIT H DV
I
SOURCE
100µA WIT H DV
= 3V)
DD
1.6V
(200µA WIT H DVDD = 5V,
= 3V)
DD
Figure 2. Load Circuit for Timing Characterization
MSB LSB
t
3
t
1
t
2
t
Figure 3. Read Cycle Timing Diagram
PDRST
(INPUT)
t
5
DOUT/RDY
08162-002
(OUTPUT)
08162-004
Figure 4. Resetting the AD7781
GAIN OR FILTER
(INPUT)
4
DOUT/RDY
(OUTPUT)
08162-003
t
6
08162-005
Figure 5. Changing Gain or Filter Option
Rev. 0 | Page 5 of 16
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