ANALOG DEVICES AD7763 Service Manual

24-Bit, 625 kSPS, 109 dB Sigma-Delta

V

V

ADC with On-Chip Buffers, Serial Interface

FEATURES

120 dB dynamic range at 78 kHz output data rate
109 dB dynamic range at 625 kHz output data rate
112 dB SNR at 78 kHz output data rate
107 dB SNR at 625 kHz output data rate
625 kHz maximum fully filtered output word rate
Programmable oversampling rate (32× to 256×)
Flexible serial interface
Fully differential modulator input
On-chip differential amplifier for signal buffering
Low-pass finite impulse response (FIR) filter with default

or user-programmable coefficients
Overrange alert bit
Digital offset and gain correction registers
Low power and power-down modes

SYNC

Synchronization of multiple devices via

2

I

S interface mode

APPLICATIONS

Data acquisition systems
Vibration analysis
Instrumentation

pin

V

REF+

REFGND

MCLK

MCLKGND

SYNC

RESET

SH2:0

ADR2:0

CDIV

AD7763

FUNCTIONAL BLOCK DIAGRAM

IN+

IN–

MULTIBIT

Σ-Δ

MODULATOR

RECONSTRUCTION

PROGRAMMABLE

DECIMATION

FIR FILTER

ENGINE

BUF

AD7763

CONTROL L OGIC

OFFSET AND GAIN

S

2

I

SCP

I/O

REGISTERS

SDL

SCR

DRDY

DIFF

SCO

FSO

SDO

Figure 1.

FSI

SDI

AV

DD1

AV

DD2

AV

DD3

AV

DD4

DECAPA
DECAPB

R

BIAS

AGND
V

DRIVE

DV

DD

DGND

05476-001

GENERAL DESCRIPTION

The AD7763 high performance, 24-bit, Σ-Δ analog-to-digital
converter (ADC) combines wide input bandwidth and high
speed with the benefits of Σ-Δ conversion, as well as performance
of 107 dB SNR at 625 kSPS, making it ideal for high speed data
acquisition. A wide dynamic range, combined with significantly
reduced antialiasing requirements, simplifies the design process.
An integrated buffer to drive the reference, a differential ampli­fier for signal buffering and level shifting, an overrange flag,
internal gain and offset registers, and a low-pass, digital FIR
filter make the AD7763 a compact, highly integrated data
acquisition device requiring minimal peripheral component
selection. In addition, the device offers programmable
decimation rates and a digital FIR filter, which can be user­programmed to ensure that its characteristics are tailored for the
user’s application. The AD7763 is ideal for applications demanding
high SNR without necessitating the design of complex, front­end signal processing.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

The differential input is sampled at up to 40 MSPS by an analog
modulator. The modulator output is processed by a series
of low-pass filters, the final filter having default or user­programmable coefficients. The sample rate, filter corner
frequencies, and output word rate are set by a combination of
the external clock frequency and the configuration registers of
the AD7763.

The reference voltage supplied to the AD7763 determines the
analog input range. With a 4 V reference, the analog input range
is ±3.2 V differential-biased around a common mode of 2 V.
This common-mode biasing can be achieved using the on-chip
differential amplifiers, further reducing the external signal
conditioning requirements.

The AD7763 is available in an exposed paddle, 64-lead TQFP_EP
and is specified over the industrial temperature range from

−40°C to +85°C.

Table 1. Related Devices

Part No. Description

AD7760 24-bit, 2.5 MSPS, 100 dB Σ-Δ, parallel interface
AD7762 24-bit, 625 kSPS, 109 dB Σ-Δ, parallel interface

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2005–2009 Analog Devices, Inc. All rights reserved.

AD7763

TABLE OF CONTENTS

Features .............................................................................................. 1

Example 2 .................................................................................... 19

Applications ....................................................................................... 1 

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Timing Specifications ....................................................................... 5

Timing Diagrams .......................................................................... 6

Absolute Maximum Ratings ............................................................ 7

ESD Caution .................................................................................. 7

Pin Configuration and Function Descriptions ............................. 8

Terminology .................................................................................... 10

Typical Performance Characteristics ........................................... 11

Theory of Operation ...................................................................... 14

AD7763 Interface ............................................................................ 15

Reading Data Using the SPI Interface ..................................... 15

Driving the AD7763 ....................................................................... 20

Using the AD7763 ...................................................................... 21

Bias Resistor Selection ............................................................... 21

Decoupling and Layout Recommendations................................ 22

Supply Decoupling ..................................................................... 23

Additional Decoupling .............................................................. 23

Reference Voltage Filtering ....................................................... 23

Differential Amplifier Components ........................................ 23

Exposed Paddle ........................................................................... 23

Layout Considerations ............................................................... 23

Programmable FIR Filter ............................................................... 24

Downloading a User-Defined Filter ............................................ 25

Example Filter Download ......................................................... 26

Registers ........................................................................................... 27

Control Register 1—Address 0x001 ......................................... 27

Synchronization .......................................................................... 15

Sharing the Serial Bus ................................................................ 15

Writing to the AD7763 .............................................................. 16

Reading Status and Other Registers ......................................... 17

Reading Data Using the I2S Interface ....................................... 18

Clocking the AD7763 ..................................................................... 19

Example 1 .................................................................................... 19

REVISION HISTORY

11/09—Rev. 0 to Rev. A

Changes to Figure 5 .......................................................................... 8

Changes to Sharing the Serial Bus Section .................................. 15

Changes to Figure 26 ...................................................................... 16

Updated Outline Dimensions ....................................................... 29

Changes to Ordering Guide .......................................................... 29

10/05—Revision 0: Initial Version

Control Register 2—Address 0x002 ......................................... 27

Status Register (Read Only) ...................................................... 28

Offset Register—Address 0x003 ............................................... 28

Gain Register—Address 0x004 ................................................. 28

Overrange Register—Address 0x005 ....................................... 28

Outline Dimensions ....................................................................... 29

Ordering Guide .......................................................................... 29

Rev. A | Page 2 of 32

AD7763

SPECIFICATIONS

AV

= DVDD = V

DD1

using on-chip amplifier with components as shown in Table 1 0, unless otherwise noted.

Table 2.

Parameter Test Conditions/Comments Specification Unit

DYNAMIC PERFORMANCE

Decimate × 256 MCLK = 40 MHz, ODR = 78 kHz, FIN = 1 kHz

Dynamic Range Modulator inputs shorted 119

Signal-to-Noise Ratio (SNR)2 Input amplitude = −0.5 dBFS 112 dB typ

Input amplitude = −60 dB 59 dBc typ

Spurious-Free Dynamic Range (SFDR)

Total Harmonic Distortion (THD)

Decimate × 64 MCLK = 40 MHz, ODR = 312.5 kHz, FIN = 1 kHz

Dynamic Range Modulator inputs shorted 112

Signal-to-Noise Ratio (SNR)2 Input amplitude = −0.5 dBFS 109.5 dB typ
Spurious-Free Dynamic Range (SFDR) Nonharmonic, input amplitude = −6 dB 126 dBc typ

Decimate × 32 MCLK = 40 MHz, ODR = 625 kHz, FIN = 100 kHz

Dynamic Range Modulator inputs shorted 108

Signal-to-Noise Ratio (SNR)2 Input amplitude = −0.5 dBFS 107 dB typ
Spurious-Free Dynamic Range (SFDR)
Total Harmonic Distortion (THD)

DC ACCURACY

Resolution 24 Bits

Differential Nonlinearity Guaranteed monotonic to 24 bits

Integral Nonlinearity 0.00076 % typ

Zero Error 0.014 % typ

Gain Error 0.018 % typ

Zero Error Drift 10 %FS/°C typ

Gain Error Drift 0.0002 %FS/°C typ

DIGITAL FILTER RESPONSE

Decimate × 32

Group Delay MCLK = 40 MHz 47 µs typ

Decimate × 64

Group Delay MCLK = 40 MHz 91.5 µs typ

Decimate × 256

Group Delay MCLK = 40 MHz 358 µs typ

ANALOG INPUT

Differential Input Voltage

V

Input Capacitance At internal buffer inputs 5 pF typ

At modulator inputs 55 pF typ

= 2.5 V; AV

DRIVE

DD2

= AV

DD3

= AV

= 5 V; V

DD4

= 4.096 V; MCLK amplitude = 5 V; TA = 25°C; normal mode,

REF

1

dB min

120.5

dB typ

Nonharmonic, input amplitude = −6 dB 126 dBc typ
Input amplitude = −60 dB 77 dBc typ
Input amplitude = −0.5 dBFS −105 dB typ
Input amplitude = −6 dB −106 dBc typ
Input amplitude = −60 dB −75 dBc typ

dB min

113

dB typ

dB min

109.5

dB typ

Nonharmonic, input amplitude = −6 dB 120 dBc typ
Input amplitude = −0.5 dBFS −105 dB typ
Input amplitude = −6 dB −107 dBc typ

0.02 % max

VIN(+) – VIN(−), V

(+) – Vin(−), V

IN

Rev. A | Page 3 of 32

= 2.5 V ±2 V p-p

REF

= 4.096 V ±3.25 V p-p

REF

AD7763

Parameter Test Conditions/Comments Specification Unit

REFERENCE INPUT

V

Input Voltage V

REF

V
V

Input DC Leakage Current ±1 µA max

REF

V

Input Capacitance 5 pF max

REF

POWER DISSIPATION

Total Power Dissipation Normal power mode 955.5 mW max
Low power mode 651 mW max
Standby Mode Clock stopped 6.35 mW typ

POWER REQUIREMENTS

AV

(Modulator Supply) ±5% +2.5 V

DD1

AV

(General Supply) ±5% +5 V

DD2

AV

(Differential Amplifier Supply) +3.15/+5.25 V min/max

DD3

AV

(Reference Buffer Supply) +3.15/+5.25 V min/max

DD4

DVDD ±5% +2.5 V
V

+1.65/+2.7 V min/max

DRIVE

Normal Mode

AI

(Modulator) 49/52 mA typ/max

DD1

AI

(General) 40/43 mA typ/max

DD2

AI

(Reference Buffer) AV

DD4

Low Power Mode

AI

(Modulator) 26/28 mA typ/max

DD1

AI

(General) 20/23 mA typ/max

DD2

AI

(Reference Buffer) AV

DD4

AI

(Diff Amp) AV

DD3

DIDD Both modes 56/62 mA typ/max

DIGITAL I/O

MCLK Input Amplitude3 5 V typ
Input Capacitance 7.3 pF typ
Input Leakage Current ±1 A/pin max
Three-State Leakage Current (SDO) ±1 A max
V

0.7 × V

INH

V

0.3 × V

INL

4

V

1.5 V min

OH

VOL 0.1 V max

1

See the Terminology section.

2

SNR specifications in dB are referred to a full-scale input, FS, and tested with an input signal at 0.5 dB below full scale, unless otherwise specified.

3

While the AD7763 can function with an MCLK amplitude of less than 5 V, this is the recommended amplitude to achieve the performance as stated.

4

Tested with a 400 A load current.

= 3.3 V ± 5% +2.5 V max

DD3

= 5 V ± 5% +4.096 V max

DD3

= 5 V 35/37 mA typ/max

DD4

= 5 V 10/11 mA typ/max

DD4

= 5 V, both modes 41/45 mA typ/max

DD3

V min

DRIVE

V max

DRIVE

Rev. A | Page 4 of 32

AD7763

TIMING SPECIFICATIONS

AV

= DVDD = V

DD1

Table 3.

Parameter Limit at T

f

1 MHz min Applied master clock frequency

MCLK

40 MHz max
f

500 kHz min Internal modulator clock derived from MCLK

ICLK

20 MHz max

1

t

1 × t

1

1

t

1 × t

2

t3 t

4

t

2 ns typ

3A

4

t

3 ns typ

3B

5

t

32 × t

4

4, 5

t

1 ns typ

4A

4, 5

t

2 ns typ

4B

t5 6.5 ns max Initial data access time

4

t

5 ns max SCO rising edge to SDO valid

6

t7 0.5 × t
t8 16 × t

t9 t
t10 5.5 ns max SDO three-state to SCO rising edge
t11 1 × t

t12 12 ns min SDI setup time
t13 10 ns min SDI hold time
t14 12 ns min
t15 16 × t

1

t

= 1/f

ICLK

2

3

4

5

ICLK.

SCO frequency selected by SCR and
t

= t1 + t2.

SCO

All edges mentioned refer to SCP = 0. Invert SCO edges for SCP = 1.
In decimate × 32 mode, this time specification applies only when

signal is constantly logic low.

= 2.5 V, AV

DRIVE

or 0.5 × t

ICLK

or 0.5 × t

ICLK

3

typ

SCO

MIN

= AV

DD2

, T

Unit Description

MAX

ICLK

ICLK

= AV

DD3

2

typ SCO high period

2

typ SCO low period

= 5 V, TA = 25°C, normal mode, unless otherwise noted.

DD4

DRDY
SCO rising edge to DRDY
SCO rising edge to DRDY

3

typ

SCO

FSO
SCO rising edge to FSO
SCO falling edge to FSO

3

ns min SDO valid after SCO falling edge

SCO

3

typ

SCO

3

typ SDL pulse width

SCO

3

min

SCO

3

typ SDL falling edge to SDL falling edge

SCO

CDIV

pins.

CDIV

= 0 and SCR =1. For all other combinations of

DRDY

low period

FSI

setup time

FSI

low period

falling edge
rising edge

low period

falling edge

rising edge

rising edge to SDL falling edge

CDIV

and SCR in decimate × 32 mode, the FSO

Rev. A | Page 5 of 32

AD7763

TIMING DIAGRAMS

t

32 ×

4

t

9

t

15

t

SCO

t

13

t

4B

t

10

FSO (O)

SCO (O)

DRDY (O)

SDO (O)

SDL (O)

SCO (O)

FSI (I)

SDI (I)

t

4A

t

t

3A

3B

t

3

t

5

t

1

t

2

t

D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ST6 ST5 ST4 ST3 ST2 ST1 ST0

6

t

8

t

7

Figure 2. SPI® Interface Serial Read Timing Diagram

t

t

14

t

11

ALL ADR2 ADR1 ADR0 RA11 RA10 RA1 RA0 D15 D14 D1 D0

1

t

2

t

12

05476-002

SCO (O)

DRDY A (O)

SDO (O)

FSO A

FSO B

FSO C

FSO D

Figure 3. Register Write

32 ×

t

SCO

SERIAL DATA F ROM ADC A

32 ×

t

SCO

SERIAL DATA F ROM ADC B S ERIAL DATA FROM ADC C SERI AL DATA FROM ADC D

32 ×

t

SCO

Figure 4. SPI Interface Serial Read Timing with Multiple AD7763 Devices Sharing the Serial Bus

32 ×

05476-003

t

SCO

05476-004

Rev. A | Page 6 of 32

AD7763

ABSOLUTE MAXIMUM RATINGS

= 25°C, unless otherwise noted.

T

A

Table 4.

Parameter Rating

AV

to GND −0.3 V to +3 V

DD1

(AV

, AV

, AV

DD2

DD3

) to GND −0.3 V to +6 V

DD4

DVDD to GND −0.3 V to +3 V
V

to GND −0.3 V to +3 V

DRIVE

V

, V

to GND −0.3 V to +6 V

IN+

IN–

Digital Input Voltage to GND1 −0.3 V to DV

+ 0.3 V

DD

MCLK to MCLKGND −0.3 V to +6 V
V

to GND2 −0.3 V to AV

REF

+ 0.3 V

DD4

AGND to DGND −0.3 V to +0.3 V
Input Current to Any Pin

Except Supplies

3

Operating Temperature Range

±10 mA

−40°C to +85°C

Commercial

Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
TQFP_EP Exposed Paddle

θJA Thermal Impedance 92.7°C/W

θJC Thermal Impedance 5.1°C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C

ESD 600 V

1

Absolute maximum voltage on digital inputs is 3.0 V or DVDD + 0.3 V,

whichever is lower.

2

Absolute maximum voltage on V

whichever is lower.

3

Transient currents of up to 200 mA do not cause SCR latch-up.

input is 6.0 V or AV

REF

+ 0.3 V,

DD4

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. A | Page 7 of 32

AD7763

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

S

DRIVE

2

DGND63V

DGND61I

64

1

DGND

MCLKGND

MCLK
AV

DD2

AGND2

AV

DD1

AGND1
DECAPA
REFGND

V

REF+

AGND4

AV

DD4

AGND2

AV

DD2

AV

DD2

AGND2

NOTES

1. THE PADDLE M US T BE CONNECTED DIRECT LY TO T HE GROUND PLANE O F
THE PCB USING MULTIPLE VIAS.

PIN 1

2
3
4
5
6
7
8

9
10
11
12
13
14
15
16

17

18

BIAS

R

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

6, 33 AV

DD1

Power Supply for Modulator, 2.5 V. These pins should be decoupled to AGND1 with 100 nF and
10 µF capacitors on each pin.

4, 14, 15, 27 AV

DD2

Power Supply, 5 V. These pins should be decoupled to AGND2 with 100 nF capacitors on each of
Pin 4, Pin 14, and Pin 15. Pin 27 should be connected to Pin 14 via an 8.2 nH inductor.

24 AV

DD3

Power Supply for Differential Amplifier, 3.3 V to 5 V. This pin should be decoupled to AGND3
with a 100 nF capacitor.

12 AV

DD4

Power Supply for Reference Buffer, 3.3 V to 5 V. This pin should be decoupled to AGND4

with a 10 nF capacitor in series with a 10 Ω resistor.
7, 34 AGND1 Power Supply Ground for Analog Circuitry Powered by AV
5, 13, 16, 18, 28 AGND2 Power Supply Ground for Analog Circuitry Powered by AV
23, 29, 31, 32 AGND3 Power Supply Ground for Analog Circuitry Powered by AV
11 AGND4 Power Supply Ground for Analog Circuitry Powered by AV
9 REFGND Reference Ground. Ground connection for the reference voltage.
41 DVDD

Power Supply for Digital Circuitry and FIR Filter, 2.5 V. This pin should be decoupled to DGND

with a 100 nF capacitor.
44, 63 V

DRIVE

Logic Power Supply Input, 1.8 V to 2.5 V. The voltage supplied at these pins determines

the operating voltage of the logic interface. These pins must be connected together and

tied to the same supply. Each pin should also be decoupled to DGND with a 100 nF capacitor.
1, 35, 42, 43, 53, 57, 59,

DGND Ground Reference for Digital Circuitry.

62, 64
19 VINA+ Positive Input to Differential Amplifier.
20 VINA− Negative Input to Differential Amplifier.
21 V
22 V

A− Negative Output from Differential Amplifier.

OUT

A+ Positive Output from Differential Amplifier.

OUT

25 VIN+ Positive Input to the Modulator.
26 VIN− Negative Input to the Modulator.
10 V

REF+

Reference Input. The input range of this pin is determined by the reference buffer
supply voltage (AV

SCR59DGND58CDIV57DGND56FSO55SCO54SDO53DGND52SDI51FSI50SDL49SCP

62

60

AD7763

TOP VIEW

(Not to S cale)

19

20

21

22

23

24

25

26

A–

A–

A+

A+

IN

IN

V

V

AGND2

OUT

V

V

+

IN

DD3

V

AV

OUT

AGND3

Figure 5. Pin Configuration

). See the Reference Voltage Filtering section for more details.

DD4

48

ADR0

47

ADR1

46

ADR2

45

SH0

44

V

DRIVE

43

DGND

42

DGND

41

DV

DD

40

SH1

39

SH2

38

DRDY

37

RESET

36

SYNC

35

DGND

34

AGND1

33

AV

DD1

27

28

30

AGND229AGND3

31

AGND332AGND3

DECAPB

05476-005

.

DD1

.

DD2

.

DD3

.

DD4

–

IN

DD2

V

AV

Rev. A | Page 8 of 32

AD7763

Pin No. Mnemonic Description

8 DECAPA Decoupling Pin. A 100 nF capacitor must be inserted between this pin and AGND1.
30 DECAPB Decoupling Pin. A 33 pF capacitor must be inserted between this pin and AGND3.
17 R

37

3 MCLK

2 MCLKGND Master Clock Ground Sensing Pin.
36

38

39, 40, 45 SH2:0

46 to 48 ADR2:0

49 SCP

50 SDL

51

52 SDI

54 SDO

55 SCO

56

58

60 SCR
61 I2S

BIAS

Bias Current Setting. A resistor must be inserted between this pin and AGND.
See the Bias Resistor Selection section.

RESET

A falling edge on this pin resets all internal digital circuitry. Holding this pin low
keeps the AD7763 in a reset state.

Master Clock Input. A low jitter digital clock must be applied to this pin. The output data rate
depends on the frequency of this clock. See the Clocking the AD7763 section.

SYNC

Synchronization Input. A falling edge on this pin resets the internal filter. This can be used
to synchronize multiple devices in a system.

DRDY

Data Ready Output. Each time new conversion data is available, an active low pulse,
½ ICLK period wide, is produced on this pin. See the AD7763 Interface section.

Share Pins 2:0. For multiple AD7763 devices sharing a common serial bus. Each device is wired
with the binary value that represents the number of devices sharing the serial bus. SH2 is the
MSB. See the Sharing the Serial Bus section.

Address 2:0. Allows multiple AD7763 devices to share a common serial bus. Each device must be
programmed with an individual address using these three pins. See the Sharing the Serial Bus
section.

Serial Clock Polarity. Determines on which edge of SCO the data bits are clocked out and on
which edge they are valid. All timing diagrams are shown with SCP = 0, and all SCO edges
shown should be inverted for SCP = 1.

Serial Data Latch. A pulse is output on this pin after every 16 data bits. The pulse is one SCO
period wide and can be used in conjunction with FSO as an alternative framing method for
serial transfers requiring a framing signal more frequent than every 32 bits.

FSI

Frame Sync In. The status of this pin is checked on the falling edge of SCO. If this pin is low, then
the first data bit is latched in on the next SCO falling edge when SCP = 0 or on the rising edge of
SCO if SCP = 1.

Serial Data In. The first data bit (MSB) must be valid on the next SCO falling edge when SCP = 0
(or SCO rising edge SCP = 1) after the FSI event has been latched. Each write requires 32 bits: the
ALL bit, 3 address bits, and 12 register address bits, followed by the remaining 16 bits of data to
be written to the device.

Serial Data Out. Address, status, and data bits are clocked out on this line during each serial
transfer.
If SCP = 0, each bit is clocked out on an SCO rising edge and is valid on the falling edge. When

2

S pin is set to logic high, this pin outputs the signal defined as SD in the I2S bus

the I
specification. See the Reading Data Using the I

2

S Interface section for details.

Serial Clock Out. This clock signal is derived from the internal ICLK signal. The frequency of SCO
is equal to either ICLK or ICLK/2, depending on the state of the CDIV

2

S pin is logic high, this pin outputs the signal defined as

Reading Data Using the I2S Interface

FSO

occurs in decimate × 32 mode, where, for certain

FSO

signal is constantly logic low. See the

Reading Data Using the I2S Interface

FSO

AD7763 Interface
SCK by the I

Frame Sync Out. This signal frames the serial data output and is 32 SCO periods wide. The

section). When the I

2

S bus specification. See the section.

exception to the framing behavior of
combinations of CDIV
Using the SPI Interface

defined as WS in the I

Clock Divider. This pin is used to select the ratio of MCLK to ICLK. See the AD7763 Interface

CDIV

and SCR, the

section. When the I2S pin is set to logic high, this pin outputs the signal

2

S bus specification. See the section.

and SCR pins (see the

Reading Data

section.
Serial Clock Rate. This pin and the CDIV

2

S Select. A Logic 1 on this pin changes the serial data-out mode from SPI to I2S. The SDO pin

I
outputs as the SD signal, the SCO pin outputs the SCK signal, and the

signal. When writing to the AD7763, the I
See the section for further details. Reading Data Using the I

pin program the SCO frequency (see ). Table 7

2

2

S pin is set to logic low and the SPI interface is used.

S Interface

FSO

pin outputs the WS

Rev. A | Page 9 of 32

AD7763

TERMINOLOGY

Signal-to-Noise Ratio (SNR) Integral Nonlinearity (INL)

The ratio of the rms value of the actual input signal to the rms
sum of all other spectral components below the Nyquist fre­quency, excluding harmonics and dc. The value for SNR is
expressed in decibels.

The ratio of the rms sum of harmonics to the fundamental. For
the AD7763, it is defined as

22222

VVVVV

++++

54

THD

()

log20dB

=

32

V

1

6

where:

V

is the rms amplitude of the fundamental.

1

V

, V3, V4, V5, and V6 are the rms amplitudes of the second

2

to the sixth harmonic.

Nonharmonic Spurious-Free Dynamic Range (SFDR)

The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component, excluding harmonics.

Dynamic Range

The ratio of the rms value of the full scale to the rms noise
measured with the inputs shorted together. The value for
dynamic range is expressed in decibels.

The maximum deviation from a straight line passing through
the endpoints of the ADC transfer function.

Differential Nonlinearity (DNL)

The difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.

Total Harmonic Distortion (THD)

Zero Error

The difference between the ideal midscale input voltage (0 V)
and the actual voltage producing the midscale output code.

Zero Error Drift

The change in the actual zero error value due to a temperature
change of 1°C. It is expressed as a percentage of full scale at room
temperature.

Gain Error

The first transition (from 100…000 to 100…001) should occur
for an analog voltage 1/2 LSB above the nominal negative full
scale. The last transition (from 011…110 to 011…111) should
occur for an analog voltage 1 1/2 LSB below the nominal full
scale. The gain error is the deviation of the difference between
the actual level of the last transition and the actual level of the
first transition, from the difference between the ideal levels.

Gain Error Drift

The change in the actual gain error value due to a temperature
change of 1°C. It is expressed as a percentage of full scale at
room temperature.

Rev. A | Page 10 of 32