ANALOG DEVICES AD7723 Service Manual

16-Bit, 1.2 MSPS CMOS,

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FEATURES

16-bit Σ-∆ ADC

1.2 MSPS output word rate 32×/16× oversampling ratio Low-pass and band-pass digital filter Linear phase On-chip 2.5 V voltage reference Standby mode Flexible parallel or serial interface Crystal oscillator Single 5 V supply

GENERAL DESCRIPTION

The AD7723 is a complete 16-bit, sigma-delta ADC. The part operates from a 5 V supply. The analog input is continuously sampled, eliminating the need for an external sample-and-hold. The modulator output is processed by a finite impulse response (FIR) digital filter. The on-chip filtering combined with a high oversampling ratio reduces the external antialias requirements to first order in most cases. The digital filter frequency response can be programmed to be either low-pass or band-pass.

The AD7723 provides 16-bit performance for input bandwidths up to 460 kHz at an output word rate up to 1.2 MHz. The sample rate, filter corner frequencies, and output word rate are set by the crystal oscillator or external clock frequency.

Sigma-Delta ADC

AD7723

FUNCTIONAL BLOCK DIAGRAM

SDO/

DB8

REF2 REF1

DV

DD

DGND

XTAL_OFF XTAL

CLKIN DGND/DB15

DGND/DB14 SCR/DB13

SLDR/DB12 SLP/DB11 TSI/DB10 FSO/DB9

FIR

FSI/ DB6

2.5V

REFERENCE

XTAL

CLOCK

SCO/

DB7

AV

AGND

VIN(+) VIN(–)

UNI

HALF_PWR

STBY MODE 1 MODE 2

SYNC

DVDD/CS

CFMT/RD

DGND/DRDY

DGND/DB0

DGND/

DB1

AD7723

MODULATOR

DGND/

DB2

DB3

CONTROL

LOGIC

DOE/

SFMT/

DB4

Figure 1.

FILTER

DB5

DD

The part provides an on-chip 2.5 V reference. Alternatively, an external reference can be used.

A power-down mode reduces the idle power consumption to 200 µW.

The AD7723 is available in a 44-lead MQFP package and is specified over the industrial temperature range from –40°C to +85°C.

01186-001

Data can be read from the device in either serial or parallel format. A stereo mode allows data from two devices to share a single serial data line. All interface modes offer easy, high speed connections to modern digital signal processors.

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

Two input modes are provided, allowing both unipolar and bipolar input ranges.

AD7723

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REVISION HISTORY

5/05—Rev. B to Rev. C

Changes to Format ............................................................. Universal

Changes to Figure 6.......................................................................... 8

Changes to System Synchronization............................................ 23

Updated Outline Dimensions....................................................... 29

Changes to the Ordering Guide.................................................... 29

10/03—Rev. A to Rev. B C

hanges to Ordering Guide............................................................ 8

Outline Dimensions Updated ....................................................... 23

9/02—Data Sheet changed from Rev. 0 to Rev. A

ew TPCs 1 and 2 Added ............................................................. 13

N

Edits to Figures 17 and 18 ............................................................. 18

Outline Dimensions Updated....................................................... 23

Rev. C | Page 2 of 32

AD7723

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SPECIFICATIONS

AVDD = DVDD = 5 V ± 5%; AGND = AGND1 = AGND2 = DGND = 0 V; f otherwise noted.

Table 1.

B Version Parameter Test Conditions/Comments Min Typ Max Unit

DYNAMIC SPECIFICATIONS f

Decimate by 32

Bipolar Mode

Signal to Noise

Full Power 2.5 V reference 87 90 dB 3 V reference 88.5 91 dB

Half Power 86.5 89 dB Total Harmonic Distortion Spurious-Free Dynamic Range4 2.5 V reference −92 dB

3 V reference −90 dB

Unipolar Mode

Signal to Noise 87 dB Total Harmonic Distortion4 −89 dB Spurious-Free Dynamic Range4 −90 dB Band-Pass Filter Mode

Bipolar Mode

Signal to Noise 76 79 dB

Decimate by 16

Bipolar Mode

Signal to Noise Measurement bandwidth = 0.383 × F

2.5 V reference 82 86 dB 3 V reference 83 87 dB

Signal to Noise Measurement bandwidth = 0.5 × F Total Harmonic Distortion4 2.5 V reference −88 dB Spurious-Free Dynamic Range4 3 V reference −86 dB

2.5 V reference −90 dB 3 V reference −88 dB

Unipolar Mode

Signal to Noise Measurement bandwidth = 0.383 × F Signal to Noise Measurement bandwidth = 0.5 × F Total Harmonic Distortion4 −89 dB

DIGITAL FILTER RESPONSE

Low-Pass Decimate by 32

0 kHz to f f

/66.9 −3 dB

CLKIN

f

/64 −6 dB

CLKIN

f

/51.9 to f

CLKIN

Group Delay 1293/2 f Settling Time 1293/f

/83.5 ±0.001 dB

CLKIN

1

= 19.2 MHz; REF2 = 2.5 V; TA = T

CLKIN

2, 3

4

HALF_PWR = 0 to 1

= 10 MHz when HALF_PWR = 1

CLKIN

−96 −90 dB

O

78 81.5 dB

84 dB

O

81 dB

/2 −90 dB

CLKIN

to T

MIN

CLKIN

MAX

, unless

Rev. C | Page 3 of 32

AD7723

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B Version Parameter Test Conditions/Comments Min Typ Max Unit

Low-Pass Decimate by 16

0 kHz to f f

/33.45 −3 dB

CLKIN

f

/32 −6 dB

CLKIN

f

/25.95 to f

CLKIN

Group Delay 541/2 f Settling Time 541/f

Band-Pass Decimate by 32

f

/51.90 to f

CLKIN

f

/62.95, f

CLKIN

f

/64, f

CLKIN

0 kHz to f Group Delay 1293/2 f Settling Time 1293/f

Output Data Rate, F

Decimate by 32 f Decimate by 166 f

ANALOG INPUTS

Full-Scale Input Span VIN(+) − VIN(−)

Bipolar Mode ±4/5 × V

Unipolar Mode 0 8/5 × V Absolute Input Voltage VIN(+) − VIN(−) AGND AV Input Sampling Capacitance 2 pF Input Sampling Rage, f

CLOCK

CLKIN Duty Ratio 45 55 %

REFERENCE

REF1 Output Resistance 3 kΩ Using Internal Reference

REF2 Output Voltage 2.39 2.54 2.69 V

REF2 Output Voltage Drift 60 ppm/°C Using External Reference

REF2 Input Impedance REF1 = AGND 4 kΩ

REF2 External Voltage Range 1.2 2.5 3.15 V

STATIC PERFORMANCE

Resolution 16 Bits Differential Nonlinearity Guaranteed monotonic ±0.5 ±1 LSB Integral Nonlinearity ±2 LSB DC CMRR 80 dB Offset Error ±20 mV Gain Error

LOGIC INPUTS (EXCLUDING CLKIN)

V

, Input High Voltage 2.0 V

INH

V

, Input High Voltage 0.8 V

INL

CLOCK INPUT (CLKIN)

V

, Input High Voltage 3.8 V

INH

V

, Input High Voltage 0.4 V

INL

ALL LOGIC INPUTS

IIN, Input Current VIN = 0 V to DV CIN, Input Capacitance 10 pF

/41.75 ±0.001 dB

CLKIN

/2 −90 dB

CLKIN

/41.75 ±0.001 dB

CLKIN

/33.34 −3 dB

CLKIN

/32 −6 dB

CLKIN

/83.5, f

CLKIN

5

O

/25.95 to f

CLKIN

/2 −90 dB

CLKIN

/32

CLKIN

/16

CLKIN

19.2 MHz

±0.5 % FSR

DD

±10 µA

CLKIN

REF2

DD

V V V

Rev. C | Page 4 of 32

AD7723

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B Version

Parameter Test Conditions/Comments Min Typ Max Unit

LOGIC OUPUTS

VOH, Output High Voltage |I VOL, Output Low Voltage |I

POWER SUPPLIES

AV

DD

I

AVDD

HALF_PWR = Logic High 25 33 mA DV

DD

I

DVDD

HALF_PWR = Logic High 15 20 mA Power Consumption

1

Operating temperature range is −40°C to +85°C (B: Version).

2

Typical values for SNR apply for parts soldered directly to the PCB ground plane.

3

Dynamic specifications apply for input signal frequencies from dc to 0.0240 × f

4

When using the internal reference, THD and SFDR specifications apply only to input signals above 10 kHz with a 10 µF decoupling capacitor between REF2 and

AGND2. At frequencies below 10 kHz, THD degrades to 84 dB and SFDR degrades to 86 dB.

5

Gain error excludes reference error.

6

CLKIN and digital inputs static and equal to 0 or DVDD.

6

| = 200 µA 4.0 V

OUT

| = 1.6 mA 0.4 V

OUT

4.75 5.25 V HALF_PWR = Logic Low 50 60 mA

4.75 5.25 V HALF_PWR = Logic Low 25 35 mA

Standby Mode 200 µW

in decimate by 16 mode and from dc to 0.0120 × f

CLKIN

in decimate by 32 mode.

CLKIN

Rev. C | Page 5 of 32

AD7723

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TIMING SPECIFICATIONS

AVDD = DVDD = 5 V ± 5%; AGND = AGND1 = DGND = 0 V; f or high; T

A

= T

MIN

to T

, unless otherwise noted.

MAX

Table 2.

Parameter Symbol Min Typ Max Unit

CLKIN Frequency f CLKIN Period (t

CLK

– 1/f

) t

CLK

CLKIN Low Pulse Width t CLKIN High Pulse Width t CLKIN Rise Time t CLKIN Fall Time t FSI Setup Time t FSI Hold Time t FSI High Time

1

CLKIN to SCO Delay t SCO Period2, SCR = 1 t SCO Period2, SCR = 0 t SCO Transition to FSO High Delay t SCO Transition to FSO Low Delay t SCO Transition to SDO Valid Delay t SCO Transition from FSI

3

SDO Enable Delay Time t SDO Disable Delay Time t DRDY

High Time2

Conversion Time2 (Refer to Table 3 and Table 4) t CLKIN to

DRDY

Transition CLKIN to DATA Valid t CS

/RD Setup Time to CLKIN

CS

/RD Hold Time to CLKIN Data Access Time t Bus Relinquish Time t SYNC Input Pulse Width t SYNC Low Time before CLKIN Rising t DRDY

High Delay after Rising SYNC

DRDY

Low Delay after SYNC Low

1

FSO pulses are gated by the release of FSI (going low).

2

Guaranteed by design.

3

Frame sync is initiated on the falling edge of CLKIN.

= 19.2 MHz; CL = 50 pF; SFMT = logic low or high, CFMT = logic low

CLKIN

CLK

1

2

3

4

5

6

7

t

8

9

10

11

12

13

t

14

15

16

t

17

18

t

19

20

t

21

t

22

23

24

25

26

t

27

t

28

1 19.2 MHz

0.052 1 µs

0.45 × t

1

0.55 × t

1

5 ns 5 ns 0 5 ns 0 5 ns 1 t 25 40 ns 2 t 1 t 0 5 ns 0 5 ns 5 12 ns 60 t

CLK

+ t

2

5 20 ns 5 20 ns 2 t

16/32 t 35 50 ns

20 35 ns 0 ns

20 ns 20 35 ns

20 35 ns 1 t 0 ns 25 35 ns 2049 t

CLK

I

OL

1.6mA

TO

OUTPUT

50pF

C

L

I

OH

200µA

1.6V

01186-002

Figure 2. Load Circuit for Timing Specifications

Rev. C | Page 6 of 32

AD7723

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t

CLKIN

FSI

SCO

CLKIN

FSI

(SFMT = 1)

SCO

(CFMT = 0)

2.3V

5

0.8V

t

1

t

9

t

10

Figure 3. Serial Mode Timing for Clock Input, Frame Sync Input, and Serial Clock Output

t

8

t

14

t

4

t

6

t

8

t

9

32 CLKIN CYCLES

t

2

t

3

t

7

01186-003

t

11

FSO

(SFMT = 0)

t

11

01186-004

FSO

(SFMT = 1)

SDO

t

12

t

13

D15 D14 D13 D2 D1 D0 D15 D14

Figure 4. Serial Mode 1: Timing for Frame Sync Input, Frame Sync Output, Serial Clock Output, and Serial Data Output (See Table 3 for Control Inputs, TSI = DOE)

32 CLKIN CYCLES

CLKIN

t

8

FSI

t

SCO

(CFMT = 0)

FSO

14

t

11

t

12

t

13

SDO

D2 D1 D0 D15 D14 D13 D12 D11 D5

D3 D2 D1 D0 D15 D14

D4

Figure 5. Serial Mode 2: Timing for Frame Sync Input, Frame Sync Output, Serial Clock Output, and Serial Data Output (See Table 3 for Control Inputs, TSI = DOE)

Rev. C | Page 7 of 32

01186-005

AD7723

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32 CLKIN CYCLES

CLKIN

t

FSI

SCO

(CFMT = 0)

FSO

SDO

t

13

D3

D2

8

t

14

t

D15

12

01186-006

11

D1

D15D0

16 CLKIN CYCLES 16 CLKIN CYCLES

D14

D13 D13 D3

D2

D3

D0D1

D15 D14 D1D2 D0

Figure 6. Serial Mode 3: Timing for Frame Sync Input, Frame Sync Output, Serial Clock Output, and Serial Data Output (See Table 3 for Control Inputs, TSI = DOE)

Table 3. Serial Interface (MODE1 = 0, MODE2 = 0)

Control Inputs Serial Mode Decimation Ratio (SLDR) Digital Filter Mode (SLP) SCO Frequency (SCR) Output Data Rate SLDR SLP SCR

1 32 Low Pass f 1 32 Band Pass f 2 32 Low Pass f 2 32 Band Pass f 3 16 Low Pass f

CLKIN

/2 f

CLKIN

/2 f

CLKIN

f

/32 1 1 0

CLKIN

f

/32 1 0 0

CLKIN

/32 1 1 1

CLKIN

/32 1 0 1

CLKIN

f

/16 0 1 0

CLKIN

Table 4. Parallel Interface

Control Inputs Digital Filter Mode Decimation Ratio Output Data Rate MODE1 MODE2

Band Pass 32 f Low Pass 32 f Low Pass 16 f

/32 0 1

CLKIN

/32 1 0

CLKIN

/16 1 1

CLKIN

DOE

t

16

01186-007

SDO

t

15

Figure 7. Serial Mode Timing for Data Output Enable and Serial Data Output

Rev. C | Page 8 of 32

AD7723

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t

18

CLKIN

t

19

DRDY

t

19

t

17

t

20

DB0–DB15

CLKIN

DRDY

RD/CS

DB0–DB15

WORD N – 1 WORD N + 1

Figure 8. Parallel Mode Read Timing,

WORD N

CS

and RD Tied Logic Low

t

18

t

19

t

22

t

21

22

t

23

21

VALID DATA

Figure 9. Parallel Mode Read Timing,

t

19

t

24

CS

= RD

t

28

01186-008

01186-009

CLKIN

t

26

SYNC

t

25

DRDY

t

27

Figure 10. SYNC Timing

Rev. C | Page 9 of 32

01186-010

AD7723

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ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 5.

Parameter Rating

DVDD to DGND −0.3 V to +7 V AVDD, AV AVDD, AV AGND, AGND1 to DGND

Digital Inputs to DGND −0.3 V to DVDD + 0.3 V Digital Outputs to DGND −0.3 V to DVDD + 0.3 V VIN (+), VIN(−) to AGND −0.3 V to AVDD + 0.3 V REF1 to AGND −0.3 V to AVDD + 0.3 V REF2 to AGND −0.3 V to AVDD + 0.3 V Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C

θJA Thermal Impedance

Lead Temperature, Soldering

Vapor Phase (60 sec) 215°C

Infrared (15 sec) 220°C

to AGND −0.3 V to +7 V

DD1

to DV

DD

−1 V to +1 V

−0.3 V to +0.3 V

95°C/W

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. C | Page 10 of 32

ANALOG DEVICES AD7723 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

TIMING SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION