ANALOG DEVICES AD7715 Service Manual

3 V/5 V, 450 μA

FEATURES

Charge-balancing ADC

16-bits no missing codes

0.0015% nonlinearity

Programmable gain front end

Gains of 1, 2, 32 and 128

Differential input capability
Three-wire serial interface
SPI-, QSPI™-, MICROWIRE™-, and DSP-compatible
Ability to buffer the analog input
3 V (AD7715-3) or 5 V (AD7715-5) operation
Low supply current: 450 μA maximum @ 3 V supplies
Low-pass filter with programmable output update
16-lead SOIC/PDIP/TSSOP

GENERAL DESCRIPTION

The AD7715 is a complete analog front end for low frequency
measurement applications. The part can accept low level input
signals directly from a transducer and outputs a serial digital
word. It employs a Σ-Δ conversion technique to realize up to
16 bits of no missing codes performance. The input signal is
applied to a proprietary programmable gain front end based
around an analog modulator. The modulator output is processed
by an on-chip digital filter. The first notch of this digital filter
can be programmed via the on-chip control register allowing
adjustment of the filter cutoff and output update rate.

The AD7715 features a differential analog input as well as a
differential reference input. It operates from a single supply (3 V
or 5 V). It can handle unipolar input signal ranges of 0 mV to
20 mV, 0 mV to 80 mV, 0 V to 1.25 V and 0 V to 2.5 V. It can
also handle bipolar input signal ranges of ±20 mV, ±80 mV,
±1.25 V and ±2.5 V. These bipolar ranges are referenced to the
negative input of the differential analog input. The AD7715
thus performs all signal conditioning and conversion for a
single channel system.

The AD7715 is ideal for use in smart, microcontroller, or DSP­based systems. It features a serial interface that can be configured
for three-wire operation. Gain settings, signal polarity, and
update rate selection can be configured in software using the
input serial port. The part contains self-calibration and system
calibration options to eliminate gain and offset errors on the
part itself or in the system.

16-Bit, Sigma-Delta ADC

AD7715

FUNCTIONAL BLOCK DIAGRAM

AV

REF IN(–) REF IN(+)

CHARGE BALANCING

AIN(+)
AIN(–)

AD7715

PGABUFFER

A = 1 TO 128

SERIAL
INTERFACE

Σ-∆

MODULATOR

REGISTER BANK

AGND

Figure 1.

DGND

CMOS construction ensures very low power dissipation, and
power-down mode reduces the standby power consumption to
50 μW typical. The part is available in a 16-lead, 0.3 inch-wide,
plastic dual-in-line package (PDIP) as well as a 16-lead 0.3 inch
wide small outline (SOIC_W) package and a 16-lead TSSOP
package.

PRODUCT HIGHLIGHTS

1. The AD7715 consumes less than 450 μA in total supply

current at 3 V supplies and 1 MHz master clock, making it
ideal for use in low-power systems. Standby current is less
than 10 μA.

2. The programmable gain input allows the AD7715 to accept

input signals directly from a strain gage or transducer
removing a considerable amount of signal conditioning.

3. The AD7715 is ideal for microcontroller or DSP processor

applications with a three-wire serial interface reducing the
number of interconnect lines and reducing the number
of optocouplers required in isolated systems. The part
contains on-chip registers which allow software control
over output update rate, input gain, signal polarity, and
calibration modes.

4. The part features excellent static performance specifications

with 16-bits no missing codes, ±0.0015% accuracy, and low
rms noise (<550 nV). Endpoint errors and the effects of
temperature drift are eliminated by on-chip calibration
options, which remove zero-scale and full-scale errors.

DD

ADC

DV

DD

DIGITAL

FILTER

CLOCK

GENERATION

MCLK IN
MCLK OUT

RESET

SCLK
CS
DIN
DOUT
DRDY

8519-001

Rev. D

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2009 Analog Devices, Inc. All rights reserved.

AD7715

TABLE OF CONTENTS

Features.............................................................................................. 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

AD7715-5 ...................................................................................... 3

AD7715-3 ...................................................................................... 5

Timing Characteristics ................................................................ 8

Absolute Maximum Ratings............................................................ 9

ESD Caution.................................................................................. 9

Pin Configuration And Function Descriptions.......................... 10

Terminology .................................................................................... 11

On-Chip Registers.......................................................................... 12

Communications Register (RS1, RS0 = 0, 0).......................... 13

Setup Register (RS1, RS0 = 0, 1); Power On/Reset Status:

28 Hex .......................................................................................... 14

Test Register (RS1, RS0 = 1, 0).................................................. 15

Data Register (RS1, RS0 = 1, 1) ................................................ 15

Output Noise ................................................................................... 16

AD7715-5 .................................................................................... 16

AD7715-3 .................................................................................... 17

Calibration Sequences.................................................................... 18

Circuit Description......................................................................... 19

Analog Input............................................................................... 19

Reference Input........................................................................... 21

Digital Filtering........................................................................... 21

Analog Filtering.......................................................................... 23

Calibration................................................................................... 23

Using the AD7715.......................................................................... 26

Clocking and Oscillator Circuit ............................................... 26

System Synchronization ............................................................ 26

Reset Input .................................................................................. 27

Standby Mode............................................................................. 27

Accuracy...................................................................................... 27

Drift Considerations.................................................................. 27

Power Supplies ............................................................................ 28

Digital Interface.......................................................................... 29

Configuring the AD7715............................................................... 31

Microcontroller/Microprocessor Interfacing ............................. 32

AD7715 to 68HC11 Interface................................................... 32

AD7715 to 8XC51 Interface...................................................... 33

AD7715 to ADSP-2103/ADSP-2105 Interface ....................... 33

Code For Setting Up The AD7715............................................... 34

C Code for Interfacing AD7715 to 68HC11........................... 34

Applications Information.............................................................. 36

Pressure Measurement............................................................... 36

Temperature Measurement....................................................... 37

Smart Transmitters..................................................................... 38

Outline Dimensions....................................................................... 39

Ordering Guide .......................................................................... 40

REVISION HISTORY

12/09—Rev. C to Rev. D

Updated Format..................................................................Universal

Changes to Table 5............................................................................ 9

Updated Outline Dimensions....................................................... 39

2/00—Rev. B to Rev. C

Rev. D | Page 2 of 40

AD7715

SPECIFICATIONS

AD7715-5

AVDD = 5 V, DVDD = 3 V or 5 V, REF IN(+) = 2.5 V; REF IN(−) = AGND; f
T

MIN

to T

, unless otherwise noted.

MAX

Table 1.

Parameter1 Min Typ Max Unit Conditions/Comments

STATIC PERFORMANCE

No Missing Codes 16 Bits Guaranteed by design; filter notch ≤ 60 Hz

Output Noise

Integral Nonlinearity ±0.0015 % of FSR Filter notch ≤ 60 Hz

Unipolar Offset Error2

Unipolar Offset Drift3 0.5 μV/°C

Bipolar Zero Error2 See Table 15 to Table 2 2

Bipolar Zero Drift3

Positive Full-Scale Error

Full-Scale Drift

Gain Error

Gain Drift

2, 6

See Table 15 to Table 2 2

3, 7

3, 5

2, 4

See Table 15 to Table 2 2

Bipolar Negative Full-Scale Error2

Bipolar Negative Full-Scale Drift3

0.5 ppm of

±0.0015

1

0.6 μV/°C For gains of 32 and 128
ANALOG INPUTS/REFERENCE INPUTS Specifications for AIN and REF IN unless noted

Input Common-Mode Rejection
(CMR)

90
Normal-Mode 50 Hz Rejection8 98 dB For filter notches of 25 Hz, 50 Hz, ±0.02 × f
Normal-Mode 60 Hz Rejection8

Common-Mode 50 Hz Rejection8

Common-Mode 60 Hz Rejection8

98

150

150
Common-Mode Voltage Range9 AGND AVDD V AIN for the BUF bit of setup register = 0 and REF IN
Absolute AIN/REF IN Voltage8
Absolute/Common-Mode AIN

9

Voltage

AIN DC Input Current8

AIN Sampling Capacitance8

AGND – 0.03

AGND + 0.05 AV

AIN Differential Voltage Range10 0 to +V

±V

AIN Input Sampling Rate, fS GAIN × f
f
REF IN(+) − REF IN(−) Voltage 2.5 V nom ±1% for specified performance; functional with

REF IN Input Sampling Rate, fS f

LOGIC INPUTS

Input Current ±10 μA
All Inputs Except MCLK IN

V

, Input Low Voltage 0.8 V DVDD = 5 V

INL

V

, Input Low Voltage 0.4 V DVDD = 3.3 V

INL

V

, Input High Voltage 2.4 V DVDD = 5 V

INH

V

, Input High Voltage 2.0 V

INH

MCLK IN Only

V

, Input Low Voltage 0.8 V DVDD = 5 V

INL

V

, Input Low Voltage 0.4 V DVDD = 3.3 V

INL

V

, Input High Voltage 3.5 V DVDD = 5 V

INH

V

, Input High Voltage 2.5 V DVDD = 3.3 V

INH

Table 15 to Table 1 8

See

Table 15 to Table 2 2

See

0.5

0.5

dB At dc; typically 102 dB

dB For filter notches of 20 Hz, 60 Hz, ±0.02 × f

dB For filter notches of 25 Hz, 50 Hz, ±0.02 × f

dB For filter notches of 20 Hz, 60 Hz, ±0.02 × f

AV

DD

DD

1

10

/GAIN11 nom

REF

/GAIN nom

REF

/64 For gains of 1 and 2

CLK IN

/8 For gains of 32 and 128

CLK IN

/64

CLK IN

= 2.4576 MHz, unless otherwise noted. All specifications

CLK IN

Depends on filter cutoffs and selected gain

μV/°C

μV/°C

FSR/°C

% of FSR Typically ±0.0004%

μV/°C For gains of 1 and 2

NOTCH

NOTCH

NOTCH

NOTCH

+ 0.03 V AIN for the BUF bit of setup register = 0 and REF IN

− 1.5 V BUF bit of setup register = 1

nA

pF

B

Unipolar input range (

Bipolar input range (

lower V

REF

/U bit of setup register = 1)

B

/U bit of setup register = 0)

Rev. D | Page 3 of 40

AD7715

Parameter1 Min Typ Max Unit Conditions/Comments

LOGIC OUTPUTS (Including MCLK OUT)

VOL, Output Low Voltage 0.4 V I
VOL, Output Low Voltage

VOH, Output High Voltage

VOH, Output High Voltage

0.4

4.0

− 0.6

DV

DD

V

V

V
Floating State Leakage Current ±10 μA
Floating State Output Capacitance13 9 pF
Data Output Coding Binary Unipolar mode

Offset binary Bipolar mode

1

Temperature range as follows: A version, −40°C to +85°C.

2

A calibration is effectively a conversion, so these errors are of the order of the conversion noise shown in Table 15 to Table 22. This applies after calibration at the

temperature of interest.

3

Recalibration at any temperature removes these drift errors.

4

Positive full-scale error includes zero-scale errors (unipolar offset error or bipolar zero error) and applies to both unipolar and bipolar input ranges.

5

Full-scale drift includes zero-scale drift (unipolar offset drift or bipolar zero drift) and applies to both unipolar and bipolar input ranges.

6

Gain error does not include zero-scale errors. It is calculated as full-scale error–unipolar offset error for unipolar ranges and full-scale error–bipolar zero error for

bipolar ranges.

7

Gain error drift does not include unipolar offset drift/bipolar zero drift. It is effectively the drift of the part if zero scale calibrations only were performed.

8

These numbers are guaranteed by design and/or characterization.

9

This common-mode voltage range is allowed provided that the input voltage on AIN(+) or AIN(−) does not go more positive than AVDD + 30 mV or go more negative

than AGND − 30 mV.

10

The analog input voltage range on AIN(+) is given here with respect to the voltage on AIN(−). The absolute voltage on the analog inputs should not go more positive
than AVDD + 30 mV or go more negative than AGND − 30 mV.

11

V

= REF IN(+) − REF IN(−).

REF

12

These logic output levels apply to the MCLK OUT only when it is loaded with one CMOS load.

13

Sample tested at 25°C to ensure compliance.

= 800 μA except for MCLK OUT12; DVDD = 5 V

SINK

= 100 μA except for MCLK OUT12; DVDD = 3.3 V

I

SINK

= 200 μA except for MCLK OUT12; DVDD = 5 V

I

SOURCE

= 100 μA except for MCLK OUT12; DVDD = 3.3 V

I

SOURCE

Rev. D | Page 4 of 40

AD7715

AD7715-3

AVDD = 3 V, DVDD = 3 V, REF IN (+) = 1.25 V; REF IN(−) = AGND; f
to T

, unless otherwise noted.

MAX

Table 2.

Parameter1 Min Typ Max Unit Conditions/Comments

STATIC PERFORMANCE

No Missing Codes 16 Bits Guaranteed by design; filter notch ≤ 60 Hz
Output Noise

Integral Nonlinearity ±0.0015 % of FSR Filter notch ≤ 60 Hz
Unipolar Offset Error2

Unipolar Offset Drift3 0.2 μV/°C
Bipolar Zero Error2 See Tabl e 15 to Table 22

Bipolar Zero Drift3

Positive Full-Scale Error

Full-Scale Drift

Gain Error

Gain Drift

2, 6

See Tabl e 15 to Table 22

3, 7

3, 5

2, 4

See Tabl e 15 to Table 22

Bipolar Negative Full-Scale Error2

Bipolar Negative Full-Scale Drift3

0.2 μV/°C

0.2 μV/°C

0.2 ppm of

±0.003 % of FSR Typically ±0.0004%

1 μV/°C For gains of 1 and 2

0.6 μV/°C For gains of 32 and 128
ANALOG INPUTS/REFERENCE INPUTS Specifications for AIN and REF IN unless noted

Input Common-Mode Rejection

90 dB At dc; tpically 102 dB

(CMR)
Normal-Mode 50 Hz Rejection8 98 dB For filter notches of 25 Hz, 50 Hz, ±0.02 × f
Normal-Mode 60 Hz Rejection8

Common-Mode 50 Hz Rejection8

Common-Mode 60 Hz Rejection8

98 dB For filter notches of 20 Hz, 60 Hz, ±0.02 × f

150 dB For filter notches of 25 Hz, 50 Hz, ±0.02 × f

150 dB For filter notches of 20 Hz, 60 Hz, ±0.02 × f

Common-Mode Voltage Range9 AGND AVDD V AIN for BUF bit of setup register = 0 and REF IN
Absolute AIN/REF IN Voltage8
Absolute/Common-Mode AIN

9

Voltage

AIN DC Input Current8

AIN Sampling Capacitance8

AGND − 0.03 AV

AGND + 0.05 AV

1 nA

10 pF

AIN Differential Voltage Range10 0 to

±V

AIN Input Sampling Rate, fS GAIN × f
f
REF IN(+) − REF IN(−) Voltage 1.25 V nom ±1% for specified performance; functional with

REF IN Input Sampling Rate, fS f

LOGIC INPUTS

Input Current ±10 μA
All Inputs Except MCLK IN

V

, Input Low Voltage 0.8 V

INL

V

, Input High Voltage 2.0 V

INH

MCLK IN Only

V

, Input Low Voltage 0.4 V

INL

V

, Input High Voltage 2.5 V

INH

Table 18 to Table 2 2

See

Table 15 to Table 2 2

See

+V

/GAIN11

REF

/GAIN nom

REF

CLK IN

/8 For gains of 32 and 128

CLK IN

/64

CLK IN

/64 For gains of 1 and 2

= 2.4576 MHz, unless otherwise noted. All specifications T

CLK IN

Depends on filter cutoffs and selected gain

FSR/°C

+ 0.03 V AIN for BUF bit of setup register = 0 and REF IN

DD

− 1.5 V BUF bit of setup register = 1

DD

nom

Unipolar input range (

Bipolar input range (

lower V

REF

B/U bit of setup register = 1)

B/U bit of setup register = 0)

NOTCH

NOTCH

NOTCH

NOTCH

MIN

Rev. D | Page 5 of 40

AD7715

Parameter1 Min Typ Max Unit Conditions/Comments

LOGIC OUTPUTS (Including MCLK OUT)

VOL, Output Low Voltage 0.4 V I
VOH, Output High Voltage DVDD − 0.6 V

Floating State Leakage Current ±10 μA
Floating State Output Capacitance13 9 pF
Data Output Coding Binary Unipolar mode

Offset binary Bipolar mode

1

Temperature range as follows: A version, −40°C to +85°C.

2

A calibration is effectively a conversion, so these errors are of the order of the conversion noise shown in Table 15 to Table 22. This applies after calibration at the

temperature of interest.

3

Recalibration at any temperature removes these drift errors.

4

Positive full-scale error includes zero-scale errors (unipolar offset error or bipolar zero error) and applies to both unipolar and bipolar input ranges.

5

Full-scale drift includes zero-scale drift (unipolar offset drift or bipolar zero drift) and applies to both unipolar and bipolar input ranges.

6

Gain error does not include zero-scale errors. It is calculated as full-scale error–unipolar offset error for unipolar ranges and Full-Scale Error–Bipolar Zero Error for

bipolar ranges.

7

Gain error drift does not include unipolar offset drift/bipolar zero drift. It is effectively the drift of the part if zero scale calibrations only were performed.

8

These numbers are guaranteed by design and/or characterization.

9

This common-mode voltage range is allowed provided that the input voltage on AIN(+) or AIN(−) does not go more positive than AVDD + 30 mV or go more negative

than AGND − 30 mV.

10

The analog input voltage range on AIN(+) is given here with respect to the voltage on AIN(−). The absolute voltage on the analog inputs should not go more positive
than AVDD + 30 mV or go more negative than AGND − 30 mV.

11

V

= REF IN(+) − REF IN(−).

REF

12

These logic output levels apply to the MCLK OUT only when it is loaded with one CMOS load.

13

Sample tested at 25°C to ensure compliance.

= 100 μA except for MCLK OUT12

SINK

= 100 μA except for MCLK OUT12

I

SOURCE

Rev. D | Page 6 of 40

AD7715

AVDD = 3 V to 5 V, DVDD = 3 V to 5 V, REF IN(+) = 1.25 V (AD7715-3) or 2.5 V (AD7715-5); REF IN(−) = AGND; MCLK IN = 1 MHz to

2.4576 MHz, unless otherwise noted. All specifications T

Table 3.

Parameter

SYSTEM CALIBRATION

Positive Full-Scale Calibration Limit1 (1.05 ×

Negative Full-Scale Calibration Limit1

Offset Calibration Limit2 −(1.05 ×

Input Span2

(2.1 × V
POWER REQUIREMENTS

Power Supply Voltages

AVDD Voltage (AD7715-3) 3 3.6 V For specified performance
AVDD Voltage (AD7715-5) 4.75 5.25 V For specified performance
DVDD Voltage 3 5.25 V For specified performance

Power Supply Currents

AVDD Current AVDD = 3.3 V or 5 V. gain = 1 to 128 (f

0.27 mA Typically 0.2 mA; BUF bit of the setup register = 0

0.6 mA Typically 0.4 mA; BUF bit of the setup register = 1, AVDD

0.5 mA Typically 0.3 mA; BUF bit of the setup register = 0

1.1 mA Typically 0.8 mA; BUF bit of the setup register = 1
DVDD Current4 Digital inputs = 0 V or DVDD; external MCLK IN

0.18 mA Typically 0.15 mA. DVDD = 3.3 V. f

0.4 mA Typically 0.3 mA. DVDD = 5 V. f

0.5 mA Typically 0.4 mA. DVDD = 3.3 V. f

0.8 mA Typically 0.6 mA. DVDD = 5 V. f

Power Supply Rejection5 Depends on gain6 dB
Normal-Mode Power Dissipation4

1.5 mW BUF bit = 0. all gains 1 MHz clock

2.65 mW BUF bit = 1. all gains 1 MHz clock

3.3 mW BUF bit = 0. Gain = 32 or 128 @ f

5.3 mW BUF bit = 1. Gain = 32 or 128 @ f

Normal-Mode Power Dissipation4

3.25 mW BUF bit = 0; all gains 1 MHz clock

5 mW BUF bit = 1; all gains 1 MHz clock

6.5 mW BUF bit = 0; gain = 32 or 128 @ f

9.5 mW BUF bit = 1; gain = 32 or 128 @ f

Standby (Power-Down) Current7 20 μA External MCLK IN = 0 V or DVDD. typically 10 μA; VDD = 5 V
Standby (Power-Down) Current7

1

After calibration, if the analog input exceeds positive full scale, the converter outputs all 1s. If the analog input is less than negative full scale, then the device outputs

all 0s.

2

These calibration and span limits apply provided the absolute voltage on the analog inputs does not exceed AVDD + 30 mV or go more negative than AGND − 30 mV.

The offset calibration limit applies to both the unipolar zero point and the bipolar zero point.

3

Assumes CLK Bit of setup register is set to correct status corresponding to the master clock frequency.

4

When using a crystal or ceramic resonator across the MCLK pins as the clock source for the device, the DVDD current and power dissipation will vary depending on the

crystal or resonator type (see the Clocking and Oscillator Circuit section).

5

Measured at dc and applies in the selected pass-band. PSRR at 50 Hz exceeds 120 dB with filter notches of 25 Hz or 50 Hz. PSRR at 60 Hz exceeds 120 dB with filter

notches of 20 Hz or 60 Hz.

6

PSRR depends on gain. Gain of 1:85 dB typical; gain of 2:90 dB typical; gains of 32 and 128:95 dB typical.

7

If the external master clock continues to run in standby mode, the standby current increases to 50 μA typical. When using a crystal or ceramic resonator across the

MCLK pins as the clock source for the device, the internal oscillator continues to run in standby mode and the power dissipation depends on the crystal or resonator
type (see the Standby Mode section).

Min

Typ

−(1.05 ×

0.8 ×
V

REF

/GAIN

V GAIN Is the selected PGA gain (1, 2, 32, or 128)

AV

AV

10 μA External MCLK IN = 0 V or DV

MIN

to T

, unless otherwise noted.

MAX

Max

)/GAIN

V

REF

V

)/GAIN

REF

)/GAIN

V

REF

)/GAIN V GAIN Is the selected PGA gain (1, 2, 32, or 128)

REF

Unit Conditions/Comments

V GAIN Is the selected PGA gain (1, 2, 32, or 128)

V GAIN Is the selected PGA gain (1, 2, 32, or 128)

V GAIN Is the selected PGA gain (1, 2, 32, or 128)

= 1 MHz) or

gain = 1 or 2 (f

= 2.4576 MHz)

CLK IN

= 3.3 V or 5 V; gain = 32 or 128 (f

= DVDD = 3.3 V; digital inputs = 0 V or DVDD; external

DD

CLK IN

= 2.4576 MHz)3

CLK IN

= 1 MHz

CLK IN

= 1 MHz

CLK IN

= 2.4576 MHz

CLK IN

= 2.4576 MHz

CLK IN

MCLK IN

= 2.4576 MHz

CLK IN

= 2.4576 MHz

CLK IN

= DVDD = 5 V. digital inputs = 0 V or DVDD; external

DD

MCLK IN

= 2.4576 MHz

CLK IN

= 2.4576 MHz

CLK IN

. typically 5 μA; VDD = 3.3 V

DD

Rev. D | Page 7 of 40

AD7715

TIMING CHARACTERISTICS

DVDD = 3 V to 5.25 V; AVDD = 3 V to 5.25 V; AGND = DGND = 0 V; f
otherwise noted.

Table 4.

Limit at T

Parameter

3, 4

f

CLKIN

1, 2

(A Version)

400 kHz min

2.5 MHz max
t

0.4 × t

CLK IN LO

t

0.4 × t

CLK IN HI

t1 500 × t
t2

100 ns min

, T

MAX

MIN

Unit Conditions/Comments

Master clock frequency: crystal oscillator or externally supplied for specified
performance

ns min Master clock input low time; t

CLK IN

ns min Master clock input high time

CLK IN

ns nom

CLK IN

DRDY
RESET

Read Operation

t3
t4

5

t

0 ns min SCLK falling edge to data valid delay

5

0 ns min
120 ns min

DRDY
CS

falling edge to SCLK rising edge setup time

80 ns max DVDD = 5 V
100 ns max DVDD = 3.3 V
t6 100 ns min SCLK high pulsewidth
t7 100 ns min SCLK low pulsewidth

CS

t8

6

t

10 ns min Bus relinquish time after SCLK rising edge

9

0 ns min

rising edge to SCLK rising edge hold time

60 ns max DVDD = +5 V
100 ns max DVDD = +3.3 V

t10 100 ns max

SCLK falling edge to DRDY

Write Operation

CS

t11

120 ns min

falling edge to SCLK rising edge setup time
t12 30 ns min Data valid to SCLK rising edge setup time
t

20 ns min Data valid to SCLK rising edge hold time

13

t

100 ns min SCLK high pulsewidth

14

t

100 ns min SCLK low pulsewidth

15

t

16

1

Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V.

2

See Figure 8 and Figure 9.

3

CLKIN Duty Cycle range is 45% to 55%. CLKIN must be supplied whenever the AD7715 is not in standby mode. If no clock is present in this case, the device can draw

higher current than specified and possibly become uncalibrated.

4

The AD7715 is production tested with f

5

These numbers are measured with the load circuit of Figure 2 and defined as the time required for the output to cross the VOL or VOH limits.

6

These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then

extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.

7

DRDY

returns high after the first read from the device after an output update. The same data can be read again, if required, while

subsequent reads do not occur close to the next output update.

0 ns min

at 2.4576 MHz (1 MHz for some IDD tests). It is guaranteed by characterization to operate at 400 kHz.

CLKIN

TO

OUTPUT

PIN

50pF

Figure 2. Load Circuit for Access Time and Bus Relinquish Time

rising edge to SCLK rising edge hold time

CS

= 2.4576 MHz; Input Logic 0 = 0 V, Logic 1 = DVDD, unless

CLKIN

CLK IN

= 1/f

CLK IN

high time

pulsewidth

to CS setup time

high7

DRDY

is high although take care that

(800µA AT DVDD = 5V

I

SINK

100µA AT DV

+1.6V

I

(200µA AT DVDD = 5V

SOURCE

100µA AT DV

DD

= 3.3V)

= 3.3V)

DD

08519-002

Rev. D | Page 8 of 40

AD7715

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 5.

Parameter Rating

AVDD to AGND −0.3 V to +7 V
AVDD to DGND −0.3 V to +7 V
AVDD to DVDD −0.3 V to +7 V
DVDD to AGND −0.3 V to +7 V
DVDD to DGND −0.3 V to +7 V
DGND to AGND −0.3 V to +7 V
Analog Input Voltage to AGND −0.3 V to AVDD + 0.3 V
Reference Input Voltage to AGND −0.3 V to AVDD + 0.3 V
Digital Input Voltage to DGND −0.3 V to DVDD + 0.3 V
Digital Output Voltage to DGND −0.3 V to DVDD + 0.3 V
Operating Temperature Range

Commercial (A Version) −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
Plastic DIP Package, Power Dissipation 450 mW

θJA Thermal Impedance 105°C/W

Lead Temperature, (Soldering, 10 sec) 260°C
SOIC Package, Power Dissipation 450 mW

θJA Thermal Impedance 75°C/W

Lead Temperature, Reflow Soldering 260°C
TSSOP Package, Power Dissipation 450 mW

θJA Thermal Impedance 128°C/W

Lead Temperature, Reflow Soldering +260°C
Power Dissipation (Any Package) to +75°C 450 mW
ESD Rating >4000 V

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. D | Page 9 of 40

AD7715

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

SCLK

MCLK IN

MCLK OUT

CS

RESET

AV
AIN(+)
AIN(–)

DD

1
2
3

AD7715

4

TOP VIEW

5

(Not to S cale)

6
7
8

16
15
14
13
12
11
10

9

DGND
DV

DD

DIN
DOUT
DRDY
AGND

REF IN(–)

REF IN(+)

08519-003

Figure 3. Pin Configuration

Table 6. Pin Function Descriptions

Pin
No. Mnemonic Description

1 SCLK

Serial Clock. Logic input. An external serial clock is applied to this input to access serial data from the AD7715. This
serial clock can be a continuous clock with all data transmitted in a continuous train of pulses. Alternatively, it can be a
noncontinuous clock with the information being transmitted to the AD7715 in smaller batches of data.

2 MCLK IN

Master Clock Signal for the Device. This can be provided in the form of a crystal/resonator or external clock. A
crystal/resonator can be tied across the MCLK IN and MCLK OUT pins. Alternatively, the MCLK IN pin can be driven
with a CMOS-compatible clock and MCLK OUT left unconnected. The part is specified with clock input frequencies of
both 1 MHz and 2.4576 MHz.

3 MCLK OUT

When the master clock for the device is a crystal/resonator, the crystal/resonator is connected between MCLK IN and
MCLK OUT. If an external clock is applied to MCLK IN, MCLK OUT provides an inverted clock signal. This clock can be
used to provide a clock source for external circuitry.

4

Chip Select. Active low logic input used to select the AD7715. With this input hardwired low, the AD7715 can operate

CS

in its three-wire interface mode with SCLK, DIN, and DOUT used to interface to the device. CS

can be used to select
the device in systems with more than one device on the serial bus or as a frame synchronization signal in
communicating with the AD7715.

5

Logic Input. Active low input which resets the control logic, interface logic, calibration coefficients, digital filter, and

RESET

analog modulator of the part to power-on status.

6 AVDD Analog Positive Supply Voltage, 3.3 V nominal (AD7715-3) or 5 V nominal (AD7715-5).
7 AIN(+) Analog Input. Positive input of the programmable gain differential analog input to the AD7715.
8 AIN(−) Analog Input. Negative input of the programmable gain differential analog input to the AD7715.
9 REF IN(+)

Reference Input. Positive input of the differential reference input to the AD7715. The reference input is differential
with the provision that REF IN(+) must be greater than REF IN(–). REF IN(+) can lie anywhere between AV

10 REF IN(−)

11 AGND

Reference Input. Negative input of the differential reference input to the AD7715. The REF IN(−) can lie anywhere
between AV

and AGND provided REF IN(+) is greater than REF IN(–).

DD

Ground Reference Point for Analog Circuitry. For correct operation of the AD7715, no voltage on any of the other pins
should go more than 30 mV negative with respect to AGND.

12

Logic Output. A logic low on this output indicates that a new output word is available from the AD7715 data register.

DRDY

The DRDY
between output updates, the DRDY
DRDY

pin returns high upon completion of a read operation of a full output word. If no data read has taken place

line returns high for 500 × t

cycles prior to the next output update. While

CLK IN

is high, a read operation should not be attempted or in progress to avoid reading from the data register as it is
being updated. The DRDY line returns low again when the update has taken place. DRDY is also used to indicate when
the AD7715 has completed its on-chip calibration sequence.

13 DOUT

Serial data output with serial data being read from the output shift register on the part. This output shift register can
contain information from the setup register, communications register or data register depending on the register
selection bits of the communications register.

14 DIN

Serial data input with serial data being written to the input shift register on the part. Data from this input shift register
is transferred to the setup register or communications register depending on the register selection bits of the
communications register.

15 DVDD Digital Supply Voltage, 3.3 V or 5 V nominal.
16 DGND Ground reference point for digital circuitry.

and AGND.

DD

Rev. D | Page 10 of 40

AD7715

TERMINOLOGY

Integral Nonlinearity

This is the maximum deviation of any code from a straight
line passing through the endpoints of the transfer function.
The endpoints of the transfer function are zero-scale (not to
be confused with bipolar zero), a point 0.5 LSB below the first
code transition (000 … 000 to 000 … 001) and Full-Scale, a
point 0.5 LSB above the last code transition (111 … 110 to 111
… 111). The error is expressed as a percentage of full scale.

Positive Full-Scale Error

Positive Full-Scale Error is the deviation of the last code
transition (111 . . . 110 to 111 . . . 111) from the ideal AIN(+)
voltage (AIN(−) + V

/GAIN −3/2 LSBs). It applies to both

REF

unipolar and bipolar analog input ranges.

Unipolar Offset Error

Unipolar Offset Error is the deviation of the first code transition
from the ideal AIN(+) voltage (AIN(−) + 0.5 LSB) when operating
in the unipolar mode.

Bipolar Zero Error

This is the deviation of the midscale transition (0111 . . . 111 to
1000 . . . 000) from the ideal AIN(+) voltage (AIN(−) − 0.5 LSB)
when operating in the bipolar mode.

Gain Error

This is a measure of the span error of the ADC. It includes full­scale errors but not zero-scale errors. For unipolar input ranges
it is defined as (full scale error—unipolar offset error) while for
bipolar input ranges it is defined as (full-scale error—bipolar
zero error).

Bipolar Negative Full-Scale Error

This is the deviation of the first code transition from the ideal
AIN(+) voltage (AIN(−) − VREF/GAIN + 0.5 LSB), when
operating in the bipolar mode.

Positive Full-Scale Overrange

Positive full-scale overrange is the amount of overhead available
to handle input voltages on AIN(+) input greater than AIN−) +
V

/GAIN (for example, noise peaks or excess voltages due

REF

to system gain errors in system calibration routines) without
introducing errors due to overloading the analog modulator
or overflowing the digital filter.

Negative Full-Scale Overrange

This is the amount of overhead available to handle voltages
on AIN(+) below AIN(−) −V

/GAIN without overloading the

REF

analog modulator or overflowing the digital filter. Note that the
analog input accepts negative voltage peaks even in the unipolar
mode provided that AIN(+) is greater than AIN(−) and greater
than AGND − 30 mV.

Offset Calibration Range

In the system calibration modes, the AD7715 calibrates its
offset with respect to the analog input. The offset calibration
range specification defines the range of voltages that the AD7715
can accept and still calibrate offset accurately.

Full-Scale Calibration Range

This is the range of voltages that the AD7715 can accept in the
system calibration mode and still calibrate full scale correctly.

Input Span

In system calibration schemes, two voltages applied in sequence
to the AD7715’s analog input define the analog input range. The
input span specification defines the minimum and maximum
input voltages from zero to full scale that the AD7715 can accept
and still calibrate gain accurately.

Rev. D | Page 11 of 40

AD7715

ON-CHIP REGISTERS

The AD7715 contains four on-chip registers, which can be
accessed by via the serial port on the part. The first of these
is a communications register that decides whether the next
operation is a read or write operation and also decides which
register the read or write operation accesses. All communi­cations to the part must start with a write operation to the
communications register. After power-on or RESET, the
device expects a write to its communications register. The data
written to this register determines whether the next operation
to the part is a write or a read operation and also determines to
which register this read or write operation occurs. Therefore,
write access to any of the other registers on the part starts with
a write operation to the communications register followed by a
write to the selected register. A read operation from any register
on the part (including the communications register itself and

the output data register) starts with a write operation to the
communications register followed by a read operation from the
selected register. The communication register also controls the
standby mode and the operating gain of the part. The
is also available by reading from the communications register. The
second register is a setup register that determines calibration
modes, filter selection and bipolar/unipolar operation. The
third register is the data register from which the output data
from the part is accessed. The final register is a test register
that is accessed when testing the device. It is advised that the
user does not attempt to access or change the contents of the
test register as it may lead to unspecified operation of the
device. The registers are discussed in more detail in the
following sections.

DRDY

status

Rev. D | Page 12 of 40