ANALOG DEVICES AD7705 Service Manual

3 V/5 V, 1 mW, 2-/3-Channel,

FEATURES

AD7705: 2 fully differential input channel ADCs
AD7706: 3 pseudo differential input channel ADCs

16 bits no missing codes

0.003% nonlinearity
Programmable gain front end: gains from 1 to 128
3-wire serial interface

SPI®-, QSPI™-, MICROWIRE™-, and DSP-compatible

Schmitt-trigger input on SCLK

Ability to buffer the analog input

2.7 V to 3.3 V or 4.75 V to 5.25 V operation
Power dissipation 1 mW maximum @ 3 V
Standby current 8 μA maximum
16-lead PDIP, 16-lead SOIC, and 16-lead TSSOP packages

GENERAL DESCRIPTION

The AD7705/AD7706 are complete analog front ends for low
frequency measurement applications. These 2-/3-channel devices
can accept low level input signals directly from a transducer and
produce serial digital output. The devices employ a Σ-Δ
conversion technique to realize up to 16 bits of no missing codes
performance. The selected input signal is applied to a
proprietary, programmable-gain front end based around an
analog modulator. The modulator output is processed by an on­chip digital filter. The first notch of this digital filter can be pro­grammed via an on-chip control register, allowing adjustment of
the filter cutoff and output update rate.

The AD7705/AD7706 devices operate from a single 2.7 V to

3.3 V or 4.75 V to 5.25 V supply. The AD7705 features two fully
differential analog input channels; the AD7706 features three
pseudo differential input channels.

Both devices feature a differential reference input. Input signal
ranges of 0 mV to 20 mV through 0 V to 2.5 V can be
incorporated on both devices when operating with a V
and a reference of 2.5 V. They can also handle bipolar input
signal ranges of ±20 mV through ±2.5 V, which are referenced to
the AIN(−) inputs on the AD7705 and to the COMMON input
on the AD7706.

of 5 V

DD

16-Bit, Sigma-Delta ADCs

AD7705/AD7706

FUNCTIONAL BLOCK DIAGRAM

V

DD

REF IN(–) REF IN(+)

AD7705/AD7706

CHARGE

BALANCING

A/D CONVERTER

ANALOG

INPUT

CHANNELS

MCLK IN

MCLK OUT

MAX

GENERATION

GND

BUFFER

CLOCK

PGA

A = 1 ≈ 128

SERIAL INTERFACE

Figure 1.

The AD7705/AD7706 devices, with a 3 V supply and a 1.225 V
reference, can handle unipolar input signal ranges of 0 mV to
10 mV through 0 V to 1.225 V. The devices can accept bipolar
input ranges of ±10 mV through ±1.225 V. Therefore, the
AD7705/AD7706 devices perform all signal conditioning and
conversion for a 2-channel or 3-channel system.

The AD7705/AD7706 are ideal for use in smart, microcontroller,
or DSP-based systems. The devices feature a serial interface that
can be configured for 3-wire operation. Gain settings, signal
polarity, and update rate selection can be configured in software
using the input serial port. The parts contains self-calibration and
system calibration options to eliminate gain and offset errors on
the part itself or in the system. CMOS construction ensures very
low power dissipation, and the power-down mode reduces the
standby power consumption to 20 μW typ.

These parts are available in a 16-lead, wide body (0.3 inch),
plastic dual in-line package (DIP); a 16-lead, wide body
(0.3 inch), standard small outline (SOIC) package; and a low
profile, 16-lead, thin shrink small outline package (TSSOP).

Σ -Δ

MODULATOR

DIGITAL FILTER

REGISTER BANK

DRDY RESET

SCLK
CS

DIN
DOUT

01166-001

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
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Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006 Analog Devices, Inc. All rights reserved.

AD7705/AD7706

TABLE OF CONTENTS

Features.............................................................................................. 1

Reference Input........................................................................... 23

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 3

Product Highlights ........................................................................... 4

Specifications..................................................................................... 5

Timing Characteristics ................................................................ 8

Absolute Maximum Ratings............................................................ 9

ESD Caution.................................................................................. 9

Pin Configurations and Function Descriptions ......................... 10

Output Noise (5 V Operation)...................................................... 12

Output Noise (3 V Operation)...................................................... 13

Typical Performance Characteristics ........................................... 14

On-Chip Registers.......................................................................... 16

Communication Register (RS2, RS1, RS0 = 0, 0, 0)............... 16

Setup Register (RS2, RS1, RS0 = 0, 0, 1); Power-On/Reset

Status: 01 Hexadecimal..............................................................

Clock Register (RS2, RS1, RS0 = 0, 1, 0); Power-On/Reset

Status: 05 Hexadecimal..............................................................

17

19

Digital Filtering........................................................................... 23

Analog Filtering.......................................................................... 25

Calibration................................................................................... 25

Theory of Operation ...................................................................... 28

Clocking and Oscillator Circuit ............................................... 28

System Synchronization ............................................................ 28

RESET

Input ............................................................................... 29

Standby Mode............................................................................. 29

Accuracy...................................................................................... 29

Drift Considerations.................................................................. 29

Power Supplies............................................................................ 30

Supply Current............................................................................ 30

Grounding and Layout.............................................................. 30

Evaluating the Performance...................................................... 31

Digital Interface.......................................................................... 31

Configuring the AD7705/AD7706 .......................................... 33

Microcomputer/Microprocessor Interfacing ......................... 34

Data Register (RS2, RS1, RS0 = 0, 1, 1) ...................................20

Test Register (RS2, RS1, RS0 = 1, 0, 0); Power-On/Reset

Status: 00 Hexadecimal..............................................................

Zero-Scale Calibration Register (RS2, RS1, RS0 = 1, 1, 0);

Power-On/Reset Status: 1F4000 Hexadecimal...........................

Full-Scale Calibration Register (RS2, RS1, RS0 = 1, 1, 1);

Power-On/Reset Status: 5761AB HexaDecimal.........................

Circuit Description......................................................................... 21

Analog Input............................................................................... 22

Bipolar/Unipolar Input.............................................................. 22

20

20

20

Rev. C | Page 2 of 44

Code For Setting Up the AD7705/AD7706............................ 35

Applications..................................................................................... 38

Pressure Measurement............................................................... 38

Temperature Measurement....................................................... 39

Smart Transmitters..................................................................... 40

Battery Monitoring .................................................................... 41

Outline Dimensions....................................................................... 42

Ordering Guide .......................................................................... 43

AD7705/AD7706

REVISION HISTORY

5/06—Rev. B to Rev. C

Updated Format.................................................................. Universal

Changes to Table 1 ............................................................................3

Updated Outline Dimensions........................................................42

Changes to Ordering Guide...........................................................43

6/05—Rev. A to Rev. B

Updated Format.................................................................. Universal

Changed Range of Absolute Voltage on Analog Inputs Universal

Changes to Table 19 ........................................................................21

Updated Outline Dimensions........................................................42

Changes to Ordering Guide...........................................................43

11/98—Rev. 0 to Rev. A

Revision 0: Initial Version

Rev. C | Page 3 of 44

AD7705/AD7706

PRODUCT HIGHLIGHTS

1. The AD7705/AD7706 devices consume less than 1 mW at

3 V supplies and 1 MHz master clock, making them ideal
for use in low power systems. Standby current is less than 8
μA.

2. The programmable gain input allows the AD7705/AD7706

to accept input signals directly from a strain gage or
transducer, removing a considerable amount of signal
conditioning.

3. The AD7705/AD7706 are ideal for microcontroller or DSP

processor applications with a 3-wire serial interface,
reducing the number of interconnect lines and reducing
the number of opto-couplers required in isolated systems.

4. The parts feature excellent static performance

specifications with 16 bits, no missing codes, ±0.003%
accuracy, and low rms noise (<600 nV). Endpoint errors
and the effects of temperature drift are eliminated by on­chip calibration options, which remove zero-scale and full­scale errors.

Rev. C | Page 4 of 44

AD7705/AD7706

SPECIFICATIONS

VDD = 3 V or 5 V, REF IN(+) = 1.225 V with VDD = 3 V, and 2.5 V with VDD = 5 V; REF IN(−) = GND; MCLK IN = 2.4576 MHz, unless
otherwise noted. All specifications T

Table 1.

Parameter B Version1 Unit Conditions/Comments

STATIC PERFORMANCE

No Missing Codes 16 Bits min Guaranteed by design, filter notch < 60 Hz
Output Noise

Integral Nonlinearity2 ±0.003 % of FSR max Filter notch < 60 Hz, typically ±0.0003%
Unipolar Offset Error3
Unipolar Offset Drift4 0.5 μV/°C typ
Bipolar Zero Error3
Bipolar Zero Drift4 0.5 μV/°C typ For gains 1, 2, and 4

0.1 μV/°C typ For gains 8, 16, 32, 64, and 128
Positive Full-Scale Error
Full-Scale Drift
Gain Error
Gain Drift

4, 6

3, 7

4, 8

0.5

3, 5

0.5 μV/°C typ

Bipolar Negative Full-Scale Error2 ±0.003 % of FSR typ Typically ±0.001%
Bipolar Negative Full-Scale Drift4 1 μV/°C typ For gains of 1 to 4

0.6 μV/°C typ For gains of 8 to 128
ANALOG INPUTS/REFERENCE INPUTS

Common-Mode Rejection (CMR)2

VDD = 5 V

Gain = 1 96 dB typ
Gain = 2 105 dB typ
Gain = 4 110 dB typ
Gain = 8 to 128 130 dB typ

VDD = 3 V

Gain = 1 105 dB typ
Gain = 2 110 dB typ
Gain = 4 120 dB typ

Gain = 8 to 128 130 dB typ
Normal-Mode 50 Hz Rejection2 98 dB typ For filter notches of 25 Hz, 50 Hz, ±0.02 × f
Normal-Mode 60 Hz Rejection2 98 dB typ For filter notches of 20 Hz, 60 Hz, ±0.02 × f
Common-Mode 50 Hz Rejection2 150 dB typ For filter notches of 25 Hz, 50 Hz, ±0.02 × f
Common-Mode 60 Hz Rejection2 150 dB typ For filter notches of 20 Hz, 60 Hz, ±0.02 × f
Absolute/Common-Mode REF IN

Absolute/Common-Mode AIN

Voltage

Voltage

2

2, 9, 10

V
Absolute/Common-Mode AIN

Voltage

2, 9

V
AIN DC Input Current2 1 nA max
AIN Sampling Capacitance2 10 pF max
AIN Differential Voltage Range11 0 to +V

±V

MIN

to T

, unless otherwise noted.

MAX

Table 5 an d

See

Depends on filter cutoffs and selected gain

Table 7

ppm of FSR/°C
typ

Specifications for AIN and REF IN, unless otherwise
noted

GND to VDD V min to V max

GND − 100 mV V min BUF bit of setup register = 0

+ 30 mV V max

DD

GND + 50 mV V min BUF bit of setup register = 1

− 1.5 V V max

DD

/gain12 nom

REF

/gain nom

REF

Unipolar input range (B
Bipolar input range (B

NOTCH

NOTCH

NOTCH

NOTCH

/U bit of setup register = 1)

/U bit of setup register = 0)

Rev. C | Page 5 of 44

AD7705/AD7706

Parameter B Version1 Unit Conditions/Comments

AIN Input Sampling Rate, fS Gain × f
f

CLKIN

Reference Input Range

REF IN(+) − REF IN(−) Voltage 1/1.75 V min/V max

REF IN(+) − REF IN(−) Voltage 1/3.5 V min/V max

REF IN Input Sampling Rate, fS f

CLKIN

LOGIC INPUTS

Input Current

All Inputs, Except MCLK IN ±1 μA max Typically ±20 nA
MCLK IN ±10 μA max Typically ±2 μA

All Inputs, Except SCLK and MCLK IN

Input Low Voltage, V

0.8 V max VDD = 5 V

INL

0.4 V max VDD = 3 V
Input High Voltage, V

2.0 V min VDD = 3 V and 5 V

INH

SCLK Only (Schmitt-Triggered Input) VDD = 5 V nominal

VT+ 1.4/3 V min/V max
VT− 0.8/1.4 V min/V max
VT+ − VT− 0.4/0.8 V min/V max

SCLK Only (Schmitt-Triggered Input) VDD = 3 V nominal

VT+ 1/2 V min/V max
VT− 0.4/1.1 V min/V max
VT+ − VT− 0.375/0.8 V min/V max

MCLK IN Only VDD = 5 V nominal

Input Low Voltage, V
Input High Voltage, V

0.8 V max

INL

3.5 V min

INH

MCLK IN Only VDD = 3 V nominal

Input Low Voltage, V
Input High Voltage, V

0.4 V max

INL

2.5 V min

INH

LOGIC OUTPUTS (Including MCLK OUT)

Output Low Voltage, VOL 0.4 V max I
Output Low Voltage, V

0.4 V max I

OL

Output High Voltage, VOH 4 V min I
Output High Voltage, V

V

OH

− 0.6 V min I

DD

Floating State Leakage Current ±10 μA max
Floating State Output Capacitance14 9 pF typ

Data Output Coding Binary Unipolar mode
Offset binary Bipolar mode
SYSTEM CALIBRATION

Positive Full-Scale Limit15 (1.05 × V

Negative Full-Scale Limit15 −(1.05 × V

Offset Limit15 −(1.05 × V

Input Span16 (0.8 × V
(2.1 × V

/64 For gains of 1 to 4

CLKIN

/8 For gains of 8 to 128

= 2.7 V to 3.3 V

V

DD

= 1.225 ± 1% for specified performance

V

REF

= 4.75 V to 5.25 V

V

DD

V

= 2.5 ± 1% for specified performance

REF

/64

= 800 μA, except for MCLK OUT;13 VDD = 5 V

SINK

= 100 μA, except for MCLK OUT;13 VDD = 3 V

SINK

= 200 μA, except for MCLK OUT;13 VDD = 5 V

SOURCE

= 100 μA, except for MCLK OUT;13 VDD = 3 V

SOURCE

)/gain V max Gain is the selected PGA gain (1 to 128)

REF

)/gain V max Gain is the selected PGA gain (1 to 128)

REF

)/gain V max Gain is the selected PGA gain (1 to 128)

REF

)/gain V min Gain is the selected PGA gain (1 to 128)

REF

)/gain V max Gain is the selected PGA gain (1 to 128)

REF

Rev. C | Page 6 of 44

AD7705/AD7706

Parameter B Version1 Unit Conditions/Comments

POWER REQUIREMENTS

VDD Voltage 2.7 to 3.3 V min to V max For specified performance

Power Supply Currents17 Digital I/Ps = 0 V or VDD, external MCLK IN and CLKDIS = 1

0.32 mA max BUF bit = 0, f

0.6 mA max BUF bit = 1, f

0.4 mA max BUF bit = 0, f

0.6 mA max BUF bit = 0, f

0.7 mA max BUF bit = 1, f

1.1 mA max BUF bit = 1, f
VDD Voltage 4.75 to 5.25 V min to V max For specified performance

Power Supply Currents

17

Digital I/Ps = 0 V or VDD, external MCLK IN and CLKDIS = 1

0.45 mA max BUF bit = 0, f

0.7 mA max BUF bit = 1, f

0.6 mA max BUF bit = 0, f

0.85 mA max BUF bit = 0, f

0.9 mA max BUF bit = 1, f

1.3 mA max BUF bit = 1, f
Standby (Power-Down) Current18 16 μA max External MCLK IN = 0 V or VDD, VDD = 5 V, see Figure 12
8 μA max External MCLK IN = 0 V or VDD, VDD = 3 V
Power Supply Rejection

1

Temperature range is −40°C to +85°C.

2

These numbers are established from characterization or design data at initial product release.

3

A calibration is effectively a conversion; therefore, these errors are of the order of the conversion noise shown in Table 5 and Table 7. This applies after calibration at

the temperature of interest.

4

Recalibration at any temperature removes these drift errors.

5

Positive full-scale error includes zero-scale errors (unipolar offset error or bipolar zero error) and applies to both unipolar and bipolar input ranges.

6

Full-scale drift includes zero-scale drift (unipolar offset drift or bipolar zero drift) and applies to both unipolar and bipolar input ranges.

7

Gain error does not include zero-scale errors. It is calculated as (full-scale error – unipolar offset error) for unipolar ranges and (full-scale error - bipolar zero error) for

bipolar ranges.

8

Gain drift does not include unipolar offset drift or bipolar zero drift. It is effectively the drift of the part if only zero-scale calibrations are performed.

9

This common-mode voltage range is allowed, provided that the input voltage on analog inputs is not more positive than VDD + 30 mV or more negative than

GND − 100 mV. Parts are functional with voltages down to GND − 200 mV, but with increased leakage at high temperatures.

10

The AD7705/AD7706 can tolerate absolute analog input voltages down to GND − 200 mV, but the leakage current increases.

11

The analog input voltage range on AIN(+) is given with respect to the voltage on AIN(−) on the AD7705, and with respect to the voltage of the COMMON input on the

AD7706. The absolute voltage on the analog inputs should not be more positive than VDD + 30 mV, or more negative than GND − 100 mV for specified performance.
Input voltages of GND − 200 mV can be accommodated, but with increased leakage at high temperatures.

12

V

= REFIN(+) − REFIN(−).

REF

13

These logic output levels apply to the MCLK OUT only when it is loaded with one CMOS load.

14

Sample tested at 25°C to ensure compliance.

15

After calibration, if the analog input exceeds positive full scale, the converter outputs all 1s. If the analog input is less than negative full scale, the device outputs all 0s.

16

These calibration and span limits apply, provided that the absolute voltage on the analog inputs does not exceed VDD + 30 mV or go more negative than

GND − 100 mV. The offset calibration limit applies to both the unipolar zero point and the bipolar zero point.

17

When using a crystal or ceramic resonator across the MCLK pins as the clock source for the device, the VDD current and power dissipation varies depending on the

crystal or resonator type (see Clocking and Oscillator Circuit section).

18

If the external master clock continues to run in standby mode, the standby current increases to 150 μA typical at 5 V and 75 μA at 3 V. When using a crystal or ceramic

resonator across the MCLK pins as the clock source for the device, the internal oscillator continues to run in standby mode, and the power dissipation depends on the
crystal or resonator type (see Standby Mode section).

19

Measured at dc and applies in the selected pass band. PSRR at 50 Hz exceeds 120 dB, with filter notches of 25 Hz or 50 Hz. PSRR at 60 Hz exceeds 120 dB, with filter

notches of 20 Hz or 60 Hz.

20

PSRR depends on both gain and VDD, as follows:

Gain 1 2 4 8 to 128

VDD = 3 V 86 78 85 93
VDD = 5 V 90 78 84 91

19, 20

dB typ

= 1 MHz, gains of 1 to 128

CLKIN

= 1 MHz, gains of 1 to 128

CLKIN

= 2.4576 MHz, gains of 1 to 4

CLKIN

= 2.4576 MHz, gains of 8 to 128

CLKIN

= 2.4576 MHz, gains of 1 to 4

CLKIN

= 2.4576 MHz, gains of 8 to 128

CLKIN

= 1 MHz, gains of 1 to 128

CLKIN

= 1 MHz, gains of 1 to 128

CLKIN

= 2.4576 MHz, gains of 1 to 4

CLKIN

= 2.4576 MHz, gains of 8 to 128

CLKIN

= 2.4576 MHz, gains of 1 to 4

CLKIN

= 2.4576 MHz, gains of 8 to 128

CLKIN

Rev. C | Page 7 of 44

AD7705/AD7706

TIMING CHARACTERISTICS

VDD = 2.7 V to 5.25 V; GND = 0 V; f

Table 2. Timing Characteristics

Limit at T

Parameter

3, 4

f

400 kHz min Master clock frequency (crystal oscillator or externally supplied)

CLKIN

(B Version)

2.5 MHz max For specified performance
t

0.4 × t

CLKIN LO

t

0.4 × t

CLKIN HI

t1 500 × t

CLKIN

CLKIN

CLKIN

t2 100 ns min
Read Operation

t3 0 ns min

t4 120 ns min

5

t

0 ns min SCLK falling edge to data valid delay

5

80 ns max VDD = 5 V

100 ns max VDD = 3.0 V

t6 100 ns min SCLK high pulse width

t7 100 ns min SCLK low pulse width

t8 0 ns min

6

t

10 ns min Bus relinquish time after SCLK rising edge

9

60 ns max VDD = 5 V

100 ns max VDD = 3.0 V

t10 100 ns max
Write Operation

t11 120 ns min

t12 30 ns min Data valid to SCLK rising edge setup time

t13 20 ns min Data valid to SCLK rising edge hold time

t14 100 ns min SCLK high pulse width

t15 100 ns min SCLK low pulse width

t16 0 ns min

1

Sample tested at 25°C to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.

2

See Figure 19 and Figure 20.

3

The f

duty cycle range is 45% to 55%. f

CLKIN

higher current than specified, and possibly become uncalibrated.

4

The AD7705/AD7706 are production tested with f

5

These numbers are measured with the load circuit of Figure 2 and defined as the time required for the output to cross the VOL or VOH limits.

6

These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then

extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.

7

DRDY

returns high upon completion of the first read from the device after an output update. The same data can be reread while

taken that subsequent reads do not occur close to the next output update.

= 2.4576 MHz; Input Logic 0 = 0 V, Logic 1 = VDD, unless otherwise noted.

CLKIN

1, 2

, T

MIN

MAX

ns min Master clock input low time, t

Unit Conditions/Comments

CLKIN

= 1/f

CLKIN

ns min Master clock input high time

ns nom

must be supplied whenever the AD7705/AD7706 are not in standby mode. If no clock is present, the devices can draw

CLKIN

at 2.4576 MHz (1 MHz for some IDD tests). They are guaranteed by characterization to operate at 400 kHz.

CLKIN

high time

DRDY

pulse width

RESET

to CS setup time

DRDY

falling edge to SCLK rising edge setup time

CS

rising edge to SCLK rising edge hold time

CS

SCLK falling edge to DRDY

falling edge to SCLK rising edge setup time

CS

rising edge to SCLK rising edge hold time

CS

high7

DRDY

is high, but care should be

I

(800μA AT VDD = 5V

SINK

TO OUTPUT

PIN

50pF

100μA AT V

I

(200μA AT VDD = 5V

SOURCE

100mA AT V

1.6V

DD

= 3V)

DD

= 3V)

01166-002

Figure 2. Load Circuit for Access Time and Bus Relinquish Time

Rev. C | Page 8 of 44

AD7705/AD7706

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameters Ratings

VDD to GND −0.3 V to +7 V
Analog Input Voltage to GND −0.3 V to VDD + 0.3 V
Reference Input Voltage to GND −0.3 V to VDD + 0.3 V
Digital Input Voltage to GND −0.3 V to VDD + 0.3 V
Digital Output Voltage to GND −0.3 V to VDD + 0.3 V
Operating Temperature Range

Commercial (B Version) −40°C to + 85°C
Storage Temperature Range −65°C to + 150°C
Junction Temperature 150°C
PDIP Package, Power Dissipation 450 mW

θJA Thermal Impedance 105°C/W

Lead Temperature (Soldering, 10 sec) 260°C
SOIC Package, Power Dissipation 450 mW

θJA Thermal Impedance 75°C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C

SSOP Package, Power Dissipation 450 mW

θJA Thermal Impedance 139°C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C

ESD Rating >4000 V

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. C | Page 9 of 44

AD7705/AD7706

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

SCLK

1

CS

RESET

2
3

AD7705

4

TOP VIEW

(Not to Scale)

5
6
7
8

MCLK IN

MCLK OUT

AIN2(+)
AIN1(+)
AIN1(–)

Figure 3. AD7705 Pin Configuration

GND

16
15

V
DIN

14
13

DOUT
DRDY

12

AIN2(–)

11
10

REF IN(–)

9

REF IN(+)

DD

01166-003

1

SCLK

CS

RESET

AIN1
AIN2

2

3

TOP VIEW

4

(Not to Scale)

5

6

7

8

AD7706

MCLK IN

MCLK OUT

COMMON REF IN(+)

Figure 4. AD7706 Pin Configuration

16

15

14

13

12

11

10

9

GND
V

DD

DIN
DOUT
DRDY
AIN3
REF IN(–)

01166-004

Table 4. Pin Function Descriptions

Mnemonic
Pin No. AD7705 AD7706 Description

1 SCLK SCLK

Serial Clock. An external serial clock is applied to the Schmitt-triggered logic input to access serial
data from the AD7705/AD7706. This serial clock can be a continuous clock with all data transmitted in
a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the information
transmitted to the AD7705/AD7706 in smaller batches of data.

2 MCLK IN MCLK IN

Master Clock Signal. This can be provided in the form of a crystal/resonator or external clock. A
crystal/resonator can be tied across the Pin MCLK IN and Pin MCLK OUT. Alternatively, the MCLK IN
pin can be driven with a CMOS-compatible clock with the MCLK OUT pin left unconnected. The parts
can be operated with clock frequencies in the range of 500 kHz to 5 MHz.

3 MCLK OUT MCLK OUT

When the master clock for these devices is a crystal/resonator, the crystal/resonator is connected
between Pin MCLK IN and Pin MCLK OUT. If an external clock is applied to Pin MCLK IN, Pin MCLK OUT
provides an inverted clock signal. This clock can be used to provide a clock source for external
circuitry and is capable of driving 1 CMOS load. If the user does not require this clock externally, Pin
MCLK OUT can be turned off via the CLKDIS bit of the clock register. This ensures that the part does
not unnecessarily burn power driving capacitive loads on Pin MCLK OUT.

4

CS Chip Select. Active low logic input used to select the AD7705/AD7706. With this input hardwired low,

CS

the AD7705/AD7706 can operate in its 3-wire interface mode with Pin SCLK, Pin DIN, and Pin DOUT
used to interface to the device. The CS

pin can be used to select the device communicating with the

AD7705/AD7706.

5

RESET Logic Input. Active low input that resets the control logic, interface logic, calibration coefficients,

RESET

digital filter, and analog modulator of the parts to power-on status.
6 AIN2(+) AIN1 Positive Input of the Differential Analog Input Pair AIN2(+)/AIN2(−) for AD7705. Channel 1 for AD7706.
7 AIN1(+) AIN2 Positive Input of the Differential Analog Input Pair AIN1(+)/AIN1(−) for AD7705. Channel 2 for AD7706.
8 AIN1(−) COMMON

Negative Input of the Differential Analog Input Pair AIN1(+)/AIN1(−) for AD7705. COMMON input for

AD7706 with Channel 1, Channel 2, and Channel 3 referenced to this input.
9 REF IN(+) REF IN(+)

Reference Input. Positive input of the differential reference input to the AD7705/AD7706. The reference

input is differential with the provision that REF IN(+) must be greater than REF IN(−).

and GND.

DD

and GND, provided that REF IN(+) is greater than REF IN(−).

DD

10 REF IN(−) REF IN(−)

REF IN(+) can lie anywhere between V

Reference Input. Negative input of the differential reference input to the AD7705/AD7706. The

REF IN(−) can lie anywhere between V
11 AIN2(−) AIN3 Negative Input of the Differential Analog Input Pair AIN2(+)/AIN2(−) for AD7705. Channel 3 for AD7706.
12

DRDY Logic Output. A logic low on this output indicates that a new output word is available from the

DRDY

AD7705/AD7706 data register. The DRDY

pin returns high upon completion of a read operation of a
full output word. If no data read has taken place between output updates, the DRDY
for 500 × t

cycles prior to the next output update. While DRDY is high, a read operation should

CLK IN

line returns high

neither be attempted nor in progress to avoid reading from the data register as it is being updated.
The DRDY

line returns low after the update has taken place. DRDY is also used to indicate when the

AD7705/AD7706 has completed its on-chip calibration sequence.

13 DOUT DOUT

Serial Data Output. Serial data is read from the output shift register on the part. The output shift
register can contain information from the setup register, communication register, clock register, or
data register, depending on the register selection bits of the communication register.

Rev. C | Page 10 of 44

AD7705/AD7706

Mnemonic
Pin No. AD7705 AD7706 Description

14 DIN DIN

15 VDD V
16 GND GND Ground Reference Point for the AD7705/AD7706 Internal Circuitry.

Supply Voltage. 2.7 V to 5.25 V operation.

DD

Serial Data Input. Serial data is written to the input shift register on the part. Data from the input shift
register is transferred to the setup register, clock register, or communication register, depending on
the register selection bits of the communication register.

Rev. C | Page 11 of 44

AD7705/AD7706

OUTPUT NOISE (5 V OPERATION)

Table 5 shows the AD7705/AD7706 output rms noise for the
selectable notch and −3 dB frequencies for the parts, as selected
by FS0 and FS1 of the clock register. The numbers given are for
the bipolar input ranges with a V

of 2.5 V and VDD = 5 V.

REF

These numbers are typical and are generated at an analog input
voltage of 0 V with the parts used in either buffered or unbuffered
mode.

Table 6 shows the output peak-to-peak noise for the

selectable notch and −3 dB frequencies for the parts.

Table 5. Output RMS Noise vs. Gain and Output Update Rate @ 5 V

Notch and
O/P Data Rate

MCLK IN = 2.4576 MHz
50 Hz 13.1 Hz 4.1 2.1 1.2 0.75 0.7 0.66 0.63 0.6
60 Hz 15.72 Hz 5.1 2.5 1.4 0.8 0.75 0.7 0.67 0.62
250 Hz 65.5 Hz 110 49 31 17 8 3.6 2.3 1.7
500 Hz 131 Hz 550 285 145 70 41 22 9.1 4.7
MCLK IN = 1 MHz
20 Hz 5.24 Hz 4.1 2.1 1.2 0.75 0.7 0.66 0.63 0.6
25 Hz 6.55 Hz 5.1 2.5 1.4 0.8 0.75 0.7 0.67 0.62
100 Hz 26.2 Hz 110 49 31 17 8 3.6 2.3 1.7
200 Hz 52.4 Hz 550 285 145 70 41 22 9.1 4.7

−3 dB
Frequency

Gain of 1 Gain of 2 Gain of 4 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128

Note that these numbers represent the resolution for which
there is no code flicker. They are not calculated based on rms
noise, but on peak-to-peak noise. The numbers given are for
bipolar input ranges with a V

of 2.5 V for either buffered or

REF

unbuffered mode. These numbers are typical and are rounded
to the nearest LSB. The numbers apply for the CLKDIV bit of
the clock register set to 0.

Typical Output RMS Noise in μV Filter First

Table 6. Peak-to-Peak Resolution vs. Gain and Output Update Rate @ 5 V

Notch and
O/P Data Rate

MCLK IN = 2.4576 MHz
50 Hz 13.1 Hz 16 16 16 16 16 16 15 14
60 Hz 15.72 Hz 16 16 16 16 15 14 14 13
250 Hz 65.5 Hz 13 13 13 13 13 13 12 12
500 Hz 131 Hz 10 10 10 10 10 10 10 10
MCLK IN = 1 MHz
20 Hz 5.24 Hz 16 16 16 16 16 16 15 14
25 Hz 6.55 Hz 16 16 16 16 15 14 14 13
100 Hz 26.2 Hz 13 13 13 13 13 13 12 12
200 Hz 52.4 Hz 10 10 10 10 10 10 10 10

−3 dB
Frequency

Gain of 1 Gain of 2 Gain of 4 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128

Typical Peak-to-Peak Resolution Bits Filter First

Rev. C | Page 12 of 44

AD7705/AD7706

OUTPUT NOISE (3 V OPERATION)

Table 7 shows the AD7705/AD7706 output rms noise for the
selectable notch and −3 dB frequencies for the parts, as selected
by FS0 and FS1 of the clock register. The numbers given are for
the bipolar input ranges with a V

of 1.225 V and a VDD = 3 V.

REF

These numbers are typical and are generated at an analog input
voltage of 0 V with the parts used in either buffered or unbuffered
mode.

Table 8 shows the output peak-to-peak noise for the

selectable notch and −3 dB frequencies for the parts.

Table 7. Output RMS Noise vs. Gain and Output Update Rate @ 3 V

Notch and
O/P Data Rate

MCLK IN = 2.4576 MHz
50 Hz 13.1 Hz 3.8 2.4 1.5 1.3 1.1 1.0 0.9 0.9
60 Hz 15.72 Hz 5.1 2.9 1.7 1.5 1.2 1.0 0.9 0.9
250 Hz 65.5 Hz 50 25 14 9.9 5.1 2.6 2.3 2.0
500 Hz 131 Hz 270 135 65 41 22 9.7 5.1 3.3
MCLK IN = 1 MHz
20 Hz 5.24 Hz 3.8 2.4 1.5 1.3 1.1 1.0 0.9 0.9
25 Hz 6.55 Hz 5.1 2.9 1.7 1.5 1.2 1.0 0.9 0.9
100 Hz 26.2 Hz 50 25 14 9.9 5.1 2.6 2.3 2.0
200 Hz 52.4 Hz 270 135 65 41 22 9.7 5.1 3.3

−3 dB
Frequency

Gain of 1 Gain of 2 Gain of 4 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128

Note that these numbers represent the resolution for which
there is no code flicker. They are not calculated based on rms
noise, but on peak-to-peak noise. The numbers given are for
bipolar input ranges with a V

of 1.225 V for either buffered or

REF

unbuffered mode. These numbers are typical and are rounded
to the nearest LSB. The numbers apply for the CLKDIV bit of
the clock register set to 0.

Typical Output RMS Noise in μV Filter First

Table 8. Peak-to-Peak Resolution vs. Gain and Output Update Rate @ 3 V

Filter First
Notch and
O/P Data Rate

MCLK IN = 2.4576 MHz
50 Hz 13.1 Hz 16 16 15 15 14 13 13 12
60 Hz 15.72 Hz 16 16 15 14 14 13 13 12
250 Hz 65.5 Hz 13 13 13 13 12 12 11 11
500 Hz 131 Hz 10 10 10 10 10 10 10 10
MCLK IN = 1 MHz
20 Hz 5.24 Hz 16 16 15 15 14 13 13 12
25 Hz 6.55 Hz 16 16 15 14 14 13 13 12
100 Hz 26.2 Hz 13 13 13 13 12 12 11 11
200 Hz 52.4 Hz 10 10 10 10 10 10 10 10

Typical Peak-to-Peak Resolution in Bits

−3 dB
Frequency Gain of 1 Gain of 2 Gain of 4 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128

Rev. C | Page 13 of 44

AD7705/AD7706

TYPICAL PERFORMANCE CHARACTERISTICS

32771

32770

32769

32768

VDD = 5V
V

= 2.5V

REF

GAIN = +128
50Hz UPDATE RATE

TA = 25°C
RMS NOISE = 600nV

400

300

32767

CODE READ

32766

32765

32764

32763

0 100

200 300 400 500 600 700 800 900 1000

READING NUMBER

Figure 5. Noise @ Gain = +128 With 50 Hz Update Rate

1.2
VDD = 3V

T

= 25°C

(mA)

DD

I

mA)

(

DD

I

1.0

0.8

0.6

0.4

0.2

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

0.4

0

1

A

BUFFERED MODE, GAIN = +1

UNBUFFERED MODE, GAIN = +1

0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6

Figure 6. I

BUFFERED MODE
f

= 5MHz,

CLK

CLKDIV = 1
UNBUFFERED MODE

f

= 1MHz,

CLK

CLKDIV = 0

= 3V

V

DD

EXTERNAL MCLK
CLKDIS = 1
T

= 25°C

A

2 4 8 16 32 64 128

Figure 7. I

BUFFERED MODE, GAIN = +128

UNBUFFERED MODE, GAIN = +128

FREQUENCY (MHz)

vs. MCLK IN Frequency @ 3 V

DD

BUFFERED MODE
f

= 2.4576MHz, CLKDIV = 0

CLK

UNBUFFERED MODE

= 5MHz, CLKDIV = 1

f

CLK

UNBUFFERED MODE
f

= 2.84MHz, CLKDIV = 0

CLK

BUFFERED MODE
f

= 1MHz, CLKDIV = 0

CLK

GAIN

vs. Gain and Clock Frequency @ 3 V

DD

01166-005

01166-006

01166-007

200

OCCURRENCE

100

0

32764

Figure 8. Histogram of Data in

1.2
VDD = 5V

= +25°C

T

A

1.0

0.8

BUFFERED MODE, GAIN = +1

0.6

(mA)

DD

I

0.4

0.2

UNBUFFERED MODE, GAIN = +1

0

0.4

0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6

Figure 9. I

1.2

BUFFERED MODE

= 5MHz,

f

CLK

CLKDIV = 1

1.0

UNBUFFERED MODE

= 1MHz,

f

CLK

CLKDIV = 0

0.8

0.6

(mA)

DD

I

0.4

VDD = 5V

0.2

EXTERNAL MCLK
CLKDIS = 1

= 25°C

T

A

0

1

Figure 10. I

32765 32766 32767 32768 32769 32770

CODE

Figure 5

BUFFERED MODE, GAIN = +128

UNBUFFERED MODE, GAIN = +128

FREQUENCY (MHz)

vs. MCLK IN Frequency @ 5 V

DD

BUFFERED MODE
f

= 2.4576MHz, CLKDIV = 0

CLK

UNBUFFERED MODE
f

= 5MHz, CLKDIV = 1

CLK

UNBUFFERED MODE
f

= 2.4576MHz, CLKDIV = 0

CLK

BUFFERED MODE
f

= 1MHz, CLKDIV = 0

CLK

2 4 8 16 32 64 128

vs. Gain and Clock Frequency @ 5 V

DD

GAIN

01166-008

01166-009

01166-010

Rev. C | Page 14 of 44