Analog Devices AD7703BN, AD7703AR, AD7703AQ, AD7703AN, AD7703SQ Datasheet

LC2MOS

5

DGND

AV

DD

DV

DD

AVSSDVSSSC1 SC2

14

15

7 64

17

AGND

A

IN

V

REF

10

8

13

CALIBRATION

SRAM

CALIBRATION

MICROCONTROLLER

CAL

BP/UP

SLEEP

20

19

CLOCK

GENERATOR

SERIAL INTERFACE

LOGIC

SDATA

SCLK

3 2 1 16 18

CLKIN CLKOUT

MODE

CS

DRDY

AD7703

9

ANALOG

MODULATOR

12

11

6-POLE GAUSSIAN

LOW-PASS

DIGITAL FILTER

20-BIT CHARGE BALANCE A/D

CONVERTER

a

FEATURES
Monolithic 20-Bit ADC

0.0003% Linearity Error
20-Bit No Missed Codes
On-Chip Self-Calibration Circuitry
Programmable Low-Pass Filter

0.1 Hz to 10 Hz Corner Frequency
0 to +2.5 V or +2.5 V Analog Input Range
4 kSPS Output Data Rate
Flexible Serial Interface
Ultralow Power

APPLICATIONS
Industrial Process Control
Weigh Scales
Portable Instrumentation
Remote Data Acquisition

GENERAL DESCRIPTION

The AD7703 is a 20-bit ADC which uses a sigma delta conver­sion technique. The analog input is continuously sampled by an
analog modulator whose mean output duty cycle is proportional
to the input signal. The modulator output is processed by an
on-chip digital filter with a six-pole Gaussian response, which
updates the output data register with 20-bit binary words at
word rates up to 4 kHz. The sampling rate, filter corner fre­quency and output word rate are set by a master clock input
that may be supplied externally, or by an on-chip gate oscillator.

The inherent linearity of the ADC is excellent, and endpoint
accuracy is ensured by self-calibration of zero and full scale
which may be initiated at any time. The self-calibration scheme
can also be extended to null system offset and gain errors in the
input channel.

The output data is accessed through a serial port, which has two
synchronous modes suitable for interfacing to shift registers or
the serial ports of industry standard microcontrollers.

CMOS construction ensures low power dissipation, and a power
down mode reduces the idle power consumption to only 10 mW.

20-Bit A/D Converter

AD7703

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

1. The AD7703 offers 20-bit resolution coupled with
outstanding 0.0003% accuracy.

2. No missing codes ensures true, usable, 20-bit dynamic range,
removing the need for programmable gain and level-setting
circuitry.

3. The effects of temperature drift are eliminated by on-chip
self-calibration, which removes zero and gain error. External
circuits can also be included in the calibration loop to remove
system offsets and gain errors.

4. A flexible synchronization allows the AD7703 to interface
directly to the serial ports of industry standard
microcontrollers and DSP processors.

5. Low operating power consumption and an ultralow power
standby mode make the AD7703 ideal for loop powered
remote sensing applications, or battery-powered portable
instruments.

REV. D

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] Fax: [phone]

© Analog Devices, Inc., 1996

AD7703–SPECIFICA TIONS

(TA = +258C; AVDD = DVDD = +5 V; AVSS = DVSS = –5 V; V

= +2.5 V; f

REF

CLKIN

BP/UP = +5 V; MODE = +5 V; AIN Source Resistance = 1 kV1 with 1 nF to AGND at AIN unless otherwise noted.)

Parameter A/S Versions

2

B Version

STATIC PERFORMANCE

Resolution 20 20 20 Bits
Integral Nonlinearity, T

+25°C ±0.003 ±0.0015 ±0.0008 % FSR max
T

to T

MIN

Differential Nonlinearity, T

MAX

Positive Full-Scale Error
Full-Scale Drift

4

Unipolar Offset Error
Unipolar Offset Drift
Bipolar Zero Error
Bipolar Zero Drift

MIN

to T

±0.0015 ±0.0007 ±0.0003 % FSR typ

MAX

±0.003 ±0.0015 ±0.0012 % FSR max

to T

MIN

3

±0.5 ±0.5 ± 0.5 LSB typ Guaranteed No Missing Codes

MAX

±4 ±4 ±4 LSB typ
±16 ±16 ±16 LSB max

3

4

3

4

± 19/±37 ± 19 ±19 LSB typ
±4 ±4 ±4 LSB typ
±16 ±16 ±16 LSB max
±26 ±26 ±26 LSB typ Temp Range: 0°C to +70°C
±67 +48/–400 ±67 ±67 LSB typ Specified Temp Range
±4 ±4 ±4 LSB typ
±16 ±16 ±16 LSB max
±13 ±13 ±13 LSB typ Temp Range: 0°C to +70°C
±34 +24/–200 ±34 ±34 LSB typ Specified Temp Range

Bipolar Negative Full-Scale Errors3±8 ±8 ±8 LSB typ

±32 ±32 ±32 LSB max
Bipolar Negative Full-Scale Drift4±10/± 20 ± 10 ±10 LSB typ
Noise (Referred to Output) 1.6 1.6 1.6 LSB rms typ

DYNAMIC PERFORMANCE

Sampling Frequency, f
Output Update Rate, f
Filter Corner Frequency, f
Settling Time to ±0.0007% FS 507904/f

S

OUT

–3 dB

f

/256 f

CLKIN

f

/1024 f

CLKIN

f

/409,600 f

CLKIN

CLKIN

CLKIN
CLKIN
CLKIN

507904/f

SYSTEM CALIBRATION

Positive Full-Scale Calibration Range V
Positive Full-Scale Overrange V

Negative Full-Scale Overrange –(V
Maximum Offset Calibration Ranges

Unipolar Input Range –(V
Bipolar Input Range –0.4 V

Input Span

7

+ 0.1 V

REF

+ 0.1 V

REF

REF

5, 6

REF

0.8 V

REF

2 V

REF

+ 0.1) –(V
+ 0.1) –(V

to +0.4 V

REF

REF

–0.4 V

0.8 V

+ 0.2 2 V

ANALOG INPUT

Unipolar Input Range 0 to +2.5 0 to +2.5 0 to +2.5 Volts
Bipolar Input Range ±2.5 ±2.5 ± 2.5 Volts
Input Capacitance 20 20 20 pF typ
Input Bias Current

1

1 1 1 nA typ

LOGIC INPUTS

All Inputs except CLKIN

V

, Input Low Voltage 0.8 0.8 0.8 V max

INL

V

, Input High Voltage 2.0 2.0 2.0 V min

INH

CLKIN

V

, Input Low Voltage 0.8 0.8 0.8 V max

INL

V

, Input High Voltage 3.5 3.5 3.5 V min

INH

IIN, Input Current 10 10 10 µA max

LOGIC OUTPUTS

VOL, Output Low Voltage 0.4 0.4 0.4 V max I
VOH, Output High Voltage DVDD –1 DVDD –1 DVDD –1 V min I
Floating State Leakage Current ±10 ±10 ±10 µA max
Floating State Output Capacitance 9 9 9 pF typ

POWER REQUIREMENTS

Power Supply Voltages

Analog Positive Supply (AVDD) 4.5/5.5 4.5/5.5 4.5/5.5 V min/V max For Specified Performance
Digital Positive Supply (DVDD) 4.5/AV
Analog Negative Supply (AVSS) –4.5/–5.5 –4.5/–5.5 –4.5/–5.5 V min/V max

DD

4.5/AV

Digital Negative Supply (DVSS) –4.5/–5.5 –4.5/–5.5 –4.5/–5.5 V min/V max
Calibration Memory Retention
Power Supply Voltage 2.0 2.0 2.0 V min

2

/256 f
/1024 f
/409,600 f

CLKIN

+ 0.1 V

REF

+ 0.1 V

REF

+ 0.1) –(V

REF

+ 0.1) –(V

REF

to +0.4 V

REF

REF

+ 0.2 2 V

REF

DD

REF

C Version

CLKIN
CLKIN
CLKIN

507904/f

–0.4 V

0.8 V

4.5/AV

2

Units Test Conditions/Comments

/256 Hz
/1024 Hz
/409,600 Hz

CLKIN

+ 0.1 V max System Calibration Applies to

REF

+ 0.1 V max Unipolar and Bipolar Ranges.

REF

+ 0.1) V max After Calibration, if A

REF

+ 0.1) V max If AIN < 0 (Unipolar) or –V

REF

to +0.4 V

REF

REF

+ 0.2 V max

REF

DD

sec For Full-Scale Input Step

the Device Will Output All 1s.

V max (Bipolar), the Device Will

REF

V min Output all 0s

= 1.6 mA

SINK

= 100 µA

SOURCE

V min/V max

= 4.096 MHz;

> V

IN

REF

REF

,

–2–

REV. D

WARNING!

ESD SENSITIVE DEVICE

AD7703

Parameter A/S Versions2B Version

STATIC PERFORMANCE

DC Power Supply Currents

Analog Positive Supply (AIDD) 2.7 2.7 2.7 mA max Typically 1.8 mA
Digital Positive Supply (DIDD) 2 2 2 mA max Typically 1.3 mA
Analog Negative Supply (AISS) 2.7 2.7 2.7 mA max Typically 1.8 mA
Digital Negative Supply (DISS) 0.1 0.1 0.1 mA max Typically 0.03 mA

Power Supply Rejection

Positive Supplies 70 70 70 dB typ

Negative Supplies 75 75 75 dB typ
Power Dissipation
Normal Operation 38 38 38 mW rnax SLEEP = Logic 1,

Standby Operations

A, B, C 20 20 20 µW max Typically 10 µW

S404040µW max

NOTES

1

The AIN pin presents a very high impedance dynamic load which varies with clock frequency. A ceramic 1 nF capacitor from the A

resistance should be 750 Ω or less.

2

Temperature Ranges are as follows: A, B, C Versions: –40°C to +85 °C; S Version: –55 °C to +125 °C.

3

Applies after calibration at the temperature of interest. Full-Scale Error applies for both unipolar and bipolar input ranges.

4

Total drift over the specified temperature range after calibration at power-up at +25°C. This is guaranteed by design and/or characterization. Recalibration at any

temperature will remove these errors.

5

In unipolar mode the offset can have a negative value (–V

6

The specifications for input overrange and for input span apply additional constraints on the offset calibration range.

7

For unipolar mode, input span is the difference between full scale and zero scale. For bipolar mode, input span is the difference between positive and negative

full-scale points. When using less than the maximum input span, the span range may be placed anywhere within the range of ±(V

8

All digital outputs unloaded. All digital inputs at 5 V CMOS levels.

9

Applies in 0.1 Hz to 10 Hz bandwidth. PSRR at 60 Hz will exceed 120 dB due to the digital filter.

10

CLKIN is stopped. All digital inputs are grounded.

Specifications subject to change without notice.

8

9

10

) such that the unipolar mode can mimic bipolar mode operation.

REF

2

C Version

2

Units Test Conditions/Comments

Typically 25 mW
SLEEP = Logic 0,

to AGND is necessary. Source

IN

+ 0.1).

REF

ABSOLUTE MAXIMUM RATINGS*

(TA = +25°C unless otherwise noted)

DVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V

DV

to AVDD . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +0.3 V

DD

DV

to AGND . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –6 V

SS

AV

to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V

DD

AV

to AGND . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –6 V

SS

AGND to DGND . . . . . . . . . . . . . . . . . . . . .–0.3 V to +0.3 V

Digital Input Voltage to DGND . . . . –0.3 V to DV

Analog Input Voltage to AGND . . . . . . . . . . .AV

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AV

Input Current to Any Pin Except Supplies

1

. . . . . . . . ±10 mA

+ 0.3 V

DD

– 0.3 V to

SS

+ 0.3 V

DD

Operating Temperature Range

Industrial (A, B, C Versions) . . . . . . . . . . . –40°C to +85°C

Extended (S Version) . . . . . . . . . . . . . . . . –55°C to +125°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300°C

Power Dissipation (DIP Package) to +75°C . . . . . . . 450 mW

Derates above +75°C by . . . . . . . . . . . . . . . . . . . . 10 mW/°C

Power Dissipation (SOIC Package) to +75°C . . . . . . 250 mW

Derates above +75°C by . . . . . . . . . . . . . . . . . . . . 15 mW/°C

NOTES
*Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

1

Transient currents of up to 100 mA will not cause SCR latch-up.

ORDERING GUIDE

Linearity

Temperature Error Package

Model Range (% FSR) Options*

AD7703AN –40°C to +85°C 0.003 N-20
AD7703BN –40°C to +85°C 0.0015 N-20
AD7703CN –40°C to +85°C 0.0012 N-20
AD7703AR –40°C to +85°C 0.003 R-20
AD7703BR –40°C to +85°C 0.0015 R-20
AD7703CR –40°C to +85°C 0.0012 R-20
AD7703AQ –40°C to +85°C 0.003 Q-20
AD7703BQ –40°C to +85°C 0.0015 Q-20
AD7703CQ –40°C to +85°C 0.0012 Q-20
AD7703SQ –55°C to +125°C 0.003 Q-20

NOTES
*N = Plastic DIP; R = SOIC; Q = Cerdip.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although this device features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

REV. D

–3–

AD7703

CAL

SC1, SC2

SC1,SC2 VALID

t

1

t

2

CLKIN

SLEEP

t

3

(AVDD = DVDD = +5 V 6 10%; AVSS = DVSS = –5 V 6 10%; AGND = DGND = 0 V; f

MAX

1, 2

4.096 MHz; Input Levels: Logic 0 = 0 V, Logic 1 = DVDD; unless otherwise noted.)

Limit at T

MIN

, T

MAX

TIMING CHARACTERISTICS

Limit at T

MIN

, T

Parameter (A, B, C Versions) (S Version) Units Conditions/Comment

3, 4

f

CLKIN

200 200 kHz min Master Clock Frequency: Internal Gate Oscillator

6

CLKIN

=

5 5 MHz max Typically 4096 kHz
200 200 kHz min Master Clock Frequency: Externally Supplied

5

t

r

5

t

f

t

1

t

2

6

t

3

SSC MODE

7

t

4

t

5

t

6

t

7

t

8

t

9

8, 9

t

10

5 5 MHz max
50 50 ns max Digital Output Rise Time. Typically 20 ns
50 50 ns max Digital Output Fall Time. Typically 20 ns
0 0 ns min SC1, SC2 to CAL High Setup Time
50 50 ns min SC1, SC2 Hold Time After CAL Goes High
1000 1000 ns min SLEEP High to CLKIN High Setup Time

3/f

CLKIN

3/f

CLKIN

ns max Data Access Time (CS Low to Data Valid)
100 100 ns max SCLK Falling Edge to Data Valid Delay (25 ns typ)
250 250 ns min MSB Data Setup Time. Typically 380 ns
300 300 ns max SCLK High Pulse Width. Typically 240 ns
790 790 ns max SCLK Low Pulse Width. Typically 730 ns
l/f

+ 200 l/f

CLKIN

4/f

+ 200 4/f

CLKIN

+ 200 ns max SCLK Rising Edge to Hi-Z Delay (1/f

CLKIN

+ 200 ns max CS High to Hi-Z Delay

CLKIN

+ 100 ns typ)

CLKIN

SEC MODE

f

SCLK

t

11

t

12

7, 10

t

13

11

t

14

8

t

15

8

t

16

NOTES

1

Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.

2

See Figures 1 to 6.

3

CLKIN duty cycle range is 20% to 80%. CLKIN must be supplied whenever the AD7703 is not in SLEEP mode. If no clock is present in this case, the device can

draw higher current than specified and possibly become uncalibrated.

4

The AD7703 is production tested with f

5

Specified using 10% and 90% points on waveform of interest.

6

In order to synchronize several AD7703s together using the SLEEP pin, this specification must be met.

7

t4 and t13 are measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.

8

t9, t10, t15 and t16 are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is
then extrapolated back to remove the effects of charging or discharging the 100 pF capacitor. This means that the tune quoted in the Timing Characteristics is the
true bus relinquish time of the part and as such is independent of external bus loading capacitances.

9

If CS is returned high before all 20 bits are output, the SDATA and SCLK outputs will complete the current data bit and then go to high impedance.

10

If CS is activated asynchronously to DRDY, CS will not be recognized if it occurs when DRDY is high for four clock cycles. The propagation delay time may be as
great as 4 CLKIN cycles plus 160 ns. To guarantee proper clocking of SDATA when using asynchronous CS, the SCLK input should not be taken high sooner than
4 CLKIN cycles plus 160 ns after CS goes low.

11

SDATA is clocked out on the falling edge of the SCLK input.

5 5 MHz max Serial Clock Input Frequency
35 35 ns min SCLK High Pulse Width
160 160 ns min SCLK Low Pulse Width
160 160 ns max Data Access Time (CS Low to Data Valid). Typically 80 ns
150 150 ns max SCLK Falling Edge to Data Valid Delay. Typically 75 ns
250 250 ns max CS High to Hi-Z Delay
200 200 ns max SCLK Falling Edge to Hi-Z Delay. Typically 100 ns

at 4.096 MHz. It is guaranteed by characterization to operate at 200 kHz.

CLKIN

I

OL

1.6mA

OUTPUT

PIN

TO

C

L

100pF

I

OH

200µA

+2.1V

Figure 1. Load Circuit for Access Time and Bus Relinquish
Time

–4–

Figure 2. Calibration Control Timing

Figure 3. Sleep Mode Timing

REV. D

AD7703

HI-Z

DB19

DB18

DB1 DB0

HI-Z

SCLK

SDATA

CLKIN

CS

HI-Z

t

7

t

8

t

5

t

9

t

4

t

8

HI-Z

CS

t

10

SDATA

DATA

VALID

HI-Z

Figure 4. SSC Mode Data Hold Time

DRDY

CS

t

12

t

11

SCLK

t

SDATA

HI-Z

13

DB19

DB18

t

14

DB1

DB0

t

16

HI-Z

Figure 5b. SEC Mode Timing Diagram

TERMINOLOGY

LINEARITY ERROR

This is the maximum deviation of any code from a straight line
passing through the endpoints of the transfer function. The end­points of the transfer function are zero-scale (not to be confused
with bipolar zero), a point 0.5 LSB below the first code transi­tion (000 . . . 000 to 000 . . . 001) and full scale, a point 1.5 LSB
above the last code transition (111 . . . 110 to 111 . . . 111).
The error is expressed as a percentage of full scale.

DIFFERENTIAL LINEARITY ERROR

This is the difference between any code’s actual width and the
ideal (1 LSB) width. Differential linearity error is expressed in
LSBs. A differential linearity specification of ± 1 LSB or less
guarantees monotonicity.

POSITIVE FULL-SCALE ERROR

Positive full-scale error is the deviation of the last code transition
(111 . . . 110 to 111 . . . 111) from the ideal (V

–3/2 LSBs).

REF

It applies to both positive and negative analog input ranges.

UNIPOLAR OFFSET ERROR

Unipolar offset error is the deviation of the first code transition
from the ideal (AGND + 0.5 LSB) when operating in the uni­polar mode.

BIPOLAR ZERO ERROR

This is the deviation of the midscale transition (0111 . . . 111 to
1000 . . . 000) from the ideal (AGND – 0.5 LSB) when operat­ing in the bipolar mode.

CS

t

15

SDATA

DATA
VALID

HI-Z

Figure 5a. SEC Mode Data Hold Time

Figure 6. SSC Mode Timing Diagram

POSITIVE FULL-SCALE OVERRANGE

Positive full-scale overrange is the amount of overhead available
to handle input voltages greater than +V

(for example, noise

REF

peaks or excess voltages due to system gain errors in system cali­bration routines) without introducing errors due to overloading
the analog modulator or overflowing the digital filter.

NEGATIVE FULL-SCALE OVERRANGE

This is the amount of overhead available to handle voltages be­low –V

without overloading the analog modulator or over-

REF

flowing the digital filter. Note that the analog input will accept
negative voltage peaks even in the unipolar mode.

OFFSET CALIBRATION RANGE

In the system calibration modes (SC2 Low) the AD7703 cali­brates its offset with respect to the A

pin. The offset calibra-

IN

tion range specification defines the range of voltages that the
AD7701 can accept and still calibrate offset accurately.

FULL-SCALE CALIBRATION RANGE

This is the range of voltages that the AD7703 can accept in the
system calibration mode and still calibrate full scale correctly.

INPUT SPAN

In system calibration schemes, two voltages applied in sequence
to the AD7703’s analog input define the analog input range.
The input span specification defines the minimum and maxi­mum input voltages from zero to full scale that the AD7703 can
accept and still calibrate gain accurately.

BIPOLAR NEGATIVE FULL-SCALE ERROR

This is the deviation of the first code transition from the ideal
(–V

+ 0.5 LSB), when operating in the bipolar mode.

REF

REV. D

–5–