Analog Devices AD7701TQ, AD7701BR, AD7701BN, AD7701ARS, AD7701AR Datasheet

LC2MOS

5

DGND

AV

DDDVDDAVSSDVSS

SC1 SC2

14

15

7 64

17

AGND

A

IN

V

REF

9

10

8

13

CALIBRATION

SRAM

CALIBRATION

MICROCONTROLLER

16-BIT A/D CONVERTER

ANALOG

MODULATOR

CAL

BP/UP

SLEEP

12

11

20

19

CLOCK

GENERATOR

SERIAL INTERFACE

LOGIC

SDATA

SCLK

3 2 1 16 18

CLKIN CLKOUT MODE CS

DRDY

6-POLE GAUSSIAN

LOW-PASS

DIGITAL FILTER

AD7701

a

FEATURES
Monolithic 16-Bit ADC

0.0015% Linearity Error
On-Chip Self-Calibration Circuitry
Programmable Low-Pass Filter

0.1 Hz to 10 Hz Corner Frequency
0 V to +2.5 V or 62.5 V Analog Input Range
4 kSPS Output Data Rate
Flexible Serial Interface
Ultralow Power

APPLICATIONS
Industrial Process Control
Weigh Scales
Portable Instrumentation
Remote Data Acquisition

GENERAL DESCRIPTION

The AD7701 is a 16-bit ADC which uses a sigma-delta conver­sion technique. The analog input is continuously sampled by an
analog modulator whose mean output duty cycle is proportional
to the input signal. The modulator output is processed by an
on-chip digital filter with a six-pole Gaussian response, which
updates the output data register with 16-bit binary words at
word rates up to 4 kHz. The sampling rate, filter corner fre­quency and output word rate are set by a master clock input
that may be supplied externally, or by a crystal-controlled on­chip clock oscillator.

The inherent linearity of the ADC is excellent, and endpoint
accuracy is ensured by self-calibration of zero and full scale
which may be initiated at any time. The self-calibration scheme
can also be extended to null system offset and gain errors in the
input channel.

The output data is accessed through a flexible serial port, which
has an asynchronous mode compatible with UARTs and two
synchronous modes suitable for interfacing to shift registers or
the serial ports of industry-standard microcontrollers.

CMOS construction insures low power dissipation, and a power
down mode reduces the idle power consumption to only 10 µW.

16-Bit A/D Converter

AD7701

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

1. The AD7701 offers 16-bit resolution coupled with outstand­ing 0.0015% accuracy.

2. No missing codes ensures true, usable, 16-bit dynamic range,
removing the need for programmable gain and level-setting
circuitry.

3. The effects of temperature drift are eliminated by on-chip
self-calibration, which removes zero and gain error. External
circuits can also be included in the calibration loop to
remove system offsets and gain errors.

4. A flexible synchronous/asynchronous interface allows the
AD7701 to interface directly to UARTs or to the serial ports
of industry-standard microcontrollers.

5. Low operating power consumption and an ultralow power
standby mode make the AD7701 ideal for loop-powered
remote sensing applications, or battery-powered portable
instruments.

REV. D

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

© Analog Devices, Inc., 1996

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] Fax: [phone]

(TA = +258C; AVDD = DVDD = +5 V; AVSS = DVSS = –5 V; V

4.096 MHz; Bipolar Mode: MODE = +5 V; AIN Source Resistance = 1k V1 with 1 nF to

AD7701–SPECIFICA TIONS

Parameter A, S Versions

STATIC PERFORMANCE

Resolution 16 16 Bits
Integral Nonlinearity

to T

T

MIN

MAX

Differential Nonlinearity

to T

T

MIN

MAX

Positive Full-Scale Error

Full-Scale Drift

4

Unipolar Offset Error

Unipolar Offset Drift
Bipolar Zero Error

Bipolar Zero Drift

3

3

4

3

4

Bipolar Negative Full-Scale Error

Bipolar Negative Full-Scale Drift
Noise (Referred to Output) 0.1 0.1 LSB rms typ

±0.003 ±0.0015 % FSR max

±0.125 ±0.125 LSB typ Guaranteed No Missing Codes
±0.5 ±0.5 LSB max
±0.13 ±0.13 LSB typ
±0.5 ±0.5 LSB max
±1.2 (±2.3 S Version) ±1.2 (±2.3 T Version) LSB typ
±0.25 ±0.25 LSB typ
±1 ±1 LSB max
±1.6 (+3/–25 S Version) ±1.6 (+3/–25 T Version) LSB typ
±0.25 ±0.25 LSB typ
±1 ± 1 LSB max
±0.8 (+1.5/–12.5 S Version) ±0.8 (+1.5/–12.5 T Version) LSB typ

3

±0.5 ±0.5 LSB typ
±2 ±2 LSB max

4

±0.6 (±1.2 S Version) ±0.6 (±1.2 T Version) LSB typ

AGND at AIN, unless otherwise noted.)

2

B, T Versions

±0.0007 % FSR typ

2

Units Test Conditions/Comments

= +2.5 V; f

REF

CLKIN

=

DYNAMIC PERFORMANCE

f

Sampling Frequency, f
Output Update Rate, f

S
OUT

Filter Corner Frequency, f

–3 dB

/256 f

CLKIN

f

/1024 f

CLKIN

f

/409,600 f

CLKIN

Settling Time to ±0.0007% FS 507904/f

CLKIN

/256 Hz

CLKIN

/1024 Hz

CLKIN

/409,600 Hz

CLKIN

507904/f

CLKIN

sec For Full-Scale Input Step

SYSTEM CALIBRATION Applies to Unipolar and

Positive Full-Scale Overrange V
Positive Full-Scale Overrange V
Negative Full-Scale Overrange –(V
Maximum Offset Calibration Range

REF
REF

5, 6

Unipolar Input Range –(V
Bipolar Input Range –0.4 V

Input Span

7

0.8 V
2 V

+ 0.1 V
+ 0.1 V

+ 0.1) –(V

REF

+ 0.1) –(V

REF

to +0.4 V

REF

REF

+ 0.2 2 V

REF

REF

+ 0.1 V max Bipolar Ranges. After Cali-

REF

+ 0.1 V max bration, If AIN > V

REF

+ 0.1) V max Device Will Output All 1s

REF

If AIN < 0 (Unipolar) or

+ 0.1) V max –V

REF

–0.4 V

0.8 V

to +0.4 V

REF

REF

+ 0.2 V max

REF

REF

V max Will Output All 0s.
V min

(Bipolar), the Device

REF

REF

, the

ANALOG INPUT

Unipolar Input Range 0 to +2.5 0 to +2.5 Volts
Bipolar Input Range ±2.5 ±2.5 Volts
Input Capacitance 10 10 pF typ
Input Bias Current

1

1 1 nA typ

LOGIC INPUTS

All Inputs Except CLKIN

, Input Low Voltage 0.8 0.8 V max

V

INL

, Input High Voltage 2.0 2.0 V min

V

INH

CLKIN

, Input Low Voltage 0.8 0.8 V max

V

INL

, Input High Voltage 3.5 3.5 V min

V

INH

IIN, Input Current 10 10 µA max

LOGIC OUTPUTS

, Output Low Voltage 0.4 0.4 V max I

V

OL

, Output High Voltage DVDD – 1 DVDD – 1 V min I

V

OH

Floating State Leakage Current ±10 ±10 µA max
Floating State Output Capacitance 9 9 pF typ

–2–

= 1.6 mA

SINK
SOURCE

= 100 µA

REV. D

AD7701

Parameter A, S Versions

POWER REQUIREMENTS

8

2

B, T Versions

2

Units Test Conditions/Comments

Power Supply Voltages

Analog Positive Supply (AV
Digital Positive Supply (DV
Analog Negative Supply (AV
Digital Negative Supply (DV

) 4.5/5.5 4.5/5.5 V min/V max

DD

) 4.5/AV

DD

) –4.5/–5.5 –4.5/–5.5 V min/V max

SS

) –4.5/–5.5 –4.5/–5.5 V min/V max

SS

DD

4.5/AV

DD

V min/V max

Calibration Memory Retention
Power Supply Voltage 2.0 2.0 V min

DC Power Supply Currents

8

Analog Positive Supply (AIDD) 2.7 2.7 mA max Typically 1.8 mA
Digital Positive Supply (DI
Analog Negative Supply (AI
Digital Negative Supply (DI

Power Supply Rejection

) 2 2 mA max Typically 1.3 mA

DD

) 2.7 2.7 mA max Typically 1.8 mA

SS

) 0.1 0.1 mA max Typically 0.03 mA

SS

9

Positive Supplies 70 70 dB typ
Negative Supplies 75 75 dB typ

Power Dissipation

Normal Operation 38 38 mW max

Standby Operation

10

20 (40 S Version) 20 (40 T Version) µW max SLEEP = Logic 0,

SLEEP = Logic 1,
Typically 25 mW

Typically 10 µW

NOTES

11

The AIN pin presents a very high impedance dynamic load which varies with clock frequency.

12

Temperature ranges are as follows: A, B Versions; –40°C to +85 °C; S, T Versions; –55° C to +125 °C.

13

Apply after calibration at the temperature of interest. Full-scale error applies for both unipolar and bipolar input ranges.

14

Total drift over the specified temperature range since calibration at power-up at +25 ° C. This is guaranteed by design and/or characterization. Recalibration at any

temperature will remove these errors.

15

In unipolar mode the offset can have a negative value (–V

16

The specifications for input overrange and for input span apply additional constraints on the offset calibration range.

17

For unipolar mode, input span is the difference between full scale and zero scale. For bipolar mode, input span is the difference between positive and negative

full-scale points. When using less than the maximum input span, the span range may be placed anywhere within the range of ±(V

18

All digital outputs unloaded. All digital inputs at 5 V CMOS levels.

19

Applies in 0.1 Hz to 10 Hz bandwidth. PSRR at 60 Hz will exceed 120 dB due to the digital filter.

10

CLKIN is stopped. All digital inputs are grounded.

Specifications subject to change without notice.

) such that the unipolar mode can mimic bipolar mode operation.

REF

REF

+0.1)

ABSOLUTE MAXIMUM RATINGS

(TA = +25°C unless otherwise noted)

DVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V

DV

to AVDD . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

DD

DV

to AGND . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –6 V

SS

AV

to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V

DD

AV

to AGND . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –6 V

SS

AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

Digital Input Voltage to DGND . . . . –0.3 V to DV

Analog Input

Voltage to AGND . . . . . . . . AV

Input Current to Any Pin Except Supplies

1

+0.3 V

DD

– 0.3 V to AVDD + 0.3 V

SS

2

. . . . . . . . ±10 mA

Industrial Cerdip (A, B Versions) . . . . . . . –40°C to +85°C

Extended Cerdip (S, T Versions) . . . . . . –55°C to +125°C

Storage Temperature Range . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300°C

Power Dissipation (Any Package) to +75°C . . . . . . . 450 mW

Derates above +75°C by . . . . . . . . . . . . . . . . . . . . 10 mW/°C

NOTES

1

Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

2

Transient currents of up to 100 mA will not cause SCR latch-up.

Operating Temperature Range

Commercial Plastic (A, B Versions) . . . . . –40°C to +85°C

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although this device features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

REV. D

–3–

AD7701

PIN FUNCTION DESCRIPTION

Pin Mnemonic Description

1 MODE Selects the Serial Interface Mode. If MODE is tied to –5 V, the AD7701 will operate in the asynchronous

communications (ac) mode. The SCLK pin is configured as an input, and data is transmitted in two bytes,
each with one start bit and two stop bits. If MODE is tied to DGND, the synchronous external clocking
(SEC) mode is selected. SCLK is configured as an input, and the output appears without formatting, the
MSB coming first. If MODE is tied to +5 V, the AD7701 operates in the synchronous self-clocking (SSC)
mode. SCLK is configured as an output, with a clock frequency of f

2 CLKOUT Clock Output to generate an Internal Master Clock by connecting a crystal between CLKOUT and CLKIN.

If an external clock is used, CLKOUT is not connected.
3 CLKIN Clock Input for External Clock.
4, 17 SC1, SC2 System Calibration Pins. The state of these pins, when CAL is taken high, determines the type of calibration

performed.
5 DGND Digital Ground. Ground reference for all digital signals.
6DV
7AV

SS

SS

Digital Negative Supply, –5 V nominal.

Analog Negative Supply, –5 V nominal.
8 AGND Analog Ground. Ground reference for all analog signals.
9A
10 V

IN
REF

Analog Input.

Voltage Reference Input, +2.5 V nominal. This determines the value of positive full-scale in the unipolar

mode and of both positive and negative full-scale in the bipolar mode.
11

SLEEP Sleep mode pin. When this pin is taken low, the AD7701 goes into a low-power mode with typically 10µW

power consumption.
12 BP/

UP Bipolar/Unipolar Mode Pin. When this pin is low, the AD7701 is configured for a unipolar input range going

from AGND to V

. When Pin 12 is high, the AD7701 is configured for a bipolar input range, ±V

REF

13 CAL Calibration Mode Pin. When CAL is taken high for more than 4 cycles, the AD7701 is reset and performs a

calibration cycle when CAL is brought low again. The CAL pin can also be used as a strobe to synchronize

the operation of several AD7701s.
14 AV
15 DV
16

CS Chip Select Input. When CS is brought low, the AD7701 will begin to transmit serial data in a format deter-

DD

DD

Analog Positive Supply, +5 V nominal.

Digital Positive Supply, +5 V nominal.

mined by the state of the MODE pin.
18

DRDY Data Ready output. DRDY is low when valid data is available in the output register. It goes high after transmission

of a word is completed. It also goes high for four clock cycles when a new data word is being loaded into the out-

put register, to indicate that valid data is not available, irrespective of whether data transmission is complete or not.
19 SCLK Serial Clock Input/Output. The SCLK pin in configured as an input or output, dependent on the type of se-

rial data transmission that has been selected by the MODE pin. When configured as an output in the syn-

chronous self-clocking mode, it has a frequency of f

/4 and a duty cycle of 25%.

CLKIN

20 SDATA Serial Data Output. The AD7701’s output data is available at this pin as a 16-bit serial word. The transmis-

sion format is determined by the state of the MODE pin.

/4 and 25% duty-cycle.

CLKlN

REF

.

PIN CONFIGURATIONS

DIP, Cerdip, SOIC

AD7701

TOP VIEW

20
19
18
17
16
15
14
13
12
11

SDATA
SCLK
DRDY
SC2
CS
DV

DD

AV

DD

CAL
BP/UP
SLEEP

MODE

CLKOUT

CLKIN

SC1

DGND

DV
AV

AGND

A

V

REF

SS
SS

IN

1
2
3
4
5
6

(Not to Scale)
7
8
9

10

MODE

CLKOUT

CLKIN

SC1

DGND

DV

AV

AGND

V

SSOP

1
2
3
4
5
6

NC

AD7701

7

NC

TOP VIEW

8

SS

(Not to Scale)

9

NC

10

SS

11

NC

12

A

13

IN

14

REF

NC = NO CONNECT

28
27
26
25
24
23
22
21
20
19
18
17
16
15

SDATA
SCLK
DRDY
SC2
CS
NC
NC
NC
DV

DD

AV

DD

NC
CAL
BP/UP
SLEEP

ORDERING GUIDE

Temperature Linearity Package

Model Range Error (% FSR) Options*

AD7701AN –40°C to +85°C 0.003 N-20
AD7701BN –40°C to +85°C 0.0015 N-20
AD7701AR –40°C to +85°C 0.003 R-20
AD7701BR –40°C to +85°C 0.0015 R-20
AD7701ARS –40°C to +85°C 0.003 RS-28
AD7701AQ –40°C to +85°C 0.003 Q-20
AD7701BQ –40°C to +85°C 0.0015 Q-20
AD7701SQ –55°C to +125°C 0.003 Q-20
AD7701TQ –55°C to +125°C 0.0015 Q-20

NOTES
*N = Plastic DIP; Q = Cerdip; R = SOIC; RS = SSOP.

–4–

REV. D

AD7701

(AVDD = DVDD = +5 V 6 10%; AVSS = DVSS = –5 V 6 10%; AGND = DGND = O V;

1, 2

f

TIMING CHARACTERISTICS

Limit at T

Parameter (A, B Versions) (S, T Versions) Units Conditions/Comments

3, 4

f

CLKIN

200 200 kHz min Master Clock Frequency: Internal Gate Oscillator
5 5 MHz max Typically 4.096 MHz
200 200 kHz min Master Clock Frequency: Externally Supplied

5

t

r

5

t

f

t

1

t

2

6

t

3

SSC Mode

7

t

4

t

5

t

6

t

7

t

8

8

t

9

8, 9

t

10

5 5 MHz max
50 50 ns max Digital Output Rise Time. Typically 20 ns
50 50 ns max Digital Output Fall Time. Typically 20 ns
0 0 ns min SC1, SC2 to CAL High Setup Time
50 50 ns min SC1, SC2 Hold Time After CAL Goes High
1000 1000 ns min SLEEP High to CLKIN High Setup Time

3/f

CLKIN

100 100 ns max SCLK Falling Edge to Data Valid Delay (25 ns typ)
250 250 ns min MSB Data Setup Time. Typically 380 ns
300 300 ns max SCLK High Pulse Width. Typically 240 ns
790 790 ns max SCLK Low Pulse Width. Typically 730 ns
l/f

CLKIN

(4/f

CLKIN

SEC Mode
f

SCLK

t

11

t

12

t

13

t

14

t

15

t

16

7, 10
11
8
8

5 5 MHz Serial Clock Input Frequency
35 35 ns min SCLK Input High Pulse Width
160 160 ns min SCLK Low Pulse Width
160 160 ns max Data Access Time (CS Low to Data Valid). Typically 80 ns
150 150 ns max SCLK Falling Edge to Data Valid Delay. Typically 75 ns
250 250 ns max CS High to Hi-Z Delay
200 200 ns max SCLK Falling Edge to Hi-Z Delay. Typically 100 ns

AC Mode
t

17

t

18

t

19

NOTES

11

Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.

12

See Figures 1 to 6.

13

CLKIN Duty Cycle range is 20% to 80%. CLKIN must be supplied whenever the AD7701 is not in SLEEP mode. If no clock is present in this case, the device can

draw higher current than specified and possibly become uncalibrated.

14

The AD7701 is production tested with f

15

Specified using 10% and 90% points on waveform of interest.

16

In order to synchronize several AD7701s together using the SLEEP pin, this specification is met.

17

t4 and t13 are measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.

18

t9, t10, t15 and t16 are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is

then extrapolated back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time quoted in the Timing Characteristics is the
true bus relinquish time of the part and as such as independent of external bus loading capacitance.

19

If CS is returned high before all 16 bits are output, the SDATA and SCLK outputs will complete the current data bit and then go to high impedance.

10

If CS is activated asynchronously to DRDY, CS will not be recognized if it occurs when DRDY is high for four clock cycles. The propagation delay time may be as

great as 4 CLKIN cycles plus 160 ns. To guarantee proper clocking of SDATA when using asynchronous CS, the SCLK input should not be taken high sooner than
4 CLKIN cycles plus 160 ns after CS goes low.

11

SDATA is clocked out on the falling edge of the SCLK input.

40 40 ns min CS Setup Time. Typically 20 ns
180 180 ns max Data Delay Time. Typically 90 ns
200 200 ns max SCLK Falling Edge to Hi-Z Delay. Typically 100 ns

MIN

, T

MAX

Limit at T

3/f

+200 l/f

) +200 (4/f

at 4.096 MHz. It is guaranteed by characterization to operate at 200 kHz.

CLKIN

= 4.096 MHz; Input Levels: Logic O = O V, Logic 1 = DVDD)

CLKIN

, T

MIN

MAX

CLKIN

+200 ns max SCLK Rising Edge to Hi-Z Delay (l/f

CLKIN

) +200 ns max CS High to Hi-Z Delay

CLKIN

ns max Data Access Time (CS Low to Data Valid)

+ 100 ns typ)

CLKIN

–5–REV. D