16-bit resolution with no missing codes
Throughput: 250 kSPS @ 5 V
INL: ±4 LSB max
S/(N + D): 92 dB @ 20 kHz
THD: –106 dB @ 20 kHz
Pseudo-differential analog input range:
0 V to V
with V
REF
No pipeline delay
Single-supply operation: 2.7 V or 5 V
Serial interface SPI®/QSPI™/MICROWIRE™/DSP-compatible
Supply Current: 540 µA @ 2.7 V/100 kSPS,
The AD7694 is a 16-bit, charge redistribution, successive
approximation, PulSAR™ analog-to-digital converter (ADC)
that operates from a single power supply, VDD, between 2.7 V
to 5.25 V. It contains a low power, high speed, 16-bit sampling
ADC with no missing codes (B grade), an internal conversion
clock, and a serial, SPI-compatible interface port. The part also
contains a low noise, wide bandwidth, short aperture delay
track-and-hold circuit. On the CNV rising edge, it samples an
analog input, IN+, between 0 V to REF with respect to a ground
sense, IN−. The reference voltage, REF, is applied externally and
can be set up to the supply voltage.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Anal og Devices. Trademarks and
registered trademarks are the property of their respective owners.
Its power scales linearly with throughput.
The AD7694 is housed in an 8-lead MSOP package with an
operating temperature specified from −40°C to +85°C.
A Grade B Grade
Parameter Conditions Min Typ Max Min Typ Max Unit
RESOLUTION 16 16 Bits
ANALOG INPUT
Voltage Range IN+ − IN− 0 V
Absolute Input Voltage IN+ −0.1 VDD + 0.1 −0.1 VDD + 0.1 V
IN− −0.1 0.1 −0.1 0.1 V
Leakage Current at 25°C Acquisition phase 1 1 nA
Input Impedance See the Analog Input section.
ACCURACY
No Missing Codes 15 16 Bits
Integral Linearity Error −6 +6 −4 +4 LSB
Transition Noise REF = VDD = 5 V 0.5 0.5 LSB
Gain Error1, T
MIN
to T
Gain Error Temperature Drift ±0.3 ±0.3 ppm/°C
Offset Error1, T
MIN
to T
Offset Temperature Drift ±0.3 ±0.3 ppm/°C
Power Supply Sensitivity
THROUGHPUT
Conversion Rate VDD = 4.75 V to 5.25 V 0 250 0 250 kSPS
VDD = 2.7 V to 4.75 V 0 150 0 150 kSPS
AC ACCURACY
Signal-to-Noise fIN = 20 kHz, V
f
Spurious-Free Dynamic Range fIN = 20 kHz −100 −106 dB
Total Harmonic Distortion fIN = 20 kHz −100 −106 dB
Signal-to-(Noise + Distortion) fIN = 20 kHz, V
f
= VDD; TA = –40°C to +85°C, unless otherwise noted.
REF
MAX
MAX
±2 ±30 ±2 ±15 LSB
±0.7 ±3.5 ±0.7 ±3.5 mV
VDD = 5 V ±5%
= 5 V 90 88 92 dB
REF
= 20 kHz, V
IN
= 20 kHz, V
IN
= 2.5 V 86 87 dB
REF
= 5 V 89 88 92 dB
REF
= 2.5 V 86 87 dB
REF
REF
0 V
REF
V
±0.05 ±0.05 LSB
2
1
See section. These specifications do include full temperature range variation, but do not include the error contribution from the external reference. Terminology
2
All specifications in dB refer to a full-scale input, FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
Rev. 0 | Page 3 of 16
AD7694
VDD = 2.7 V to 5.25 V; V
Table 3.
Parameter Conditions Min Typ Max Unit
REFERENCE
Voltage Range 1 VDD V
Load Current 250 kSPS, V
SAMPLING DYNAMICS
−3 dB Input Bandwidth 9 MHz
DIGITAL INPUTS
Logic Levels
V
IL
VDD = 2.7 V 0.45 V
V
IH
VDD = 3.3 V 1.9 V
I
IL
I
IH
DIGITAL OUTPUTS
Data Format Serial, 16 bits straight binary
Pipeline Delay
V
OL
V
OH
POWER SUPPLIES
VDD Specified performance 2.7 5.25 V
Operating Current
VDD VDD = 5 V, 100 kSPS throughput 0.8 1.2 mA
VDD = 2.7 V, 100 kSPS throughput 540 960 µA
Standby Current
1, 2
TEMPERATURE RANGE
Specified Performance T
= VDD; TA = –40°C to +85°C, unless otherwise noted.
REF
− V
= V
IN+
IN−
/2 = 2.5 V 50 µA
REF
VDD = 4.75 V 0.8 V
VDD = 5.25 V 3.15 V
−1 +1 µA
−1 +1 µA
I
= +500 µA 0.4 V
SINK
I
= −500 µA VDD − 0.3 V
SOURCE
VDD = 5 V, 25°C
to T
MIN
MAX
Conversion results available immediately
after completed conversion
1 50 nA
−40 +85
°C
1
With all digital inputs forced to VDD or GND, as required.
2
During acquisition phase.
Rev. 0 | Page 4 of 16
AD7694
TIMING SPECIFICATIONS
VDD = 4.75 V to 5.25 V; TA = −40°C to +85°C, unless otherwise stated.
Table 4.
Parameter Symbol Min Typ Max Unit
Conversion Time: CNV Rising Edge to Data Available t
Time between Conversions t
SCK Period t
SCK Low Time t
SCK High Time t
SCK Falling Edge to Data Remains Valid t
SCK Falling Edge to Data Valid Delay t
CNV Low to SDO, D15 MSB Valid t
CNV High to SDO High Impedance t
Conversion Time: CNV Rising Edge to Data Available t
Time between Conversions t
SCK Period t
SCK Low Time t
SCK High Time t
SCK Falling Edge to Data Remains Valid t
SCK Falling Edge to Data Valid Delay t
CNV Low to SDO, D15 MSB Valid t
CNV High to SDO High Impedance t