ANALOG DEVICES AD7693 Service Manual

16-Bit, ±0.5 LSB, 500 kSPS PulSAR®

V

FEATURES

16-bit resolution with no missing codes
Throughput: 500 kSPS
INL/DNL: ±0.25 LSB typ, ±0.5 LSB max (±8 ppm of FSR)
Dynamic range: 96.5 dB
SINAD: 96 dB @ 1 kHz
THD: −120 dB @ 1 kHz
True differential analog input range: ±V

0 V to V

with V

REF

up to VDD on both inputs

REF

No pipeline delay
Single-supply 5 V operation with

1.8 V/2.5 V/3 V/5 V logic interface
Serial interface SPI®/QSPI™/MICROWIRE™/DSP compatible
Daisy-chain multiple ADCs, selectable busy indicator
Power dissipation: 40 nJ/conversion

40 μW @ 5 V/1 kSPS
4 mW @ 5 V/100 kSPS

18 mW @ 5 V/500 kSPS
Standby current: 1 nA
10-lead package: MSOP (MSOP-8 size) and

3 mm × 3 mm QFN (LFCSP) (SOT-23 size)
Pin-for-pin compatible with the 16-bit AD7687 and AD7688

and the 18-bit AD7690 and AD7691

APPLICATIONS

Battery-powered equipment
Data acquisitions
Seismic data acquisition systems
DVMs
Instrumentation
Medical instruments

1.0

0.8

0.6

0.4

0.2

0

INL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

0 65536

16384 32768 49152

Figure 1. Integral Nonlinearity vs. Code

POSITIVE INL = +0.17LSB
NEGATIVE INL = –0. 17LSB

CODE

REF

Differential ADC in MSOP/QFN

AD7693

APPLICATION DIAGRAM

+2.5V TO +5V

±10V, ±5V, ...

ADA4941-1

Table 1. MSOP, QFN (LFCSP)/SOT-23
14-/16-/18-Bit PulSAR ADC

100

Type

kSPS

18-Bit AD7691 AD7690

16-Bit True

AD7684 AD7687 AD7688

Differential
16-Bit Pseudo AD7683 AD7685 AD7686 ADA4841-x
Differential/

AD7680 AD7694

Unipolar
14-Bit AD7940 AD7942 AD7946 ADA4841-x

GENERAL DESCRIPTION

The AD7693 is a 16-bit, successive approximation analog-to­digital converter (ADC) that operates from a single power supply,
VDD. It contains a low power, high speed, 16-bit sampling ADC
with no missing codes, an internal conversion clock, and a
versatile serial interface port. The reference voltage, V
applied externally and can be set up to the supply voltage, VDD.
On the CNV rising edge, it samples the voltage difference
between the IN+ and IN− pins. The voltages on these pins
swing in opposite phase between 0 V and V

Its power scales linearly with throughput.
Using the SDI input, the SPI-compatible serial interface also

features the ability to daisy-chain several ADCs on a single
3-wire bus and provides an optional busy indicator. It is compatible
with 1.8 V, 2.5 V, 3 V, or 5 V logic, using the separate VIO supply.

The AD7693 is housed in a 10-lead MSOP or a 10-lead QFN
(LFCSP) with operation specified from −40°C to +85°C.

06394-001

REF

IN+

AD7693

IN–

GND

Figure 2.

250
kSPS

+5

VDD

VIO

SDI

SCK

SDO

CNV

+1.8V TO VDD

3- OR 4-WIRE
INTERFACE
(SPI, DAISY CHAIN, CS)

400 kSPS
to
500 kSPS

AD7693

about V

REF

ADC
Driver

ADA4941-1
ADA4841-x

ADA4941-1
ADA4841-x

, is

REF

/2.

REF

6394-002

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006–2011 Analog Devices, Inc. All rights reserved.

AD7693

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

Application Diagram........................................................................ 1

General Description......................................................................... 1

Revision History ...............................................................................2

Specifications..................................................................................... 3

Timing Specifications....................................................................... 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configurations and Function Descriptions........................... 7

Terminology...................................................................................... 8

Typical Performance Characteristics............................................. 9

Theory of Operation ......................................................................12

Circuit Information.................................................................... 12

Converter Operation.................................................................. 12

Typical Connection Diagram ...................................................13

Analog Inputs..............................................................................14

Driver Amplifier Choice ........................................................... 14

Single-Ended-to-Differential Driver ....................................... 15

Voltage Reference Input ............................................................ 15

Power Supply............................................................................... 15

Supplying the ADC from the Reference.................................. 16

Digital Interface.......................................................................... 16

CS

Mode, 3-Wire Without Busy Indicator ............................. 17

CS

Mode, 3-Wire with Busy Indicator.................................... 18

CS

Mode, 4-Wire Without Busy Indicator ............................. 19

CS

Mode, 4-Wire with Busy Indicator.................................... 20

Chain Mode Without Busy Indicator...................................... 21

Chain Mode with Busy Indicator............................................. 22

Application Hints ...........................................................................23

Layout .......................................................................................... 23

Evaluating AD7693 Performance............................................. 23

Outline Dimensions....................................................................... 24

Ordering Guide .......................................................................... 24

REVISION HISTORY

6/11—Rev. 0 to Rev. A

Changes to Resolution Parameter and Common-Mode Input

Range Parameter in Table 2............................................................. 3

Changes to Figure 6 and Table 6..................................................... 7

Updated Outline Dimensions....................................................... 24

Changes to Ordering Guide.......................................................... 24

12/06—Revision 0: Initial Version

Rev. A | Page 2 of 24

AD7693

SPECIFICATIONS

VDD = 4.5 V to 5.5 V, VIO = 2.3 V to VDD, V

Table 2.

Parameter Conditions/Comments Min Typ Max Unit

RESOLUTION 16 Bits
ANALOG INPUT

Voltage Range IN+ − (IN−) −V
Absolute Input Voltage IN+, IN− −0.1 V
Common-Mode Input Range IN+, IN− V
Analog Input CMRR fIN = 250 kHz 65 dB
Leakage Current at 25°C Acquisition phase 1 nA
Input Impedance1

THROUGHPUT

Conversion Rate 0 500 kSPS
Transient Response Full-scale step 400 ns

ACCURACY

No Missing Codes 16 Bits
Integral Linearity Error −0.5 ±0.25 +0.5 LSB2
Differential Linearity Error −0.5 ±0.25 +0.5 LSB
Transition Noise REF = VDD = 5 V 0.35 LSB
Gain Error3 −20 ±0.5 +20 LSB
Gain Error Temperature Drift ±0.3 ppm/°C
Zero Error3 −5 ±0.5 +5 LSB
Zero Temperature Drift ±0.3 ppm/°C
Power Supply Sensitivity

AC ACCURACY4

Dynamic Range 96 96.5 dB5
Signal-to-Noise fIN = 1 kHz 95.5 96 dB
f
f
f
Signal-to-(Noise + Distortion) fIN = 1 kHz 95.5 96 dB
f
f
Total Harmonic Distortion fIN = 1 kHz −120 −108 dB
f
f
Spurious-Free Dynamic Range fIN = 1 kHz 120 dB
f
f
Intermodulation Distortion6 115 dB

1

See the Analog Inputs section.

2

LSB means least significant bit. With the ±5 V input range, one LSB is 152.6 μV.

3

See the Terminology section. These specifications include full temperature range variation but not the error contribution from the external reference.

4

With V

= 5 V, unless otherwise noted.

REF

5

All specifications expressed in decibels are referred to a full-scale input FSR and tested with an input signal at 0.5 dB below full scale, unless otherwise specified.

6

f

= 21.4 kHz and f

IN1

= 18.9 kHz, with each tone at −7 dB below full scale.

IN2

= VDD, all specifications T

REF

VDD = 5 V ± 5%

= 10 kHz 95.5 dB

IN

= 100 kHz 93 dB

IN

= 1 kHz, V

IN

= 10 kHz 95.5 dB

IN

= 100 kHz 90 dB

IN

= 10 kHz −113 dB

IN

= 100 kHz −92 dB

IN

= 10 kHz 114 dB

IN

= 100 kHz 93.5 dB

IN

= 2.5 V 93 dB

REF

to T

MIN

+V

REF

/2 – 0.1 V

REF

, unless otherwise noted.

MAX

/2 V

REF

V

REF

+ 0.1 V

REF

/2 + 0.1 V

REF

±1 ppm

Rev. A | Page 3 of 24

AD7693

VDD = 4.5 V to 5.5 V, VIO = 2.3 V to VDD, V

Table 3.

Parameter Conditions/Comments Min Typ Max Unit

REFERENCE

Voltage Range 0.5 VDD + 0.3 V
Load Current 500 kSPS, REF = 5 V 100 μA

SAMPLING DYNAMICS

−3 dB Input Bandwidth 9 MHz
Aperture Delay VDD = 5V 2.5 ns

DIGITAL INPUTS

Logic Levels

VIL −0.3 +0.3 × VIO V
VIH 0.7 × VIO VIO + 0.3 V
IIL −1 +1 μA
IIH −1 +1 μA

DIGITAL OUTPUTS

Data Format

Pipeline Delay1
VOL I
VOH I

POWER SUPPLIES

VDD Specified performance 4. 5 5.5 V
VIO Specified performance 2.3 VDD + 0.3 V
VIO Range 1.8 VDD + 0.3 V
Standby Current

2, 3

VDD and VIO = 5 V, 25°C 1 50 nA
Power Dissipation 100 SPS throughput 5 μW
100 kSPS throughput 4 mW
500 kSPS throughput 18 21.5 mW
Energy per Conversion 40 nJ

TEMPERATURE RANGE4

Specified Performance T

1

Conversion results available immediately after completed conversion.

2

With all digital inputs forced to VIO or GND as required.

3

During acquisition phase.

4

Contact an Analog Devices sales representative for the extended temperature range.

= VDD, all specifications T

REF

Serial 16 bits, twos

MIN

to T

, unless otherwise noted.

MAX

complement

= +500 μA 0.4 V

SINK

= −500 μA VIO − 0.3 V

SOURCE

to T

MIN

−40 +85 °C

MAX

Rev. A | Page 4 of 24

AD7693

TIMING SPECIFICATIONS

VDD = 4.5 V to 5.5 V, VIO = 2.3 V to VDD, V

Table 4.

1

Parameter Symbol Min Typ Max Unit

Conversion Time: CNV Rising Edge to Data Available t
Acquisition Time t
Time Between Conversions t
CNV Pulse Width (CS Mode)

SCK Period (CS Mode)
SCK Period (Chain Mode) t

VIO Above 4.5 V 17 ns
VIO Above 3 V 18 ns
VIO Above 2.7 V 19 ns

VIO Above 2.3 V 20 ns
SCK Low Time t
SCK High Time t
SCK Falling Edge to Data Remains Valid t
SCK Falling Edge to Data Valid Delay t

VIO Above 4.5 V 14 ns

VIO Above 3 V 15 ns

VIO Above 2.7 V 16 ns

VIO Above 2.3 V 17 ns
CNV or SDI Low to SDO D15 MSB Valid (CS Mode)

VIO Above 4.5 V 15 ns

VIO Above 2.7 V 18 ns

VIO Above 2.3 V 22 ns
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
SDI Valid Setup Time from CNV Rising Edge (CS Mode)
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
SCK Valid Setup Time from CNV Rising Edge (Chain Mode) t
SCK Valid Hold Time from CNV Rising Edge (Chain Mode) t
SDI Valid Setup Time from SCK Falling Edge (Chain Mode) t
SDI Valid Hold Time from SCK Falling Edge (Chain Mode) t
SDI High to SDO High (Chain Mode with Busy Indicator) t

VIO Above 4.5 V 15 ns

VIO Above 2.3 V 26 ns

1

See Figure 3 and Figure 4 for load conditions.

= VDD, all specifications T

REF

MIN

t
t

t

t
t
t

to T

CONV

ACQ

CYC

CNVH

SCK

SCK

SCKL

SCKH

HSDO

DSDO

EN

DIS

SSDICNV

HSDICNV

SSCKCNV

HSCKCNV

SSDISCK

HSDISCK

DSDOSDI

, unless otherwise noted.

MAX

0.5 1.6 μs

400 ns

2.0 μs
10 ns

15 ns

7 ns

7 ns

4 ns

25 ns

15 ns

0 ns
5 ns

10 ns

4 ns

4 ns

Rev. A | Page 5 of 24

AD7693

T

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Rating

Analog Inputs

IN+,1 IN−1

GND − 0.3 V to VDD + 0.3 V

or ±130 mA
REF GND − 0.3 V to VDD + 0.3 V
Supply Voltages

VDD, VIO to GND −0.3 V to +7 V

VDD to VIO ±7 V
Digital Inputs to GND −0.3 V to VIO + 0.3 V
Digital Outputs to GND −0.3 V to VIO + 0.3 V
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
θJA Thermal Impedance (MSOP-10) 200°C/W
θJC Thermal Impedance (MSOP-10) 44°C/W
Lead Temperature Range JEDEC J-STD-20

1

See the Analog Inputs section.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

O SDO

50pF

C

L

500µA I

500µA I

OL

1.4V

OH

6394-003

Figure 3. Load Circuit for Digital Interface Timing

30% VIO

t

DELAY

2V OR VIO – 0.5V

0.8V OR 0.5V

12V IF VI O ABOVE 2. 5V, VIO – 0.5V IF VIO BEL OW 2.5V .

20.8V IF V IO ABOVE 2.5V, 0.5V IF VI O BELOW 2.5V.

Figure 4. Voltage Levels for Timing

70% VIO

t

1

2

DELAY

2V OR VIO – 0.5V

0.8V OR 0.5V

1

2

06394-004

Rev. A | Page 6 of 24

AD7693

G

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

REF

VDD

IN+

IN–

GND

1

2

AD7693

3

TOP VIEW

(Not to Scale)

4

5

VIO

10

SDI

9

SCK

8

SDO

7

6

CNV

06394-005

Figure 5. 10-Lead MSOP Pin Configuration

1REF

2VDD

AD7693

3IN+

TOP VIEW

4IN–

(Not to Scale)

5

ND

NOTES

1. THE EXPOSED PAD IS CONNECTED
TO GND. THIS CONNECTION I S NOT

REQUIRED TO MEET THE ELECTRICAL
PERFORMANCES.

Figure 6. 10-Lead QFN (LFCSP) Pin Configuration

10 VIO

9SDI

8SCK

7SDO

6CNV

05793-006

Table 6. Pin Function Descriptions

Pin No. Mnemonic Type1 Description

1 REF AI

Reference Input Voltage. The REF range is from 0.5 V to VDD. It is referred to the GND pin. This

pin should be decoupled closely to the pin with a 10 μF capacitor.
2 VDD P Power Supply.
3 IN+ AI
4 IN− AI
5 GND P
6 CNV DI

Differential Positive Analog Input.

Differential Negative Analog Input.

Power Supply Ground.

Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions

and selects the interface mode of the part: chain or CS

read when CNV is high. In CS

mode, the SDO pin is enabled when CNV is low.

mode. In chain mode, the data should be

7 SDO DO Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.
8 SCK DI

Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this

clock.
9 SDI DI

Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC

as follows:

Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a

data input to daisy-chain the conversion results of two or more ADCs onto a single SDO line.

The digital data level on SDI is output on SDO with a delay of 16 SCK cycles.

mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV

CS

can enable the serial output signals when low and if SDI or CNV is low when the conversion is

complete, the busy indicator feature is enabled.
10 VIO P

Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V,

2.5 V, 3 V, or 5 V).

EPAD

Exposed Pad. The exposed pad is connected to GND. This connection is not required to meet

the electrical performances. The exposed pad is only on the 10-Lead QFN (LFCSP).

1

AI = analog input, DI = digital input, DO = digital output, and P = power.

Rev. A | Page 7 of 24

AD7693

TERMINOLOGY

Least Significant Bit (LSB)

The LSB is the smallest increment that can be represented by a
converter. For a differential analog-to-digital converter with N
bits of resolution, the LSB expressed in volts is

V

2

LSB

(V) =

Integral Nonlinearity Error (INL)

INL refers to the deviation of each individual code from a line
drawn from negative full scale through positive full scale. The
point used as negative full scale occurs ½ LSB before the first
code transition. Positive full scale is defined as a level 1½ LSB
beyond the last code transition. The deviation is measured from
the middle of each code to the true straight line (see Figure 26).

Differential Nonlinearity Error (DNL)

In an ideal ADC, code transitions are 1 LSB apart. DNL is the
maximum deviation from this ideal value. It is often specified in
terms of resolution for which no missing codes are guaranteed.

Zero Error

Zero error is the difference between the ideal midscale voltage,
that is, 0 V, from the actual voltage producing the midscale
output code, that is, 0 LSB.

Gain Error

The first transition (from 100 ... 00 to 100 ... 01) should occur at
a level ½ LSB above nominal negative full scale (−4.999847 V
for the ±5 V range). The last transition (from 011 … 10 to
011 … 11) should occur for an analog voltage 1½ LSB below the
nominal full scale (+4.999771 V for the ±5 V range.) The gain
error is the deviation of the difference between the actual level
of the last transition and the actual level of the first transition
from the difference between the ideal levels.

Aperture Delay

Aperture delay is the measure of the acquisition performance. It
is the time between the rising edge of the CNV input and when
the input signal is held for a conversion.

2

REF

N

Transi ent Res p ons e

Transient response is the time required for the ADC to accurately
acquire its input after a full-scale step function is applied.

Dynamic Range

Dynamic range is the ratio of the rms value of the full scale to
the total rms noise measured with the inputs shorted together.
The value for dynamic range is expressed in decibels.

Signal-to-Noise Ratio (SNR)

SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.

Signal-to-(Noise + Distortion) Ratio (SINAD)

SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
SINAD is expressed in decibels.

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in decibels.

Spurious-Free Dynamic Range (SFDR)

SFDR is the difference, in decibels, between the rms amplitude
of the input signal and the peak spurious signal.

Effective Number of Bits (ENOB)

ENOB is a measurement of the resolution with a sine wave
input. It is related to SINAD by the following formula:

ENOB = (SINAD

and is expressed in bits.

− 1.76)/6.02

dB

Rev. A | Page 8 of 24