ANALOG DEVICES AD7690 Service Manual

18-Bit, 1.5 LSB INL, 400 kSPS PulSAR®

V

FEATURES

18-bit resolution with no missing codes
Throughput: 400 kSPS
INL: ±0.75 LSB typ, ±1.5 LSB max (±6 ppm of FSR)
Dynamic range: 102 dB @ 400 kSPS
Oversampled dynamic range: 125 dB @ 1 kSPS
Noise-free code resolution: 20 bits @ 1 kSPS
Effective resolution: 22.7 bits @ 1 kSPS
SINAD: 101.5 dB @ 1 kHz
THD: −125 dB @ 1 kHz
True differential analog input range: ±VREF

0 V to V
No pipeline delay
Single-supply 5 V operation with

1.8 V/2.5 V/3 V/5 V logic interface
Serial interface, SPI®/QSPI™/MICROWIRE™/DSP compatible
Daisy-chain multiple ADCs and busy indicator
Power dissipation

4.25 μW @ 100 SPS

4.25 mW @ 100 kSPS
Standby current: 1 nA
10-lead package: MSOP (MSOP-8 size) and

3 mm × 3 mm QFN (LFCSP) (SOT-23 size)

Pin-for-pin compatible with QFN/MSOP PulSAR ADCs

APPLICATIONS

Battery-powered equipment
Data acquisition
Seismic data acquisition systems
DVMs
Instrumentation
Medical instruments

with V

REF

1.5

1.0

0.5

0

INL (LSB)

–0.5

–1.0

–1.5

0 262144

up to VDD on both inputs

REF

POSITIVE INL = +0.42LSB
NEGATIVE INL = –0.6LSB

65536 131072 196608

CODE

Figure 1. Integral Nonlinearity vs. Code

05792-025

Differential ADC in MSOP/QFN

AD7690

APPLICATION EXAMPLE

+2.5V TO +5

±10V, ±5V, ...

ADA4941-1

Table 1. MSOP, QFN (LFCSP)/SOT-23
14-/16-/18-Bit PulSAR ADC

Type

18-Bit True

Differential

16-Bit True

Differential

16-Bit Pseudo

Differential

14-Bit Pseudo

Differential

100
kSPS

AD7691 AD7690

AD7684 AD7687 AD7688

AD7680
AD7683

AD7940 AD7942 AD7946 ADA4841

GENERAL DESCRIPTION

The AD7690 is an 18-bit, successive approximation, analog-to­digital converter (ADC) that operates from a single power supply,
VDD. It contains a low power, high speed, 18-bit sampling ADC
with no missing codes, an internal conversion clock, and a
versatile serial interface port. On the CNV rising edge, it
samples the voltage difference between the IN+ and IN− pins.
The voltages on these pins swing in opposite phase between 0 V
and REF. The reference voltage, REF, is applied externally and
can be set up to the supply voltage.

The power of the AD7690 scales linearly with the throughput.

The SPI-compatible serial interface also features the ability,
using the SDI input, to daisy-chain several ADCs on a single,
3-wire bus and provides an optional busy indicator. It is compatible
with 1.8 V, 2.5 V, 3 V, or 5 V logic, using the separate VIO supply.

The AD7690 is housed in a 10-lead MSOP or a 10-lead QFN
(LFCSP) with operation specified from −40°C to +85°C.

REF

IN+

IN–

GND

AD7690

Figure 2.

250
kSPS

AD7685
AD7694

+5V

VDD

VIO

SDI
SCK
SDO
CNV

+1.8V TO VDD

3- OR 4-WIRE
INTERFACE
(SPI, DAISY CHAI N, CS)

400 kSPS
to
500 kSPS

1000
kSPS

AD7982 ADA4941

AD7982

ADA4941

AD7693
AD7686 AD7980 ADA4841

ADC
Driver

ADA4841

ADA4841

5792-001

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006–2011 Analog Devices, Inc. All rights reserved.

AD7690

TABLE OF CONTENTS

Features .............................................................................................. 1

Driver Amplifier Choice ........................................................... 14

Applications ....................................................................................... 1

Application Example ........................................................................ 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Timing Specifications ....................................................................... 5

Absolute Maximum Ratings ............................................................ 6

ESD Caution .................................................................................. 6

Pin Configurations and Function Descriptions ........................... 7

Terminolog y ...................................................................................... 8

Typical Performance Characteristics ............................................. 9

Theory of Operation ...................................................................... 12

Circuit Information .................................................................... 12

Converter Operation .................................................................. 12

Typical Connection Diagram ................................................... 13

Analog Inputs .............................................................................. 14

Single-to-Differential Driver .................................................... 15

Voltage Reference Input ............................................................ 15

Power Supply ............................................................................... 16

Supplying the ADC from the Reference .................................. 16

Digital Interface .......................................................................... 16

CS

Mode, 3-Wire Without Busy Indicator ............................. 17

CS

Mode, 3-Wire With Busy Indicator ................................... 18

CS

Mode, 4-Wire Without Busy Indicator ............................. 19

CS

Mode, 4-Wire With Busy Indicator ................................... 20

Chain Mode Without Busy Indicator ...................................... 21

Chain Mode with Busy Indicator ............................................. 22

Application Hints ........................................................................... 23

Layout .......................................................................................... 23

Evaluating the AD7690’s Performance .................................... 23

Outline Dimensions ....................................................................... 24

Ordering Guide .......................................................................... 24

REVISION HISTORY

7/11—Rev. A to Rev. B

Changes to Common-Mode Input Range Min Parameter ......... 3

Added EPAD Note to Figure 6 and Table 6 ................................... 7

Updated Outline Dimensions ....................................................... 24

Changes to Ordering Guide .......................................................... 24

3/07—Rev. 0 to Rev. A

Removed Endnote Regarding QFN Package .................. Universal

Changes to Features .......................................................................... 1

Changes to Table 1 ............................................................................ 1

Changes to Figure 2 .......................................................................... 1

Changes to Gain Error in Table 2 ................................................... 3

Change to Gain Error Temperature Drift in Table 2 ................... 3

Change to Zero Temperature Drift in Table 2 .............................. 3

Changes to Power Dissipation in Table 3 ...................................... 4

Change to Conversion Time:

CNV Rising Edge to Data Available in Table 4 ........................ 5

Change to Acquisition Time in Table 4 .......................................... 5

Changes to Figure 12 ......................................................................... 9

Change to Figure 22 Caption ........................................................ 11

Changes to Circuit Information Section ..................................... 12

Change to Table 7 ........................................................................... 13

Change to Endnote 1 of Figure 26 ................................................ 13

Added Figure 29 ............................................................................. 14

Changes to Driver Amplifier Choice Section ............................. 14

Change to Evaluating the AD7690’s Performance Section ....... 23

Updated Outline Dimensions ....................................................... 24

Changes to Ordering Guide .......................................................... 24

4/06—Revision 0: Initial Version

Rev. B | Page 2 of 24

AD7690

SPECIFICATIONS

VDD = 4.75 V to 5.25 V, VIO = 2.3 V to VDD, V

Table 2.

Parameter Conditions Min Typ Max Unit

RESOLUTION 18 Bits
ANALOG INPUT

Voltage Range IN+ to IN− −V
Absolute Input Voltage IN+, IN− −0.1 V
Common-Mode Input Range IN+, IN− V
Analog Input CMRR fIN = 250 kHz 65 dB
Leakage Current at 25°C Acquisition phase 1 nA
Input Impedance1

THROUGHPUT

Conversion Rate 0 400 kSPS
Transient Response Full-scale step 400 ns

ACCURACY

No Missing Codes 18 Bits
Integral Linearity Error −1.5 ±0.75 +1.5 LSB2
Differential Linearity Error −1 ±0.5 +1.25 LSB
Transition Noise REF = VDD = 5 V 0.75 LSB
Gain Error3 −40 ±2 +40 LSB
Gain Error Temperature Drift ±0.3 ppm/°C
Zero Error3 −0.8 +0.8 mV
Zero Temperature Drift ±0.3 ppm/°C
Power Supply Sensitivity

VDD = 5 V ± 5%

AC ACCURACY

Dynamic Range V

= 5 V 101 102 dB4

REF

Oversampled Dynamic Range5 fIN= 1 kSPS 125 dB
Signal-to-Noise fIN = 1 kHz, V
f

= 1 kHz, V

IN

Spurious-Free Dynamic Range fIN = 1 kHz, V
Total Harmonic Distortion fIN = 1 kHz, V
Signal-to-(Noise + Distortion) fIN = 1 kHz, V
Intermodulation Distortion6 115 dB

1

See the Analog Inputs section.

2

LSB means least significant bit. With the ±5 V input range, one LSB is 38.15 μV.

3

See the Terminology section. These specifications include full temperature range variation but not the error contribution from the external reference.

4

All specifications in dB are referred to a full-scale input FSR. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.

5

Dynamic range obtained by oversampling the ADC running at a throughput fS of 400 kSPS, followed by postdigital filtering with an output word rate fO.

6

f

= 21.4 kHz and f

IN1

= 18.9 kHz, with each tone at −7 dB below full scale.

IN2

= VDD, all specifications T

REF

to T

MIN

+V

REF

/2 − 0.1 V

REF

, unless otherwise noted.

MAX

/2 V

REF

V

REF

+ 0.1 V

REF

/2 + 0.1 V

REF

±0.25 LSB

= 5 V 100 101.5 dB

REF

= 2.5 V 94.5 96 dB

REF

= 5 V −125 dB

REF

= 5 V −125 dB

REF

= 5 V 100 101.5 dB

REF

Rev. B | Page 3 of 24

AD7690

VDD = 4.75 V to 5.25 V, VIO = 2.3 V to VDD, V

Table 3.

Parameter Conditions Min Typ Max Unit

REFERENCE

Voltage Range 0.5 VDD + 0.3 V
Load Current 400 kSPS, REF = 5 V 100 μA

SAMPLING DYNAMICS

−3 dB Input Bandwidth 9 MHz
Aperture Delay VDD = 5 V 2.5 ns

DIGITAL INPUTS

Logic Levels

VIL −0.3 +0.3 × VIO V
VIH 0.7 × VIO VIO + 0.3 V
IIL −1 +1 μA
IIH −1 +1 μA

DIGITAL OUTPUTS

Data Format Serial 18 bits, twos complement
Pipeline Delay

VOL I
VOH I

= +500 μA 0.4 V

SINK

= −500 μA VIO − 0.3 V

SOURCE

POWER SUPPLIES

VDD Specified performance 4.75 5.25 V
VIO Specified performance 2.3 VDD + 0.3 V
VIO Range 1.8 VDD + 0.3 V
Standby Current

1, 2

VDD and VIO = 5 V, 25°C 1 50 nA
Power Dissipation VDD = 5 V, 100 SPS throughput 4.25 μW
VDD = 5 V, 100 kSPS throughput 4.25 5 mW
VDD = 5 V, 400 kSPS throughput 17 20 mW
Energy per Conversion 50 nJ/sample

TEMPERATURE RANGE3

Specified Performance T

1

With all digital inputs forced to VIO or GND as required.

2

During acquisition phase.

3

Contact an Analog Devices, Inc., sales representative for the extended temperature range.

MIN

to T

= VDD, all specifications T

REF

MIN

to T

, unless otherwise noted.

MAX

Conversion results available immediately

after completed conversion

−40 +85 °C

MAX

Rev. B | Page 4 of 24

AD7690

TIMING SPECIFICATIONS

VDD = 4.75 V to 5.25 V, VIO = 2.3 V to VDD, V

= VDD, all specifications T

REF

MIN

to T

, unless otherwise noted.

MAX

Table 4.

1

Parameter Symbol Min Typ Max Unit

Conversion Time: CNV Rising Edge to Data Available t
Acquisition Time t
Time Between Conversions t
CNV Pulse Width (CS Mode)
SCK Period (CS Mode)
SCK Period (Chain Mode) t

0.5 2.1 μs

CONV

400 ns

ACQ

2.5 μs

CYC

t

10 ns

CNVH

t

15 ns

SCK

SCK

VIO Above 4.5 V 17 ns
VIO Above 3 V 18 ns
VIO Above 2.7 V 19 ns

VIO Above 2.3 V 20 ns
SCK Low Time t
SCK High Time t
SCK Falling Edge to Data Remains Valid t
SCK Falling Edge to Data Valid Delay t

7 ns

SCKL

7 ns

SCKH

4 ns

HSDO

DSDO

VIO Above 4.5 V 14 ns

VIO Above 3 V 15 ns

VIO Above 2.7 V 16 ns

VIO Above 2.3 V 17 ns

t

CNV or SDI Low to SDO D17 MSB Valid (CS Mode)

EN

VIO Above 4.5 V 15 ns

VIO Above 2.7 V 18 ns

VIO Above 2.3 V 22 ns

t

CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
SDI Valid Setup Time from CNV Rising Edge (CS Mode)
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
SCK Valid Setup Time from CNV Rising Edge (Chain Mode) t
SCK Valid Hold Time from CNV Rising Edge (Chain Mode) t
SDI Valid Setup Time from SCK Falling Edge (Chain Mode) t
SDI Valid Hold Time from SCK Falling Edge (Chain Mode) t
SDI High to SDO High (Chain Mode with BUSY Indicator) t

25 ns

DIS

t

15 ns

SSDICNV

t

0 ns

HSDICNV

5 ns

SSCKCNV

10 ns

HSCKCNV

3 ns

SSDISCK

4 ns

HSDISCK

DSDOSDI

VIO Above 4.5 V 15 ns

VIO Above 2.3 V 26 ns

1

See Figure 3 and Figure 4 for load conditions.

70% VIO

t

1

2

DELAY

2V OR VIO – 0.5V

0.8V OR 0.5V

1

2

02968-003

TO SDO

50pF

C

L

500μAI

500μAI

OL

1.4V

OH

02968-002

Figure 3. Load Circuit for Digital Interface Timing

30% VIO

t

DELAY

2V OR VIO – 0.5V

0.8V OR 0.5V

NOTES:

1. 2V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V.

2. 0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.

Figure 4. Voltage Levels for Timing

Rev. B | Page 5 of 24

AD7690

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Rating

Analog Inputs

IN+,1 IN−1

REF GND − 0.3 V to VDD + 0.3 V
Supply Voltages

VDD, VIO to GND −0.3 V to +7 V

VDD to VIO ±7 V
Digital Inputs to GND −0.3 V to VIO + 0.3 V
Digital Outputs to GND −0.3 V to VIO + 0.3 V
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
θJA Thermal Impedance

(10-Lead MSOP)
θJC Thermal Impedance

(10-Lead MSOP)
Lead Temperature Range JEDEC J-STD-20

1

See the Analog Inputs section.

GND − 0.3 V to VDD + 0.3 V
or ±130 mA

200°C/W

44°C/W

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. B | Page 6 of 24

AD7690

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

REF

VDD

IN+

IN–

GND

1

2

AD7690

3

TOP VIEW

(Not to Scale)

4

5

10

VIO

SDI

9

8

SCK

SDO

7

CNV

6

05792-004

Figure 5. 10-Lead MSOP Pin Configuration

1REF

2VDD

AD7690

3IN+

TOP VIEW

4IN–

(Not to Scale)

5GND

NOTES

1. THE EXPOSED PAD I S NOT CONNECTED
INTERNALL Y. FO R INCREASED REL IABILI TY OF
THE SOL DER JOINT S, IT IS RECOMMENDED THAT
THE PAD BE SO LDERED TO THE G ROUND PLANE.

Figure 6. 10-Lead QFN (LFCSP) Pin Configuration

10 VIO

9SDI

8SCK

7SDO

6CNV

5792-005

Table 6. Pin Function Descriptions

Pin No. Mnemonic Type1 Description

1 REF AI

Reference Input Voltage. The REF range is from 0.5 V to VDD. It is referred to the GND pin. This

pin should be decoupled closely to the pin with a 10 μF capacitor.
2 VDD P Power Supply.
3 IN+ AI Differential Positive Analog Input.
4 IN− AI Differential Negative Analog Input.
5 GND P Power Supply Ground.
6 CNV DI

Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions

and selects the interface mode of the part, chain or CS mode. In CS mode, the SDO pin is

enabled when CNV is low. In chain mode, the data should be read when CNV is high.
7 SDO DO Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.
8 SCK DI Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock.
9 SDI DI

Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC

as follows:

Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a

data input to daisy-chain the conversion results of two or more ADCs onto a single SDO line.

The digital data level on SDI is output on SDO with a delay of 18 SCK cycles.

mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV

CS

can enable the serial output signals when low. If SDI or CNV is low when the conversion is

complete, the busy indicator feature is enabled.
10 VIO P

Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V,

2.5 V, 3 V, or 5 V).

EPAD

Exposed Pad. The exposed pad is not connected internally. For increased reliability of the solder

joints, it is recommended that the pad be soldered to the ground plane.

1

AI = analog input, DI = digital input, DO = digital output, and P = power.

Rev. B | Page 7 of 24

AD7690

TERMINOLOGY

Integral Nonlinearity Error (INL)

INL refers to the deviation of each individual code from a line
drawn from negative full scale through positive full scale. The
point used as negative full scale occurs ½ LSB before the first
code transition. Positive full scale is defined as a level 1½ LSB
beyond the last code transition. The deviation is measured from
the middle of each code to the true straight line (see Figure 25).

Differential Nonlinearity Error (DNL)

In an ideal ADC, code transitions are 1 LSB apart. DNL is the
maximum deviation from this ideal value. It is often specified in
terms of resolution for which no missing codes are guaranteed.

Zero Error

Zero error is the difference between the ideal midscale voltage,
that is, 0 V, from the actual voltage producing the midscale
output code, that is, 0 LSB.

Gain Error

The first transition (from 100 ... 00 to 100 ... 01) should occur at
a level ½ LSB above nominal negative full scale (−4.999981 V
for the ±5 V range). The last transition (from 011 … 10 to
011 … 11) should occur for an analog voltage 1½ LSB below the
nominal full scale (+4.999943 V for the ±5 V range). The gain
error is the deviation of the difference between the actual level
of the last transition and the actual level of the first transition
from the difference between the ideal levels.

Spurious-Free Dynamic Range (SFDR)

SFDR is the difference, in decibels, between the rms amplitude
of the input signal and the peak spurious signal.

Effective Number of Bits (ENOB)

ENOB is a measurement of the resolution with a sine wave
input. It is related to SINAD by the following formula:

ENOB = (SINAD

− 1.76)/6.02

dB

and is expressed in bits.

Noise-Free Code Resolution

Noise-free code resolution is the number of bits beyond which it is
impossible to distinctly resolve individual codes. It is calculated as:

Noise-Free Code Resolution = log

(2N/Peak-to-Peak Noise)

2

and is expressed in bits.

Effective Resolution

Effective resolution is calculated as

Effective Resolution = log

(2N/RMS Input Noise)

2

and is expressed in bits.

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in decibels.

Dynamic Range

Dynamic range is the ratio of the rms value of the full scale to
the total rms noise measured with the inputs shorted together.
The value for dynamic range is expressed in decibels.

Signal-to-Noise Ratio (SNR)

SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components that is less than the
Nyquist frequency, excluding harmonics and dc. The value of
SNR is expressed in decibels.

Signal-to-(Noise + Distortion) Ratio (SINAD)

SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
SINAD is expressed in decibels.

Aperture Delay

Aperture delay is the measure of the acquisition performance. It
is the time between the rising edge of the CNV input and when
the input signal is held for a conversion.

Transi en t Re s pons e

Transient response is the time required for the ADC to accurately
acquire its input after a full-scale step function is applied.

Rev. B | Page 8 of 24