ANALOG DEVICES AD 7689 BCPZ Datasheet

16-Bit, 4-Channel/8-Channel,

Data Sheet

FEATURES

16-bit resolution with no missing codes 4-channel (AD7682)/8-channel (AD7689) multiplexer with

choice of inputs Unipolar single-ended Differential (GND sense) Pseudobipolar Throughput: 250 kSPS INL: ±0.4 LSB typical, ±1.5 LSB maximum (±23 ppm or FSR) Dynamic range: 93.8 dB SINAD: 92.5 dB at 20 kHz THD: −100 dB at 20 kHz Analog input range: 0 V to V Multiple reference types

Internal selectable 2.5 V or 4.096 V External buffered (up to 4.096 V)

External (up to VDD) Internal temperature sensor (TEMP) Channel sequencer, selectable 1-pole filter, busy indicator No pipeline delay, SAR architecture Single-supply 2.3 V to 5.5 V operation with 1.8 V to 5.5 V

logic interface

Serial interface compatible with SPI, MICROWIRE, QSPI,

and DSP

Power dissipation

3.5 mW at 2.5 V/200 kSPS

12.5 mW at 5 V/250 kSPS Standby current: 50 nA Low cost grade available 20-lead 4 mm × 4 mm LFCSP package 20-lead 2.4 mm × 2.4 mm WLCSP package

APPLICATIONS

Multichannel system monitoring Battery-powered equipment Medical instruments: ECG/EKG Mobile communications: GPS Power line monitoring Data acquisition Seismic data acquisition systems Instrumentation Process control

Rev. F Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

with V

REF

up to VDD

REF

250 kSPS PulSAR ADC

AD7682/AD7689

FUNCTIONAL BLOCK DIAGRAM

0.5V TO VDD

10µF

ONE-POLE

LPF

Figure 1.

REF

AD7682/AD7689

16-BIT SAR

ADC

SEQUENCER

IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7

COM

0.5V TO VDD – 0.5V

0.1µF

BAND GAP

REF

TEMP

SENSOR

REFIN

MUX

GENERAL DESCRIPTION

The AD7682/AD7689 are 4-channel/8-channel, 16-bit, charge redistribution successive approximation register (SAR) analogto-digital converters (ADCs) that operate from a single power supply, VDD.

The AD7682/AD7689 contain all components for use in a multichannel, low power data acquisition system, including a true 16-bit SAR ADC with no missing codes; a 4-channel (AD7682) or 8-channel (AD7689) low crosstalk multiplexer that is useful for configuring the inputs as single-ended (with or without ground sense), differential, or bipolar; an internal low drift reference (selectable 2.5 V or 4.096 V) and buffer; a temperature sensor; a selectable one-pole filter; and a sequencer that is useful when channels are continuously scanned in order.

The AD7682/AD7689 use a simple SPI interface for writing to the configuration register and receiving conversion results. The SPI interface uses a separate supply, VIO, which is set to the host logic level. Power dissipation scales with throughput.

The AD7682/AD7689 are housed in a tiny 20-lead LFCSP and 20-lead WLCSP with operation specified from −40°C to +85°C.

Table 1. Multichannel 14-/16-Bit PulSAR® ADCs

Type Channels 250 kSPS 500 kSPS ADC Driver

14-Bit

16-Bit 4

16-Bit 8

Technical Support www.analog.com

8 AD7949

AD7682

AD7689 AD7699

2.3V TO 5.5V

VDD

SPI SERIAL INTERFACE

GND

ADA4805-1/ ADA4807-1

VIO

1.8V TO VDD

CNV

SCK

SDO

DIN

07353-001

AD7682/AD7689 Data Sheet

Features .............................................................................................. 1

Applications ....................................................................................... 1 

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 4

Timing Specifications .................................................................. 7

Absolute Maximum Ratings ............................................................ 9

ESD Caution .................................................................................. 9

Pin Configurations and Function Descriptions ......................... 10

Typical Performance Characteristics ........................................... 14

Terminology .................................................................................... 17

Theory of Operation ...................................................................... 18

Overview ...................................................................................... 18

Converter Operation .................................................................. 18

Transfer Functions...................................................................... 19

Typical Connection Diagrams .................................................. 20

Analog Inputs .............................................................................. 21

Driver Amplifier Choice ............................................................ 23

Voltage Reference Output/Input .............................................. 23

Power Supply ............................................................................... 25

Supplying the ADC from the Reference .................................. 25

Digital Interface .............................................................................. 26

Reading/Writing During Conversion, Fast Hosts .................. 26

Reading/Writing After Conversion, Any Speed Hosts .......... 26

Reading/Writing Spanning Conversion, Any Speed Host .... 26

Configuration Register, CFG .................................................... 26

General Timing Without a Busy Indicator ............................. 28

General Timing with a Busy Indicator .................................... 29

Channel Sequencer .................................................................... 30

Read/Write Spanning Conversion Without a Busy Indicator

....................................................................................................... 31

Read/Write Spanning Conversion with a Busy Indicator ..... 32

Applications Information .............................................................. 33

Layout .......................................................................................... 33

Evaluating the AD7682/AD7689 Performance ........................ 33

Outline Dimensions ....................................................................... 34

Ordering Guide .......................................................................... 35



REVISION HISTORY

4/16—Rev. E to Rev. F

Changed ADA4841-x to ADA4805-1/ADA4807-1, Table 1 ....... 1

Added Endnote 6, Table 3; Renumbered Sequentially ................ 6

Changes to Figure 28 and Figure 29 ............................................. 20

Changes to Table 10 ........................................................................ 23

Changes to External Reference Section and the Reference

Decoupling Section ........................................................................ 24

Changes to the Supplying the ADC from the Reference Section .. 25

Changes to Ordering Guide .......................................................... 35

1/15—Rev. D to Rev. E

Added WLCSP (Throughout) ......................................................... 1

Added WLCSP Signal-to-Noise and SINAD Parameters;

Table 2 ................................................................................................ 3

Changed θ

48°C/W .............................................................................................. 9

Added Figure 6, Figure 7, and Table 8 ......................................... 12

Changes to Layout Section ............................................................ 33

Added Figure 47; Outline Dimensions ........................................ 34

Changes to Ordering Guide .......................................................... 35

Thermal Impedance (LFCSP) from 47.6°C/W to

4/12—Rev. C to Rev. D

Changes to Figure 27 ...................................................................... 18

Changed Internal Reference Section to Internal

Reference/Temperature Sensor Section ....................................... 21

Changes to Internal Reference/Temperature Sensor Section ... 21 Changed External Reference/Temperature Sensor Section to

External Reference Section ........................................................... 22

Changes to External Reference and Internal Buffer Section and

External Reference Section ........................................................... 22

Changes to REF Bit, Function Column, Table 10 ...................... 25

Updated Outline Dimensions ....................................................... 32

9/11—Rev. B to Rev. C

Changes to Internal Reference Section ........................................ 21

Changes to the External Reference and Internal Buffer

Section .............................................................................................. 22

Changes to the External Reference/Temperature Sensor

Section .............................................................................................. 22

Changes to Table 10, REF Bit Description .................................. 25

Rev. F | Page 2 of 35

Data Sheet AD7682/AD7689

6/09—Rev. A to Rev. B

Changes Table 6 ................................................................................. 8

Changes to Figure 37 ...................................................................... 25

Changes to Figure 38 ...................................................................... 26

3/09—Rev. 0 to Rev. A

Changes to Features Section, Applications Section, and

Figure 1 ............................................................................................... 1

Added Table 2; Renumbered Sequentially ..................................... 3

Changed VREF to V

Changes to Table 3 ............................................................................ 5

Changes to Table 4 ............................................................................ 6

Changes to Table 5 ............................................................................ 7

Deleted Endnote 2 in Table 6 ........................................................... 8

Changes to Figure 4, Figure 5, and Table 7 .................................... 9

Changes to Figure 6, Figure 9, and Figure 10 .............................. 11

Changes to Figure 22 ...................................................................... 13

Changes to Overview Section and Converter Operation

Section .............................................................................................. 15

Changes to Table 8 .......................................................................... 16

Changes to Figure 26 and Figure 27 ............................................. 17

Changes to Bipolar Single Supply Section and Analog Inputs

Section .............................................................................................. 18

Changes to Internal Reference/Temperature Sensor Section .... 20

..................................................................... 4

REF

Added Figure 31; Renumbered Sequentially ............................... 20

Changes to External Reference and Internal Buffer Section and

External Reference Section ............................................................ 21

Added Figure 32 and Figure 33 ..................................................... 21

Changes to Power Supply Section ................................................. 22

Changes to Digital Interface Section, Reading/Writing After Conversion, Any Speed Hosts Section, and Configuration

Changes to Table 10 ........................................................................ 24

Added General Timing Without a Busy Indicator Section and

Figure 37 ........................................................................................... 25

Added General Timing With a Busy Indicator Section and

Figure 38 ........................................................................................... 26

Added Channel Sequencer Section and Figure 39 ..................... 27

Changes to Read/Write Spanning Conversion Without a Busy

Indicator Section and Figure 41 .................................................... 28

Changes to Read/Write Spanning Conversion with a Busy

Indicator and Figure 43 .................................................................. 29

Changes to Evaluating AD7682/AD7689 Performance

Section .............................................................................................. 30

Added Exposed Pad Notation to Outline Dimensions .............. 31

Changes to Ordering Guide ........................................................... 31

5/08—Revision 0: Initial Version

Rev. F | Page 3 of 35

AD7682/AD7689 Data Sheet

SPECIFICATIONS

VDD = 2.3 V to 5.5 V, VIO = 1.8 V to VDD, V

Table 2.

Test Conditions/

Parameter

Comments

RESOLUTION 16 16 Bits ANALOG INPUT

Voltage Range Unipolar mode 0 +V

Bipolar mode −V

Absolute Input Voltage

Positive input, unipolar and bipolar modes

Negative or COM input, unipolar mode

Negative or COM input,

bipolar mode Analog Input CMRR fIN = 250 kHz 68 68 dB Leakage Current at 25°C Acquisition phase 1 1 nA Input Impedance1

THROUGHPUT

Conversion Rate

Full Bandwidth2 VDD = 4.5 V to 5.5 V 0 250 0 250 kSPS VDD = 2.3 V to 4.5 V 0 200 0 200 kSPS

¼ Bandwidth2 VDD = 4.5 V to 5.5 V 0 62.5 0 62.5 kSPS VDD = 2.3 V to 4.5 V 0 50 0 50 kSPS Transient Response

Full-scale step, full bandwidth

Full-scale step, ¼ bandwidth

ACCURACY

No Missing Codes 15 16 Bits Integral Linearity Error −4 +4 −1.5 ±0.4 +1.5 LSB3 Differential Linearity Error −1 ±0.25 +1.5 LSB Transition Noise REF = VDD = 5 V 0.6 0.5 LSB Gain Error4 −32 +32 −8 ±1 +8 LSB Gain Error Match ±2 −4 ±0.5 +4 LSB Gain Error Temperature

±1 ±1 ppm/°C

Drift Offset Error4 VDD = 4.5 V to 5.5 V −32 +32 −8 ±1 +8 LSB VDD = 2.3 V to 4.5 V ±32 ±5 LSB Offset Error Match ±2 −4 ±0.5 +4 LSB Offset Error Temperature

±1 ±1 ppm/°C

Drift Power Supply Sensitivity VDD = 5 V ± 5% ±1.5 ±1.5 LSB

AC ACCURACY5

Dynamic Range 90.5 93.8 dB6 Signal-to-Noise

LFCSP fIN = 20 kHz, V

= 20 kHz, V

internal REF

= 20 kHz, V

internal REF

= VDD, all specifications T

REF

MIN

to T

, unless otherwise noted.

MAX

AD7689A AD7682B/AD7689B

Unit Min Typ Max Min Typ Max

/2 +V

REF

−0.1 V

0 +V

REF

/2 −V

REF

+ 0.1 −0.1 V

REF

/2 +V

REF

+ 0.1 V

REF

−0.1 +0.1 −0.1 +0.1 V

/2 − 0.1 V

REF

/2 V

/2 + 0.1 V

REF

/2 − 0.1 V

REF

/2 V

REF

/2 + 0.1 V

REF

1.8 1.8 s

14.5 14.5 s

= 5 V 90 92.5 93.5 dB

REF

= 4.096 V,

REF

= 2.5 V,

REF

89 91 92.3 dB

86 87.5 88.8 dB

Rev. F | Page 4 of 35

Data Sheet AD7682/AD7689

Test Conditions/

Parameter

WLFCSP fIN = 20 kHz, V

Comments

= 20 kHz, V

= 5 V 91 92 dB

REF

= 4.096 V,

REF

89.5 91 dB

internal REF

= 20 kHz, V

= 2.5 V,

REF

86 87.5 dB

internal REF

SINAD

LFCSP fIN = 20 kHz, V

= 20 kHz, V

= 5 V 89 91 92.5 dB

REF

= 5 V,

REF

30.5 33.5 dB

−60 dB input = 20 kHz, V

= 4.096 V

REF

88 90 91 dB

internal REF

= 20 kHz, V

= 2.5 V

REF

86 87 88.4 dB

internal REF

WLFCSP fIN = 20 kHz, V

= 20 kHz, V

= 5 V 89.5 91 dB

REF

= 5 V,

REF

32 dB

−60 dB input = 20 kHz, V

= 4.096 V

REF

88.5 89.5 dB

internal REF

= 20 kHz, V

= 2.5 V

REF

85.5 87 dB

internal REF

= 20 kHz −97 −100 dB

Tot al H a r monic

Distortion (THD)

= 20 kHz 105 110 dB

Spurious-Free Dynamic

Range

Channel-to-Channel

Crosstalk

fIN = 100 kHz on adjacent channel(s)

−120 −125 dB

SAMPLING DYNAMICS

−3 dB Input Bandwidth Full bandwidth 1.7 1.7 MHz ¼ bandwidth 0.425 0.425 MHz Aperture Delay VDD = 5 V 2.5 2.5 ns

See the Analog Inputs section.

The bandwidth is set in the configuration register.

LSB means least significant bit. With the 5 V input range, one LSB is 76.3 µV.

See the Terminology section. These specifications include full temperature range variation but not the error contribution from the external reference.

With VDD = 5 V, unless otherwise noted.

All specifications expressed in decibels are referred to a full-scale input FSR and tested with an input signal at 0.5 dB below full scale, unless otherwise specified.

AD7689A AD7682B/AD7689B

Unit Min Typ Max Min Typ Max

Rev. F | Page 5 of 35

AD7682/AD7689 Data Sheet

VDD = 2.3 V to 5.5 V, VIO = 1.8 V to VDD, V

Table 3.

Parameter Test Conditions/Comments Min Typ Max Unit

INTERNAL REFERENCE

REF Output Voltage 2.5 V at 25°C 2.490 2.500 2.510 V

4.096 V at 25°C 4.086 4.096 4.106 V REFIN Output Voltage1 2.5 V at 25°C 1.2 V

4.096 V at 25°C 2.3 V REF Output Current ±300 µA Temperature Drift ±10 ppm/°C Line Regulation VDD = 5 V ± 5% ±15 ppm/V Long-Term Drift 1000 hours 50 ppm Turn-On Settling Time C

= 10 µF 5 ms

REF

EXTERNAL REFERENCE

Voltage Range REF input 0.5 VDD + 0.3 V REFIN input (buffered) 0.5 VDD − 0.5 V Current Drain2 250 kSPS, REF = 5 V 50 µA

TEMPERATURE SENSOR

Output Voltage3 25°C 283 mV Temperature Sensitivity 1 mV/°C

DIGITAL INPUTS

Logic Levels

VIL −0.3 +0.3 × VIO V VIH 0.7 × VIO VIO + 0.3 V IIL −1 +1 µA IIH −1 +1 µA

DIGITAL OUTPUTS

Data Format4 Pipeline Delay5 VOL I VOH I

= +500 µA 0.4 V

SINK

SOURCE

POWER SUPPLIES

VDD6 Specified performance 2.3 5.5 V VIO Specified performance 1.8 VDD + 0.3 V Standby Current7, 8 VDD and VIO = 5 V at 25°C 50 nA Power Dissipation VDD = 2.5 V, 100 SPS throughput 1.7 µW VDD = 2.5 V, 200 kSPS throughput 3.5 mW VDD = 5 V, 250 kSPS throughput 12.5 18 mW VDD = 5 V, 250 kSPS throughput with internal reference 15.5 21 mW Energy per Conversion VDD = 5 V 60 nJ

TEMPERATURE RANGE9

Specified Performance T

This is the output from the internal band gap.

This is an average current and scales with throughput.

The output voltage is internal and present on a dedicated multiplexer input.

Unipolar mode is serial 16-bit straight binary. Bipolar mode is serial 16-bit twos complement.

Conversion results available immediately after completed conversion.

The minimum VDD supply must be 3 V when the 2.5 V internal reference is enabled, and 4.5 V when the 4.096 V internal reference is enabled. See Figure 23 for more

information.

With all digital inputs forced to VIO or GND as required.

During acquisition phase.

Contact an Analog Devices, Inc., sales representative for the extended temperature range.

MIN

to T

= VDD, all specifications T

REF

MIN

to T

, unless otherwise noted.

MAX

= −500 µA VIO − 0.3 V

−40 +85 °C

MAX

Rev. F | Page 6 of 35

Data Sheet AD7682/AD7689

TIMING SPECIFICATIONS

VDD = 4.5 V to 5.5 V, VIO = 1.8 V to VDD, all specifications T

Table 4.

Parameter1 Symbol Min Typ Max Unit

CONVERSION TIME

CNV Rising Edge to Data Available t ACQUISITION TIME t TIME BETWEEN CONVERSIONS t DATA WRITE/READ DURING CONVERSION t SCK

Period t

Low Time t

High Time t

Falling Edge to Data Remains Valid t

Falling Edge to Data Valid Delay t

VIO Above 2.7 V 18 ns VIO Above 2.3 V 23 ns

VIO Above 1.8 V 28 ns

CNV

Pulse Width t

Low to SDO D15 MSB Valid tEN

VIO Above 2.7 V 18 ns VIO Above 2.3 V 22 ns

VIO Above 1.8 V 25 ns High or Last SCK Falling Edge to SDO High Impedance t Low to SCK Rising Edge t

DIN

Valid Setup Time from SCK Rising Edge t Valid Hold Time from SCK Rising Edge t

See Figure 2 and Figure 3 for load conditions.

MIN

to T

, unless otherwise noted.

MAX

2.2 µs

CONV

1.8 µs

ACQ

4.0 µs

CYC

1.2 µs

DATA

SCK

11 ns

SCKL

11 ns

SCKH

4 ns

HSDO

DSDO

10 ns

CNVH

32 ns

DIS

10 ns

CLSCK

5 ns

SDIN

5 ns

HDIN

+ 2 ns

DSDO

Rev. F | Page 7 of 35

AD7682/AD7689 Data Sheet

VDD = 2.3 V to 4.5 V, VIO = 1.8 V to VDD, all specifications T

Table 5.

Parameter1 Symbol Min Typ Max Unit

CONVERSION TIME t

CNV Rising Edge to Data Available ACQUISITION TIME t TIME BETWEEN CONVERSIONS t DATA WRITE/READ DURING CONVERSION t SCK

Period t

Low Time t

High Time t

Falling Edge to Data Remains Valid t

Falling Edge to Data Valid Delay t

VIO Above 3 V 24 ns VIO Above 2.7 V 30 ns VIO Above 2.3 V 38 ns VIO Above 1.8 V 48 ns

CNV tEN

Pulse Width t

Low to SDO D15 MSB Valid

VIO Above 3 V 21 ns VIO Above 2.7 V 27 ns VIO Above 2.3 V 35 ns

VIO Above 1.8 V 45 ns High or Last SCK Falling Edge to SDO High Impedance t Low to SCK Rising Edge t

DIN

Valid Setup Time from SCK Rising Edge t Valid Hold Time from SCK Rising Edge t

See Figure 2 and Figure 3 for load conditions.

MIN

to T

, unless otherwise noted.

MAX

3.2 µs

CONV

1.8 µs

ACQ

5 µs

CYC

1.2 µs

DATA

SCK

12 ns

SCKL

12 ns

SCKH

5 ns

HSDO

DSDO

10 ns

CNVH

50 ns

DIS

10 ns

CLSCK

5 ns

SDIN

5 ns

HDIN

+ 2 ns

DSDO

1.4V

07353-002

OSDO

50pF

500µA

Figure 2. Load Circuit for Digital Interface Timing

0% VI

DELAY

2V OR VIO – 0. 5V

0.8V OR 0.5V

2V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V.

0.8V IF VI O ABOVE 2.5V, 0.5V IF VI O BELOW 2.5V.

Figure 3. Voltage Levels for Timing

Rev. F | Page 8 of 35

70% VIO

DELAY

2V OR VI O – 0.5V

0.8V OR 0.5V

07353-003

Data Sheet AD7682/AD7689

ABSOLUTE MAXIMUM RATINGS

Table 6.

Parameter Rating

Analog Inputs

INx,1 COM

REF, REFIN GND − 0.3 V to VDD + 0.3 V Supply Voltages

VDD, VIO to GND −0.3 V to +7 V

VIO to VDD −0.3 V to VDD + 0.3 V DIN, CNV, SCK to GND −0.3 V to VIO + 0.3 V SDO to GND −0.3 V to VIO + 0.3 V Storage Temperature Range −65°C to +150°C Junction Temperature 150°C θJA Thermal Impedance (LFCSP) 48° C/W θJC Thermal Impedance (LFCSP) 4. 4°C/W

See the Analog Inputs section.

GND − 0.3 V to VDD + 0.3 V or VDD ± 130 mA

Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.

ESD CAUTION

Rev. F | Page 9 of 35

AD7682/AD7689 Data Sheet

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

IN1

VDD

IN0

VDD

IN1

IN3

IN0

IN2

PIN 1 INDICATOR

1VDD 2REF

AD7682

3REFIN 4GND

TOP VIEW

5GND

(Not to Scale)

IN2

NOTES

1. NC = NO CONNECT. . THE EXPOSED PAD IS NOT CONNECTED

INTERNALLY. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS, IT IS RECO MMENDED THAT T HE PAD BE SOLDERED TO THE SYSTEM GROUND PLANE.

15 VIO 14 SDO 13 SCK 12 DIN 11 CNV

IN3

COM

07353-004

Figure 4. AD7682 LFCSP Pin Configuration

Table 7. AD7682 LFCSP and AD7689 LFCSP Pin Function Descriptions

AD7682

LFCSP

Pin No.

Mnemonic

1, 20 VDD VDD P

AD7689

LFCSP Mnemonic

Description

Typ e

Power Supply. Nominally 2.5 V to 5.5 V when using an external reference and decoupled with 10 F and 100 nF capacitors. When using the internal reference for a 2.5 V output, the minimum must be 3.0 V. When using the internal reference for 4.096 V output, the minimum must be 4.6 V.

2 REF REF AI/O

Reference Input/Output. See the Voltage Reference Output/Input section. When the internal reference is enabled, this pin produces a selectable system reference of 2.5 V or

4.096 V. When the internal reference is disabled and the buffer is enabled, REF produces a buffered version of the voltage present on the REFIN pin (VDD − 0.5 V, maximum), which is useful when using low cost, low power references. For improved drift performance, connect a precision reference to REF (0.5 V to VDD). For any reference method, this pin needs decoupling with an external 10 F capacitor connected as close to REF as possible. See the Reference Decoupling section.

3 REFIN REFIN AI/O

Internal Reference Output/Reference Buffer Input. See the Voltage Reference Output/Input section. When using the internal reference, the internal unbuffered reference voltage is present and requires decoupling with a 0.1 F capacitor. When using the internal reference buffer, apply a source between 0.5 V and (VDD − 0.5 V) that is

buffered to the REF pin, as described in the REF pin description. 4, 5 GND GND P Power Supply Ground. 6 NC IN4 AI No Connection (AD7682). Analog Input Channel 4 (AD7689). 7 IN2 IN5 AI Analog Input Channel 2 (AD7682). Analog Input Channel 5 (AD7689). 8 NC IN6 AI No Connection (AD7682). Analog Input Channel 6 (AD7689). 9 IN3 IN7 AI Analog Input Channel 3 (AD7682). Analog Input Channel 7 (AD7689). 10 COM COM AI

11 CNV CNV DI

Common Channel Input. All input channels, IN[7:0], can be referenced to a common-

mode point of 0 V or V

REF

/2 V.

Conversion Input. On the rising edge, CNV initiates the conversion. During conversion, if

CNV is held low, the busy indictor is enabled. 12 DIN DIN DI

Data Input. Use this input for writing to the 14-bit configuration register. The

configuration register can be written to during and after conversion. 13 SCK SCK DI

Serial Data Clock Input. This input is used to clock out the data on SDO and clock in data

on DIN in an MSB first fashion.

PIN 1 INDICATOR

1VDD 2REF

AD7689

3REFIN 4GND

TOP VIEW

5GND

(Not to Scale)

IN4

IN5

IN6

NOTES

1. THE EXPOSED PAD IS NOT CONNECT ED INTERNALLY. F OR INCREASED RELIABILITY OF THE SOLDER JOINTS, IT IS RECOMMENDED THAT THE PAD BE SOLDERED TO THE SYSTEM GROUND PLANE.

15 VIO 14 SDO 13 SCK 12 DIN 11 CNV

IN7

COM

Figure 5. AD7689 LFCSP Pin Configuration

07353-005

Rev. F | Page 10 of 35

Data Sheet AD7682/AD7689

AD7682

LFCSP

Pin No.

Mnemonic

14 SDO SDO DO

15 VIO VIO P

16 IN0 IN0 AI Analog Input Channel 0. 17 NC IN1 AI No Connection (AD7682). Analog Input Channel 1 (AD7689). 18 IN1 IN2 AI Analog Input Channel 1 (AD7682). Analog Input Channel 2 (AD7689). 19 NC IN3 AI No Connection (AD7682). Analog Input Channel 3 (AD7689). 21 EPAD EPAD NC

AI means analog input, AI/O means analog input/output, DI means digital input, DO means digital output, P means power, and NC means no internal connection.

AD7689

LFCSP Mnemonic Type1 Description

Serial Data Output. The conversion result is output on this pin, synchronized to SCK. In unipolar modes, conversion results are straight binary; in bipolar modes, conversion results are twos complement.

Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V, or 5 V).

Exposed Pad. The exposed pad is not connected internally. For increased reliability of the solder joints, it is recommended that the pad be soldered to the system ground plane.

Rev. F | Page 11 of 35

AD7682/AD7689 Data Sheet

987654321

NC IN1 IN0 VIOA

VDD VDD NC SDO

REF REF IN DIN S CK

GND GND IN3 CNV

NC IN2 NC COME

Figure 6. AD7682 WLCSP Pin Configuration

AD7682

987654321

REF REFIN DIN SCK

07353-105

Table 8. AD7682 WLCSP and AD7689 WLCSP Pin Function Descriptions

AD7682

WLCSP

Pin No.

Mnemonic

B6, B8 VDD VDD P

AD7689

WLCSP Mnemonic

Typ e1 Description

Power Supply. Nominally 2.5 V to 5.5 V when using an external reference and decoupled

with 10 F and 100 nF capacitors. When using the internal reference for a 2.5 V output,

the minimum must be 3.0 V. When using the internal reference for 4.096 V output, the

minimum must be 4.6 V. C9 REF REF AI/O

Reference Input/Output. See the Voltage Reference Output/Input section. When the

internal reference is enabled, this pin produces a selectable system reference of 2.5 V or

4.096 V. When the internal reference is disabled and the buffer is enabled, REF produces a

buffered version of the voltage present on the REFIN pin (VDD − 0.5 V, maximum), which

is useful when using low cost, low power references. For improved drift performance,

connect a precision reference to REF (0.5 V to VDD). For any reference method, this pin

needs decoupling with an external 10 F capacitor connected as close to REF as possible.

See the Reference Decoupling section. C7 REFIN REFIN AI/O

Internal Reference Output/Reference Buffer Input. See the Voltage Reference

Output/Input section. When using the internal reference, the internal unbuffered

reference voltage is present and requires decoupling with a 0.1 F capacitor. When using

the internal reference buffer, apply a source between 0.5 V and (VDD − 0.5 V) that is

buffered to the REF pin, as described in the REF pin description. D6, D8 GND GND P Power Supply Ground. A7 NC IN3 AI No Connection (AD7682). Analog Input Channel 3 (AD7689). E5 IN2 IN5 AI Analog Input Channel 2 (AD7682). Analog Input Channel 5 (AD7689). E3 NC IN6 AI No Connection (AD7682). Analog Input Channel 6 (AD7689). D4 IN3 IN7 AI Analog Input Channel 3 (AD7682). Analog Input Channel 7 (AD7689). E1 COM COM AI

D2 CNV CNV DI

Common Channel Input. All input channels, IN[7:0], can be referenced to a common-

mode point of 0 V or V

REF

/2 V.

Conversion Input. On the rising edge, CNV initiates the conversion. During conversion, if

CNV is held low, the busy indictor is enabled.

D7689

IN3 IN2 IN0 VIOA

VDD VDD IN1 SDO

GND GND IN7 CNV

IN4 IN5 IN6 COME

07353-106

Figure 7. AD7689 WLCSP Pin Configuration

Rev. F | Page 12 of 35

Data Sheet AD7682/AD7689

AD7682

WLCSP

Pin No.

Mnemonic

C5 DIN DIN DI

C3 SCK SCK DI

B2 SDO SDO DO

A1 VIO VIO P

A3 IN0 IN0 AI Analog Input Channel 0. B4 NC IN1 AI No connection (AD7682). Analog Input Channel 1 (AD7689). A5 IN1 IN2 AI Analog Input Channel 1 (AD7682). Analog Input Channel 2 (AD7689). E7 NC IN4 AI No Connection (AD7682). Analog Input Channel 4 (AD7689).

AI means analog input, AI/O means analog input/output, DI means digital input, DO means digital output, P means power, and NC means no internal connection.

AD7689

WLCSP Mnemonic Type1 Description

Data Input. Use this input for writing to the 14-bit configuration register. The configuration register can be written to during and after conversion.

Serial Data Clock Input. This input is used to clock out the data on SDO and clock in data on DIN in an MSB first fashion.

Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V, or 5 V).

Rev. F | Page 13 of 35

AD7682/AD7689 Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

VDD = 2.5 V to 5.5 V, V

1.5 INL MAX = +0.34 LSB INL MIN = –0.44 LSB

1.0

= 2.5 V to 5 V, VIO = 2.3 V to VDD, unless otherwise noted.

REF

1.5

1.0

DNL MAX = +0.20 LSB DNL MIN = –0.22 LSB

0.5

INL (LSB)

–0.5

–1.0

–1.5

0 16,384 32,768

CODES

Figure 8. Integral Nonlinearity vs. Code, V

49,152 65,536

REF

200k

180k

160k

140k

120k

100k

COUNTS

80k

60k

40k

20k

00487 619000

7FFB 7FFC 7FFD 7F FE 7FFF 8000 8001 8002

7FFA

135,326

124,689

CODE IN HEX

Figure 9. Histogram of a DC Input at Code Center

–20

–40

–60

–80

–100

–120

–140

AMPLIT UDE (dB of Full -Scale)

–160

–180

05025 75 100 125

Figure 10. 20 kHz FFT, V

= VDD = 5V

REF

= 250kSPS

= 19.9kHz

SNR = 92.9dB SINAD = 92.4dB THD = –102dB SFDR = 103dB SECOND HARMONIC = –111dB THIRD HARMONIC = –104d B

FREQUENCY (kHz)

= VDD = 5 V

REF

= VDD = 5 V

σ = 0.50

= VDD = 5V

REF

0.5

DNL (LSB)

–0.5

–1.0

0 16,384 32,768

07353-009

CODES

Figure 11. Differential Nonlinearity vs. Code, V

49,152 65, 536

= VDD = 5 V

REF

07353-006

160k

140k

120k

100k

80k

COUNTS

60k

40k

20k

178

7FFB 7FFC 7FFD 7FFE 7FFF 8000 8001 8002 8003

07353-007

6649

135,207

63,257

CODE IN HEX

51,778

σ = 0.78 V

= VDD = 2.5V

REF

4090

60 1

07353-010

Figure 12. Histogram of a DC Input at Code Center

–20

–40

–60

–80

–100

–120

–140

AMPLIT UDE (dB o f Ful l-Scal e)

–160

–180

05025 75 100

07353-008

Figure 13. 20 kHz FFT, V

= VDD = 2.5V

REF

= 200kSPS

= 19.9kHz

SNR = 88.0dB SINAD = 87.0dB THD = –89dB SFDR = 89dB SECOND HARMO NIC = –105dB THIRD HARMO NIC = –90dB

FREQUENCY (kHz)

= VDD = 2.5 V

REF

07353-011

Rev. F | Page 14 of 35

Data Sheet AD7682/AD7689

–

100

SNR (dB)

= VDD = 5V, –0.5dB

0 50 100 150 200

REF

= VDD = 5V, –10dB

REF

= VDD = 2.5V, –0. 5dB

REF

= VDD = 2.5V, –10d B

REF

FREQUENCY (kHz)

Figure 14. SNR vs. Frequency

SNR @ 2kHz

SNR, SINAD (dB)

1.0

SINAD @ 2kHz SNR @ 20kHz SINAD @ 20kHz ENOB @ 2kHz ENOB @ 20kHz

1.5 2.0 2. 5 3.0 3.5 4.0 4.5 5.0

REFERENCE VOLTAGE (V)

Figure 15. SNR, SINAD, and ENOB vs. Reference Voltage

= 20kHz

SNR (dB)

REF

= VDD = 2.5V

REF

= VDD = 5V

5.5

17.0

16.5

16.0

15.5

15.0

14.5

14.0

13.5

13.0

SINAD (dB)

= VDD = 5V, –0.5dB

0 50 100 150 200

07353-041

REF

= VDD = 5V, –10dB

REF

= VDD = 2.5V, –0. 5dB

REF

= VDD = 2.5V, –10d B

REF

FREQUENCY (kHz)

07353-012

Figure 17. SINAD vs. Frequency

130

125

120

115

110

105

100

ENOB (Bits)

07353-013

SFDR (dB)

1.0

1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

SFDR = 2kHz

SFDR = 20kHz

THD = 20kHz

THD = 2kHz

REFERENCE VOLTAGE (V)

–65

–70

–75

–80

–85

–90

–95

–100

–105

–110

–115

–120

THD (dB)

07353-016

Figure 18. SFDR and THD vs. Reference Voltage

= 20kHz

–95

= VDD = 5V

REF

= VDD = 2.5V

–100

THD (dB)

–105

REF

–35 –15 5 25 45 65 85 105

–55

TEMPERATURE (°C)

Figure 16. SNR vs. Temperature

125

07353-014

–110

–35 –15 5 25 45 65 85 105

–55

TEMPERAT URE (°C)

Figure 19. THD vs. Temperature

125

07353-017

Rev. F | Page 15 of 35

AD7682/AD7689 Data Sheet

–

–70

–80

3000

2750

2500

2250

2.5V INTERN AL REF

4.096V INT ERNAL REF INTERN AL BUFFER, TEMP ON INTERN AL BUFFER, TEMP OFF EXTERNAL REF, T EMP ON EXTERNAL REF, T EMP OFF VIO

= 200kSPS

100

–90

THD (dB)

–100

= VDD = 5V, –0.5dB

–110

–120

0 50 100 150 200

FREQUENCY (kHz)

REF

= VDD = 2. 5V, –0.5d B

REF

= VDD = 2. 5V, –10dB

REF

= VDD = 5V, –10dB

REF

Figure 20. THD vs. Frequency

= 20kHz

= VDD = 5V

SNR (dB)

–10

–8 –6 –2 0–4

REF

= VDD = 2.5V

REF

INPUT LEVEL (dB)

Figure 21. SNR vs. Input Level

2000

1750

VDD CURRENT (µ A)

1500

1250

1000

2.5 3. 0 3.5 4.0 4.5 5.0 5.5

07353-015

VDD SUPPLY (V)

VIO CURRENT (µA)

07353-021

Figure 23. Operating Currents vs. Supply

3000

= 200kSPS

2750

2500

2250

2000

1750

VDD CURRENT (µA)

1500

1250

1000

07353-018

VDD = 5V, I NTERNAL 4.096V REF

VDD = 5V, EXT ERNAL REF

VDD = 2.5, EXTERNAL REF

VIO

–55

–35–155 25456585105

TEMPERATURE (°C)

125

180

160

140

120

100

VIO CURRENT (µA)

07353-022

Figure 24. Operating Currents vs. Temperature

–1

UNIPOLAR ZERO

–2

OFFSET ERROR AND GAIN ERROR (LSB)

–3

UNIPOLAR GAIN BIPOLAR ZERO BIPOLAR GAIN

–55

–35 –15 5 25 45 65 85 105

TEMPERAT URE (°C)

Figure 22. Offset and Gain Errors vs. Temperature

125

VDD = 2.5V, 25°C

DELAY (ns)

DSDO

VDD = 3.3V, 25°C

07353-020

Figure 25. t

DSDO

VDD = 2.5V, 85°C

VDD = 5V, 85°C

VDD = 3.3V, 85°C

SDO CAPACI TIVE LOAD (pF)

VDD = 5V, 25°C

Delay vs. SDO Capacitance Load and Supply

1200 20406080100

07353-023

Rev. F | Page 16 of 35

Data Sheet AD7682/AD7689

TERMINOLOGY

Least Significant Bit (LSB)

The LSB is the smallest increment represented by a converter. For an ADC with N bits of resolution, the LSB expressed in volts is

REF

LSB2(V) 

Integral Nonlinearity Error (INL)

INL refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line (see Figure 27).

Differential Nonlinearity Error (DNL)

In an ideal ADC, code transitions are 1 LSB apart. DNL is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed.

Offset Error

The first transition must occur at a level ½ LSB above analog ground. The offset error is the deviation of the actual transition from that point.

Gain Error

The last transition (from 111…10 to 111…11) must occur for an analog voltage 1½ LSB below the nominal full scale. The gain error is the deviation in LSB (or percentage of full-scale range) of the actual level of the last transition from the ideal level after the offset error is adjusted out. Closely related is the full-scale error (also in LSB or percentage of full-scale range), which includes the effects of the offset error.

Aperture Delay

Aperture delay is the measure of the acquisition performance. It is the time between the rising edge of the CNV input and the point at which the input signal is held for a conversion.

Transi e n t R e sp o n s e

Transient response is the time required for the ADC to accurately acquire its input after a full-scale step function is applied.

Dynamic Range

Dynamic range is the ratio of the rms value of the full scale to the total rms noise measured with the inputs shorted together. The value for dynamic range is expressed in decibels.

Signal-to-Noise Ratio (SNR)

SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels.

Signal-to-(Noise + Distortion) Ratio (SINAD)

SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in decibels.

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels.

Spurious-Free Dynamic Range (SFDR)

SFDR is the difference, in decibels, between the rms amplitude of the input signal and the peak spurious signal.

Effective Number of Bits (ENOB)

ENOB is a measurement of the resolution with a sine wave input. It is related to SINAD by the formula

ENOB = (SINAD

− 1.76)/6.02

and is expressed in bits.

Channel-to-Channel Crosstalk

Channel-to-channel crosstalk is a measure of the level of crosstalk between any two adjacent channels. It is measured by applying a dc to the channel under test and applying a full-scale, 100 kHz sine wave signal to the adjacent channel(s). The crosstalk is the amount of signal that leaks into the test channel, and is expressed in decibels.

Reference Voltage Temperature Coefficient

Reference voltage temperature coefficient is derived from the typical shift of output voltage at 25°C on a sample of parts at the maximum and minimum reference output voltage (V at T

, T (25°C), and T

MIN

TCV

REF

. It is expressed in ppm/°C as

MAX

MinVMaxV

)Cppm/( 



REF

REFREF

MAX

TTC25V



)(–)(

MIN

) measured

REF

)–()(

where:

(Max) = maximum V

REF

(Min) = minimum V

REF

(25°C) = V

REF

MAX

MIN

= +85°C.

= –40°C.

REF

at 25°C.

REF

at T

MIN

, T (25°C), or T

MAX

Rev. F | Page 17 of 35

AD7682/AD7689 Data Sheet

THEORY OF OPERATION

INx+

SWITCHES CONTRO L

LSB

SW+MSB

REF

GND

INx– OR

COM

16,384C

4C 2C C C32,768C

Figure 26. ADC Simplified Schematic

LSB

SW–MSB

COMP

CONTROL

LOGIC

CNV

BUSY

OUTPUT CODE

07353-026

OVERVIEW

The AD7682/AD7689 are 4-channel/8-channel, 16-bit, charge redistribution SAR ADCs. These devices are capable of converting 250,000 samples per second (250 kSPS) and power down between conversions. For example, when operating with an external reference at 1 kSPS, they consume 17 µW typically, ideal for battery-powered applications.

The AD7682/AD7689 contain all of the components for use in a multichannel, low power data acquisition system, including

 16-bit SAR ADC with no missing codes  4-channel/8-channel, low crosstalk multiplexer  Internal low drift reference and buffer  Temperature sensor  Selectable one-pole filter  Channel sequencer

These components are configured through an SPI-compatible, 14-bit register. Conversion results, also SPI compatible, can be read after or during conversions with the option for reading back the configuration associated with the conversion.

The AD7682/AD7689 provide the user with an on-chip trackand-hold and do not exhibit pipeline delay or latency.

The AD7682/AD7689 are specified from 2.3 V to 5.5 V and can be interfaced to any 1.8 V to 5 V digital logic family. They are housed in a 20-lead, 4 mm × 4 mm LFCSP and a 20-lead,

2.4 mm × 2.4 mm WLCSP that combine space savings and allow flexible configurations. They are pin-for-pin compatible with the 16-bit AD7699 and 14-bit AD7949.

CONVERTER OPERATION

The AD7682/AD7689 are successive approximation ADCs based on a charge redistribution DAC. Figure 26 shows the simplified schematic of the ADC. The capacitive DAC consists of two identical arrays of 16 binary weighted capacitors, which are connected to the two comparator inputs.

During the acquisition phase, terminals of the array tied to the comparator input are connected to GND via SW+ and SW−. All independent switches are connected to the analog inputs.

The capacitor arrays are used as sampling capacitors and acquire the analog signal on the INx+ and INx− (or COM) inputs. When the acquisition phase is complete and the CNV input goes high, a conversion phase is initiated. When the conversion phase begins, SW+ and SW− open first. The two capacitor arrays are then disconnected from the inputs and connected to the GND input. Therefore, the differential voltage between the INx+ and INx− (or COM) inputs captured at the end of the acquisition phase applies to the comparator inputs, causing the comparator to become unbalanced. By switching each element of the capacitor array between GND and REF, the comparator input varies by binary weighted voltage steps (V

/2, V

REF

/4...V

REF

switches, starting with the MSB, to bring the comparator back into a balanced condition. After the completion of this process, the device returns to the acquisition phase, and the control logic generates the ADC output code and a busy signal indicator.

Because the AD7682/AD7689 have an on-board conversion clock, the serial clock, SCK, is not required for the conversion process.

/32,768). The control logic toggles these

REF

Rev. F | Page 18 of 35

Data Sheet AD7682/AD7689

TRANSFER FUNCTIONS

With the inputs configured for unipolar range (single-ended, COM with ground sense, or paired differentially with INx− as ground sense), the data output is straight binary.

With the inputs configured for bipolar range (COM = V paired differentially with INx− = V

/2), the data outputs are

REF

twos complement. The ideal transfer characteristic for the AD7682/AD7689 is

shown in Figure 27 and for both unipolar and bipolar ranges with the internal 4.096 V reference.

REF

/2 or

TWOS

COMPLEMENT

011...111

011...110

011...101

ADC CODE

100...010

100...001

100...000

STRAIGHT

BINARY

111...111

111...110

111...101

000...010

000...001

000...000 –FSR

–FSR + 1LSB

–FSR + 0.5LSB

ANALOG I NPUT

Figure 27. ADC Ideal Transfer Function

+FSR – 1.5LSB

+FSR – 1LSB

07353-027

Table 9. Output Codes and Ideal Input Voltages

Description

Unipolar Analog Input

= 4.096 V

REF

Digital Output Code (Straight Binary Hex)

Bipolar Analog Input

= 4.096 V

REF

Digital Output Code (Twos Complement Hex)

FSR − 1 LSB 4.095938 V 0xFFFF3 2.047938 V 0x7FFF3 Midscale + 1 LSB 2.048063 V 0x8001 62.5 V 0x0001 Midscale 2.048 V 0x8000 0 V 0x0000 Midscale − 1 LSB 2.047938 V 0x7FFF −62.5 V 0xFFFF

−FSR + 1 LSB 62.5 V 0x0001 −2.047938 V 0x8001

−FSR 0 V 0x0000

With COM or INx− = 0 V or all INx referenced to GND.

With COM or INx− = V

This is also the code for an overranged analog input ((INx+) − (INx−), or COM, above V

This is also the code for an underranged analog input ((INx+) − (INx−), or COM, below GND).

/2.

REF

− GND).

REF

−2.048 V 0x80004

Rev. F | Page 19 of 35

AD7682/AD7689 Data Sheet

TYPICAL CONNECTION DIAGRAMS

1.8V TO VDD

GND

VDD

100nF

VIO

DIN MOSI

SCK

SDO

CNV

SCK

MISO

07353-028

100nF

10µF

IN0

IN[7:1]

COM

REF

REFIN

AD7689

V+

0V TO

REF

0V TO

REF

0V OR V

REF

NOTES

1. INTERNAL REFERENCE SHOWN. SEE VOLTAGE REFERENCE OUTPUT/INPUT SECTION FOR REFERENCE SELECTION.

2. C

IS USUALLY A 10µF CERAMIC CAPACITOR (X5R).

REF

3. SEE THE DRIVER AMPLIFIER CHOICE SECTION FOR ADDITIONAL RECOMMENDED AMPLIFIERS.

4. SEE THE DIGITAL INTERFACE SECTION FOR CONFIGURING AND READING CONVERSION DATA.

ADA4805-1/ ADA4807-1

V–

V+

ADA4805-1/ ADA4807-1

V–

Figure 28. Typical Application Diagram with Multiple Supplies

1.8V TO VDD

100nF

VIO

DIN MOSI

SCK

SDO

CNV

SCK

MISO

V+

ADA4805-1/ ADA4807-1

V–

V+

ADA4805-1/ ADA4807-1

V–

10µF

+5V

REF

IN0

IN[7:1]

100nF

REFIN

AD7689

100nF

VDD

p-p

REF

NOTES

1. INTERNAL REFERENCE SHOWN. SEE VOLTAGE REFERENCE OUTPUT/INPUT SECTION FOR REFERENCE SELECTION.

2. C

IS USUALLY A 10µF CERAMIC CAPACITOR (X5R).

REF

3. SEE THE DRIVER AMPLIFIER CHOICE SECTION FOR ADDITIONAL RECOMMENDED AMPLIFIERS.

4. SEE THE DIGITAL INTERFACE SECTION FOR CONFIGURING AND READING CON VERSION DATA.

COM

GND

07353-029

Figure 29. Typical Application Diagram Using Bipolar Input

Rev. F | Page 20 of 35

Data Sheet AD7682/AD7689

Unipolar or Bipolar

Figure 28 shows an example of the recommended connection diagram for the AD7682/AD7689 when multiple supplies are available.

Bipolar Single Supply

Figure 29 shows an example of a system with a bipolar input using single supplies with the internal reference (optional different VIO supply). This circuit is also useful when the amplifier/signal conditioning circuit is remotely located with some common mode present. Note that for any input configuration, the INx inputs are unipolar and are always referenced to GND (no negative voltages even in bipolar range).

For this circuit, a rail-to-rail input/output amplifier can be used; however, take the offset voltage vs. input common-mode range into consideration (1 LSB = 62.5 V with V

= 4.096 V). Note

REF

that the conversion results are in twos complement format when using the bipolar input configuration. Refer to the

AN-581 Application Note, Biasing and Decoupling Op Amps in

Single Supply Applications, for additional details about using single-supply amplifiers.

ANALOG INPUTS

Input Structure

Figure 30 shows an equivalent circuit of the input structure of the AD7682/AD7689. The two diodes, D1 and D2, provide ESD protection for the analog inputs, IN[7:0] and COM. Care must be taken to ensure that the analog input signal does not exceed the supply rails by more than 0.3 V because this causes the diodes to become forward biased and to start conducting current.

These diodes can handle a maximum forward-biased current of 130 mA. For instance, these conditions may eventually occur when the input buffer supplies are different from VDD. In such a case, for example, an input buffer with a short circuit, the current limitation can be used to protect the device.

CMRR (dB)

Figure 31. Analog Input CMRR vs. Frequency

100

FREQUENCY (kHz)

10k10

07353-031

During the acquisition phase, the impedance of the analog inputs can be modeled as a parallel combination of the capacitor, CPIN, and the network formed by the series connection of RIN and CIN. CPIN is primarily the pin capacitance. RIN is typically

2.2 kΩ and is a lumped component composed of serial resistors and the on resistance ofthe switches. CIN is typically 27 pF and is mainly the ADC sampling capacitor.

Selectable Low-Pass Filter

During the conversion phase, when the switches are opened, the input impedance is limited to C are acquiring, R

and CIN make a one-pole, low-pass filter that

. While the AD7682/AD7689

reduces undesirable aliasing effects and limits the noise from the driving circuitry. The low-pass filter can be programmed for the full bandwidth or ¼ of the bandwidth with CFG[6], as shown in Table 11. This setting changes R

to 19 kΩ. Note that

the converter throughput must also be reduced by ¼ when using the filter. If the maximum throughput is used with the bandwidth (BW) set to ¼, the converter acquisition time, t

ACQ

is violated, resulting in increased THD.

INx+

OR INx–

OR COM

GND

Figure 30. Equivalent Analog Input Circuit

07353-030

This analog input structure allows the sampling of the true differential signal between INx+ and COM or INx+ and INx−. (COM or INx− = GND ± 0.1 V or V

± 0.1 V). By using these

REF

differential inputs, signals common to both inputs are rejected, as shown in Figure 31.

Rev. F | Page 21 of 35

AD7682/AD7689 Data Sheet

Input Configurations

Figure 32 shows the different methods for configuring the analog inputs with the configuration register, CFG[12:10]. Refer to the Configuration Register, CFG, section for more details.

The analog inputs can be configured as shown in

 Figure 32 (A), single-ended referenced to system ground;

CFG[12:10] = 111 (IN[7:0]) have a range of GND to V

. In this configuration, all inputs

REF

 Figure 32 (B), bipolar differential with a common reference

point; COM = V

/2; CFG[12:10] = 0102. Unipolar

REF

differential with COM connected to a ground sense; CFG[12:10] = 110 have a range of GND to V

. In this configuration, all inputs IN[7:0]

REF

 Figure 32 (C), bipolar differential pairs with the negative

input channel referenced to V

/2; CFG[12:10] = 00X2.

REF

Unipolar differential pairs with the negative input channel referenced to a ground sense; CFG[12:10] = 10X

. In these

configurations, the positive input channels have the range of GND to V referred to V

. The negative input channels are a sense

REF

/2 for bipolar pairs, or GND for unipolar

REF

pairs. The positive channel is configured with CFG[9:7]. If CFG[9:7] is even, then IN0, IN2, IN4, and IN6 are used. If CFG[9:7] is odd, then IN1, IN3, IN5, and IN7 are used, as indicated by the channels with parentheses in Figure 32 (C). For example, for IN0/IN1 pairs with the positive channel on IN0, CFG[9:7] = 000 positive channel on IN5, CFG[9:7] = 101

. For IN4/IN5 pairs with the

. Note that for the

sequencer, detailed in the Channel Sequencer section, the positive channels are always IN0, IN2, IN4, and IN6.

 Figure 32 (D), inputs configured in any of the preceding

combinations (showing that the AD7682/AD7689 can be configured dynamically).

CH0+

CH1+

CH2+

CH3+

CH4+

CH5+

CH6+

CH7+

CH0+ (–)

CH0– (+)

CH1+ (–)

CH1– (+)

CH2+ (–)

CH2– (+)

CH3+ (–)

CH3– (+)

IN0

IN1

IN2

IN3

IN4

IN5

IN6

IN7

COM

GND

A—8 CHANNELS,

SINGLE ENDED

IN0

IN1

IN2

IN3

IN4

IN5

IN6

IN7

COM

GND

C—4 CHANNELS,

DIFFERE NTIAL

CH0+

CH1+

CH2+

CH3+

CH4+

CH5+

CH6+

CH7+

COM–

B—8 CHANNELS,

COMMON REFERNCE

CH0+ (–)

CH0– (+)

CH1+ (–)

CH1– (+)

CH2+

CH3+

CH4+

CH5+

COM–

D—COMBINATION

IN0

IN1

IN2

IN3

IN4

IN5

IN6

IN7

COM

GND

IN0

IN1

IN2

IN3

IN4

IN5

IN6

IN7

COM

GND

07353-032

Figure 32. Multiplexed Analog Input Configurations

Sequencer

The AD7682/AD7689 include a channel sequencer useful for scanning channels in a repeated fashion. Refer to the Channel Sequencer section for further details on the sequencer operation.

Source Resistance

When the source impedance of the driving circuit is low, the

AD7682/AD7689 can be driven directly. Large source imped-

ances significantly affect the ac performance, especially THD. The dc performances are less sensitive to the input impedance. The maximum source impedance depends on the amount of THD that can be tolerated. The THD degrades as a function of the source impedance and the maximum input frequency.

Rev. F | Page 22 of 35

Data Sheet AD7682/AD7689

DRIVER AMPLIFIER CHOICE

Although the AD7682/AD7689 are easy to drive, the driver amplifier must meet the following requirements:

 The noise generated by the driver amplifier must be kept as

low as possible to preserve the SNR and transition noise performance of the AD7682/AD7689. Note that the

AD7682/AD7689 have a noise much lower than most other

16-bit ADCs and, therefore, can be driven by a noisier amplifier to meet a given system noise specification. The noise from the amplifier is filtered by the AD7682/AD7689 analog input circuit low-pass filter made by R by an external filter, if one is used. Because the typical noise of the AD7682/AD7689 is 35 µV rms (with V 5 V), the SNR degradation due to the amplifier is



SNR

LOSS







log20



 



Nef

3dB



where:

is the input bandwidth in megahertz of the AD7682/

–3dB

AD7689 (1.7 MHz in full BW or 425 kHz in ¼ BW), or the

cutoff frequency of an input filter, if one is used. N is the noise gain of the amplifier (for example, 1 in buffer configuration).

is the equivalent input noise voltage of the op amp, in

nV/√Hz.

 For ac applications, the driver must have a THD

performance commensurate with the AD7682/AD7689. Figure 20 shows THD vs. frequency for the AD7682/

AD7689.

 For multichannel, multiplexed applications on each input

or input pair, the driver amplifier and the AD7682/

AD7689 analog input circuit must settle a full-scale step

onto the capacitor array at a 16-bit level (0.0015%). In amplifier data sheets, settling at 0.1% to 0.01% is more commonly specified. This may differ significantly from the settling time at a 16-bit level and must be verified prior to driver selection.

Table 10. Recommended Driver Amplifiers

Amplifier Typical Application

ADA4805-1 Low noise, small size, and low power ADA4807-1 Very low noise and high frequency ADA4627-1 Precision, low noise, and low input bias ADA4522-1 Precision, zero drift, and EMI enhanced ADA4500-2

Precision, rail-to-rail input/output, and zero input crossover distortion

 

 

)(

 

and CIN, or

REF

VOLTAGE REFERENCE OUTPUT/INPUT

The AD7682/AD7689 allow the choice of a very low temperature drift internal voltage reference, an external reference, or an external buffered reference.

The internal reference of the AD7682/AD7689 provide excellent performance and can be used in almost all applications. There are six possible choices of voltage reference schemes, briefly described in Table 11, with more details in each of the following sections.

Internal Reference/Temperature Sensor

The precision internal reference, suitable for most applications, can be set for either a 2.5 V or a 4.096 V output, as detailed in Table 11. With the internal reference enabled, the band gap voltage is also present on the REFIN pin, which requires an external 0.1 F capacitor. Because the current output of REFIN is limited, it can be used as a source if followed by a suitable buffer, such as the AD8605. Note that the voltage of REFIN changes depending on the 2.5 V or 4.096 V internal reference.

Enabling the reference also enables the internal temperature sensor, which measures the internal temperature of the AD7682/

AD7689, and is therefore useful for performing a system

calibration. For applications requiring the use of the temperature sensor, the internal reference must be active (internal buffer can be disabled in this case). Note that, when using the temperature sensor, the output is straight binary referenced from the

AD7682/AD7689 GND pin.

The internal reference is temperature compensated to within 10 mV. The reference is trimmed to provide a typical drift of ±10 ppm/°C.

Connect the AD7682/AD7689 as shown in Figure 33 for either a 2.5 V or 4.096 V internal reference.

10µF

AD7682/ AD7689

Figure 33. 2.5 V or 4.096 V Internal Reference Connection

REF

TEMP

GND

100nF

REFIN

07353-049

Rev. F | Page 23 of 35

AD7682/AD7689 Data Sheet

External Reference and Internal Buffer

For improved drift performance, an external reference can be used with the internal buffer, as shown in Figure 34. The external source is connected to REFIN, the input to the on-chip unity-gain buffer, and the output is produced on the REF pin. An external reference can be used with the internal buffer with or without the temperature sensor enabled. Refer to Table 11 for register details. With the buffer enabled, the gain is unity and is limited to an input/output of VDD = −0.2 V; however, the maximum voltage allowable must be ≤(VDD − 0.5 V).

The internal reference buffer is useful in multiconverter applications because a buffer is typically required in these applications. In addition, a low power reference can be used because the internal buffer provides the necessary performance to drive the SAR architecture of the AD7682/AD7689.

REF SOURCE

≤ (VDD – 0.5V)

10µF 100nF

REF

REFIN

AD7682/ AD7689

Figure 34. External Reference Using Internal Buffer

TEMP

GND

07353-132

External Reference

In any of the six voltage reference schemes, an external reference can be connected directly on the REF pin as shown in Figure 35 because the output impedance of REF is >5 k. To reduce power consumption, power down the reference and buffer. Refer to Table 11 for register details. For improved drift performance, an external reference from the family of devices that includes the ADR430, ADR431, ADR433, ADR434, and

ADR435, or the family of devices that includes the ADR440, ADR441, ADR443, ADR444, and ADR445 is recommended.

REF SOURCE

10µF

AD7682/ AD7689

Figure 35.External Reference

0.5V < REF < (VDD + 0.3V)

NO CONNECTIO N REQUIRED

REF

REFIN

TEMP

GND

07353-047

Note that the best SNR is achieved with a 5 V external reference as the internal reference is limited to 4.096 V. The SNR degradation is as follows:

096.4

SNR

LOSS

log20

Reference Decoupling

Whether using an internal or external reference, the AD7682/

AD7689 voltage reference output/input, REF, has a dynamic

input impedance and must be driven by a low impedance source with efficient decoupling between the REF and GND pins. This decoupling depends on the choice of the voltage reference but usually consists of a low ESR capacitor connected to REF and GND with minimum parasitic inductance. A 10 µF (X5R, 1206 size) ceramic chip capacitor is appropriate when using the internal reference, a member of the ADR430, ADR431,

ADR433, ADR434, and ADR435 family of external references,

a member of the ADR440, ADR441, ADR443, ADR444, and

ADR445 family of external references, or a low impedance buffer

such as the AD8031 or the AD8605. The placement of the reference decoupling capacitor is also

important to the performance of the AD7682/AD7689, as explained in the Layout section. Mount the decoupling capacitor with a thick PCB trace on the same side as the ADC at the REF pin. The GND must also connect to the reference decoupling capacitor with the shortest distance and to the analog ground plane with several vias.

If desired, smaller reference decoupling capacitor values down to 2.2 µF can be used with a minimal impact on performance, especially on DNL.

Regardless, there is no need for an additional lower value ceramic decoupling capacitor (for example, 100 nF) between the REF and GND pins.

For applications that use multiple AD7682/AD7689 devices or other PulSAR devices, it is more effective to use the internal reference buffer to buffer the external reference voltage, thus reducing SAR conversion crosstalk.

The voltage reference temperature coefficient (TC) directly impacts full scale; therefore, in applications where full-scale accuracy matters, care must be taken with the TC. For instance, a ±10 ppm/°C TC of the reference changes full scale by ±1 LSB/°C.

Rev. F | Page 24 of 35

Data Sheet AD7682/AD7689

POWER SUPPLY

The AD7682/AD7689 use two power supply pins: an analog and digital core supply (VDD), and a digital input/output interface supply (VIO). VIO allows direct interface with any logic between 1.8 V and VDD. To reduce the supplies needed, the VIO and VDD pins can be tied together. The AD7682/AD7689 are independent of power supply sequencing between VIO and VDD. Additionally, they are very insensitive to power supply variations over a wide frequency range, as shown in Figure 36.

PSSR (dB)

100

FREQUENCY (kHz)

Figure 36. PSRR vs. Frequency

The AD7682/AD7689 power down automatically at the end of each conversion phase; therefore, the operating currents and power scale linearly with the sampling rate. This makes the device ideal for low sampling rates (even of a few hertz), and low battery-powered applications.

10,000

10k10

07353-034

SUPPLYING THE ADC FROM THE REFERENCE

For simplified applications, the AD7682/AD7689, with their low operating current, can be supplied directly using an external reference circuit like the one shown in Figure 38. The reference line can be driven by

 The system power supply directly.  A reference voltage with enough current output capability,

such as the ADR430, ADR431, ADR433, ADR434, ADR435,

ADR440, ADR441, ADR443, ADR444, or ADR445.

 A reference buffer, such as the AD8605, which can also

filter the system power supply, as shown in Figure 38.

10kΩ

1µF

OPTIO NAL REFERENCE BUF FERAND FIL TER.

AD8605

Figure 38. Example of an Application Circuit

10Ω

1µF

10µF

0.1µF

VIOREF VDD

AD7689

7353-035

VDD = 5V, I NTERNAL REF

1000

100

0.1

OPERATING CURRENT (µA)

0.010

0.001

VDD = 5V, EXTERNAL REF

VDD = 2.5V, EXTE RNAL REF

1k 10k

SAMPLING RATE (SPS)

VIO

100k

1M100

07353-040

Figure 37. Operating Currents vs. Sampling Rate

Rev. F | Page 25 of 35

AD7682/AD7689 Data Sheet

DIGITAL INTERFACE

The AD7682/AD7689 use a simple 4-wire interface and are compatible with SPI, MICROWIRE™, QSPI™, digital hosts, and DSPs (for example, Blackfin® ADSP-BF53x, SHARC®, ADSP219x, and ADSP-218x).

The interface uses the CNV, DIN, SCK, and SDO signals and allows CNV, which initiates the conversion, to be independent of the readback timing. This is useful in low jitter sampling or simultaneous sampling applications.

A 14-bit register, CFG[13:0], is used to configure the ADC for the channel to be converted, the reference selection, and other components, which are detailed in the Configuration Register, CFG, section.

When CNV is low, reading/writing can occur during conversion, acquisition, and spanning conversion (acquisition plus conversion). The CFG word is updated on the first 14 SCK rising edges, and conversion results are output on the first 15 (or 16, if busy mode is selected) SCK falling edges. If the CFG readback is enabled, an additional 14 SCK falling edges are required to output the CFG word associated with the conversion results with the CFG MSB following the LSB of the conversion result.

A discontinuous SCK is recommended because the device is selected with CNV low, and SCK activity begins to write a new configuration word and clock out data.

The timing diagrams indicate digital activity (SCK, CNV, DIN, and SDO) during the conversion. However, due to the possibility of performance degradation, digital activity occurs only prior to the safe data reading/writing time, t

DATA

, because the AD7682/AD7689 provide error correction circuitry that can correct for an incorrect bit during this time. From t

DATA

to t

CONV

there is no error correction, and conversion results may be corrupted. Configure the AD7682/AD7689 and initiate the busy indicator (if desired) prior to t

. It is also possible to corrupt

DATA

the sample by having SCK or DIN transitions near the sampling instant. Therefore, it is recommended to keep the digital pins quiet for approximately 20 ns before and 10 ns after the rising edge of CNV, using a discontinuous SCK whenever possible to avoid any potential performance degradation.

READING/WRITING DURING CONVERSION, FAST HOSTS

When reading/writing during conversion (n), conversion results are for the previous (n − 1) conversion, and writing the CFG register is for the next (n + 1) acquisition and conversion.

After the CNV is brought high to initiate conversion, it must be brought low again to allow reading/writing during conversion. Reading/writing must only occur up to t time is limited, the host must use a fast SCK.

and, because this

DATA

The SCK frequency required is calculated by

EdgesSCKNumber



SCK

The time between t

DATA

and t

CONV

is a safe time when digital

activity must not occur, or sensitive bit decisions may be corrupt.

READING/WRITING AFTER CONVERSION, ANY SPEED HOSTS

When reading/writing after conversion, or during acquisition (n), conversion results are for the previous (n − 1) conversion, and writing is for the (n + 1) acquisition.

For the maximum throughput, the only time restriction is that the reading/writing take place during the t

(minimum) time.

ACQ

For slow throughputs, the time restriction is dictated by the throughput required by the user, and the host is free to run at any speed. Thus for slow hosts, data access must take place during the acquisition phase.

READING/WRITING SPANNING CONVERSION, ANY SPEED HOST

When reading/writing spanning conversion, the data access starts at the current acquisition (n) and spans into the conversion (n). Conversion results are for the previous (n − 1) conversion, and writing the CFG register is for the next (n + 1) acquisition and conversion.

Similar to reading/writing during conversion, reading/writing must only occur up to t

. For the maximum throughput, the

DATA

only time restriction is that reading/writing take place during the t

+ t

DATA

time.

ACQ

For slow throughputs, the time restriction is dictated by the required throughput, and the host is free to run at any speed. Similar to reading/writing during acquisition, for slow hosts, the data access must take place during the acquisition phase with additional time into the conversion.

Data access spanning conversion requires the CNV to be driven high to initiate a new conversion, and data access is not allowed when CNV is high. Therefore, the host must perform two bursts of data access when using this method.

CONFIGURATION REGISTER, CFG

The AD7682/AD7689 use a 14-bit configuration register (CFG[13:0]), as detailed in Table 11, to configure the inputs, the channel to be converted, the one-pole filter bandwidth, the reference, and the channel sequencer. The CFG register is latched (MSB first) on DIN with 14 SCK rising edges. The CFG update is edge dependent, allowing for asynchronous or synchronous hosts.

Rev. F | Page 26 of 35

Data Sheet AD7682/AD7689

The register can be written to during conversion, during acquisition, or spanning acquisition/conversion, and is updated at the end of conversion, t

(maximum). There is always a

CONV

one deep delay when writing the CFG register. At power-up, the CFG register is undefined and two dummy conversions are required to update the register. To preload the CFG register with a factory setting, hold DIN high for two conversions (CFG[13:0] = 0x3FFF). This sets the AD7682/AD7689 for the following:

13 12 11 10 9 8 7 6 5 4 3 2 1 0

CFG INCC INCC INCC INx INx INx BW REF REF REF SEQ SEQ RB

Table 11. Configuration Register Description

Bit(s) Name Description

[13] CFG Configuration update. 0 = keep current configuration settings. 1 = overwrite contents of register. [12:10] INCC Input channel configuration. Selection of pseudo bipolar, pseudo differential, pairs, single-ended, or temperature sensor. Refer

0 0 X1 Bipolar differential pairs; INx− referenced to V 0 1 0 Bipolar; INx referenced to COM = V 0 1 1 Temperature sensor. 1 0 X1 Unipolar differential pairs; INx− referenced to GND ± 0.1 V. 1 1 0 Unipolar, INx referenced to COM = GND ± 0.1 V.

[9:7] INx Input channel selection in binary fashion.

[6] BW Select bandwidth for low-pass filter. Refer to the Selectable Low-Pass Filter section. 0 = ¼ of BW, uses an additional series resistor to further bandwidth limit the noise. Maximum throughput must be reduced to ¼. 1 = full BW. [5:3] REF

0 0 0 Internal reference, REF = 2.5 V output, temperature enabled. 0 0 1 Internal reference, REF = 4.096 V output, temperature enabled. 0 1 0 External reference, temperature enabled. 0 1 1 External reference, internal buffer, temperature enabled. 1 1 0 External reference, temperature disabled.

[2:1] SEQ Channel sequencer. Allows for scanning channels in an IN0 to IN[7:0] fashion. Refer to the Channel Sequencer section.

0 0 Disable sequencer. 0 1 Update configuration during sequence. 1 0 Scan IN0 to IN[7:0] (set in CFG[9:7]), then temperature.

[0] RB Read back the CFG register. 0 = read back current configuration at end of data. 1 = do not read back contents of configuration.

X means don’t care.

to the Input Configurations section. Bit 12 Bit 11 Bit 10 Function

1 1 1

Unipolar, INx referenced to GND.

AD7682 AD7689

Bit 9 Bit 8 Bit 7 Channel Bit 9 Bit 8 Bit 7 Channel

0 0 IN0 0 0 0 IN0

0 1 IN1 0 0 1 IN1

1 0 IN2 … … … …

1 1 IN3 1 1 1 IN7

Reference/buffer selection. Selection of internal, external, external buffered, and enabling of the on-chip temperature sensor. Refer to the Voltage Reference Output/Input section.

Bit 5 Bit 4 Bit 3 Function

1 1 1 External reference, internal buffer, temperature disabled.

Bit 2 Bit 1 Function

1 1 Scan IN0 to IN[7:0] (set in CFG[9:7]).

 IN[7:0] unipolar referenced to GND, sequenced in order.  Full bandwidth for a one-pole filter.  Internal reference/temperature sensor disabled, buffer

enabled.

 Enables the internal sequencer.  No readback of the CFG register.

Table 11 summarizes the configuration register bit details. See the Theory of Operation section for more details.

/2 ± 0.1 V.

REF

/2 ± 0.1 V.

REF

Rev. F | Page 27 of 35

AD7682/AD7689 Data Sheet

GENERAL TIMING WITHOUT A BUSY INDICATOR

Figure 39 details the timing for all three modes: read/write during conversion (RDC), read/write after conversion (RAC), and read/write spanning conversion (RSC). Note that the gating item for both CFG and data readback is at the end of conversion (EOC). At EOC, if CNV is high, the busy indicator is disabled.

As detailed in the Digital Interface section, the data access must occur up to safe data reading/writing time, t word is not written to prior to EOC, it is discarded and the current configuration remains. If the conversion result is not read out fully prior to EOC, it is lost as the ADC updates SDO with the MSB of the current conversion. For detailed timing, refer to Figure 42 and Figure 43, which depict reading/writing spanning conversion with all timing details, including setup, hold, and SCK.

CYC

POWER

PHASE

CNV

DIN

RDC

SDO

SCK

CNV

RAC

SDO

SCK

CNV

RSC

SDO

SCK

NOTES

1. CNV MUST BE HIGH PRIOR TO THE END OF CONVERSION (EOC) TO AVOID THE BUSY INDICATOR.

2. A TOT AL OF 16 SCK FALL ING EDGES ARE REQUI RED TO RE TURN SDO T O HIGH- Z. IF CFG READBACK IS ENABLED, A TOT AL OF 30 SCK FALLING EDGES IS REQUIRED TO RETURN SDO TO H IGH-Z.

DIN

MSB

XXX

CONV

CONVERSION

(n – 2) UNDEFI NED

XXX

DATA (n – 3)

XXX

116 16 16 16

EOC

ACQUISITION

(n – 1) UNDEFINED

NOTE 1

CFG (n) CFG (n + 1) CFG (n + 2) CFG (n + 3)

DATA (n – 2)

NOTE 2

NOTE 1

CFG (n) CFG (n)

DATA (n – 2)

116 16 16

Figure 39. General Interface Timing for the AD7682/AD7689 Without a Busy Indicator

. If the full CFG

DATA

SOC

DATA

CONVERSION

(n – 1) UNDEFINED

CFG (n) CFG ( n + 1) CFG (n + 2)

DATA (n – 2)

NOTE 2

XXX

DATA (n – 2)

XXX

nnnnn + 1 n + 1 n + 1

NOTE 2

EOC

ACQUISITI ON

XXX

When CNV is brought low after EOC, SDO is driven from high impedance to the MSB. Falling SCK edges clock out bits starting with MSB − 1.

The SCK can idle high or low depending on the clock polarity (CPOL) and clock phase (CPHA) settings if SPI is used. A simple solution is to use CPOL = CPHA = 0 as shown in Figure 39 with SCK idling low.

From power-up, in any read/write mode, the first three conversion results are undefined because a valid CFG does not take place until the second EOC; therefore, two dummy conversions are required. If the state machine writes the CFG during the power-up state (RDC shown), the CFG register must be rewritten at the next phase. The first valid data occurs in phase (n + 1) when the CFG register is written during phase (n − 1).

EOC

(n)

MSB

XXX

DATA (n – 1)

XXX

DATA (n – 1)

XXX

EOC

CONVERSIO N

(n)

DATA (n – 1)

XXX

1 1

DATA (n – 1)

XXX

ACQUISITION

(n + 1)

1161616

CFG (n + 2) CFG (n + 2)CFG (n + 1) CFG (n + 1)

DATA (n)

CONVERSION

(n + 1)

DATA (n)

DATA (n) DATA ( n + 1)

ACQUISITION

(n + 2)

DATA (n + 1)DATA (n)

CFG (n + 3)

07353-043

Rev. F | Page 28 of 35

Data Sheet AD7682/AD7689

GENERAL TIMING WITH A BUSY INDICATOR

Figure 40 details the timing for all three modes: RDC, RAC, and RSC. Note that the gating item for both CFG and data readback is at EOC. The data access must occur up to safe data reading/writing time, t to prior to EOC, it is discarded and the current configuration remains.

At the EOC, if CNV is low, the busy indicator enables. In addition, to generate the busy indicator properly, the host must assert a minimum of 17 SCK falling edges to return SDO to high impedance because the last bit on SDO remains active. Unlike the case detailed in the Read/Write Spanning Conversion Without a Busy Indicator section, if the conversion result is not read out fully prior to EOC, the last bit clocked out remains. If this bit is low, the busy signal indicator cannot be generated because the busy generation requires either a high impedance or a remaining bit high-to-low transition. A good example of this occurs when an SPI host sends 16 SCKs because

POWER

PHASE

. If the full CFG word is not written

DATA

START OF CONVERSION

(SOC)

CONV

CONVERSION

(n – 2) UNDEFI NED

CYC

EOC

ACQUISIT ION

(n – 1) UNDEFINED

DATA

CONVERSION

(n – 1) UNDEFINED

EOC

ACQUISITI ON

these are usually limited to 8-bit or 16-bit bursts; therefore, the LSB remains. Because the transition noise of the AD7682/

AD7689 is 4 LSBs peak-to-peak (or greater), the LSB is low 50%

of the time. For this interface, the SPI host needs to burst 24 SCKs, or a QSPI interface can be used and programmed for 17 SCKs.

The SCK can idle high or low depending on the CPOL and CPHA settings if SPI is used. A simple solution is to use CPOL = CPHA = 1 (not shown) with SCK idling high.

From power-up, in any read/write mode, the first three conversion results are undefined because a valid CFG does not take place until the second EOC; thus, two dummy conversions are required. Also, if the state machine writes the CFG during the power-up state (RDC shown), the CFG register needs to be rewritten again at the next phase. The first valid data occurs in phase (n + 1) when the CFG register is written during phase (n − 1).

EOC EOC

CONVERSIO N

(n)

ACQUISITION

(n + 1)

CONVERSIO N

(n + 1)

ACQUISITI ON

(n + 2)

CNV

DIN

RDC

SDO

SCK

CNV

DIN

RAC

SDO

SCK

CNV

DIN

RSC

SDO

SCK

NOTES

1. CNV MUST BE LOW PRIOR T O THE E ND OF CONVERSION (EOC) TO GENERAT E THE BUSY INDICAT OR.

2. A TOT AL OF 17 SCK FALL ING EDGES ARE REQ UIRED TO RETURN SDO TO HI GH-Z. IF CFG READBACK IS ENABLED, A TOT AL OF 31 S CK FALLING EDG ES IS REQ UIRED TO RETURN SDO TO HI GH-Z.

XXX

1 1

NOTE 1

CFG (n) CFG (n + 1) CFG (n + 2)

17 17 17 17

NOTE 1

CFG (n) CFG (n + 1) CFG (n + 2) CFG (n + 3)

NOTE 2

NOTE 1

CFG (n)

1nn + 117

NOTE 2

1 n n + 1 17 1 n n + 1 17

1 1

17 17

CFG (n + 1) CFG (n + 3)

Figure 40. General Interface Timing for the AD7682/AD7689 With a Busy Indicator

DATA (n)

CFG (n + 2)

DATA (n) DATA (n + 1 )

DATA (n + 1)DATA ( n)

07353-044

Rev. F | Page 29 of 35

AD7682/AD7689 Data Sheet

CHANNEL SEQUENCER

The AD7682/AD7689 include a channel sequencer useful for scanning channels in a repeated fashion. Channels are scanned as singles or pairs, with or without the temperature sensor, after the last channel is sequenced.

The sequencer starts with IN0 and finishes with IN[7:0] set in CFG[9:7]. For paired channels, the channels are paired depending on the last channel set in CFG[9:7]. Note that in sequencer mode, the channels are always paired with the positive input on the even channels (IN0, IN2, IN4, and IN6), and with the negative input on the odd channels (IN1, IN3, IN5, and IN7). For example, setting CFG[9:7] = 110 or 111 scans all pairs with the positive inputs dedicated to IN0, IN2, IN4, and IN6.

CFG[2:1] are used to enable the sequencer. After the CFG register is updated, DIN must be held low while reading data out for Bit 13, or the CFG register begins updating again.

Note that while operating in a sequence, some bits of the CFG register can be changed. However, if changing CFG[11] (paired or single channel) or CFG[9:7] (last channel in sequence), the sequence reinitializes and converts IN0 (or IN0/IN1 pairs) after the CFG register is updated.

Figure 41 details the timing for all three modes without a busy indicator. Refer to the Read/Write Spanning Conversion Without a Busy Indicator section and the Read/Write Spanning

SOC

CONVERSIO N

(n – 1) UNDEFINED

DATA

CFG (n)

DATA (n – 2)

XXX

NOTE 2

EOC

RDC

PHASE

CNV

DIN

SDO

SCK

POWER

MSB XXX

CYC

CONV

CONVERSION

(n – 2) UNDEFI NED

XXX

DATA (n – 3)

XXX

EOC

ACQUISIT ION

(n – 1) UNDEFINED

NOTE 1

16 16 16 16

ACQUISIT ION

Conversion Without a Busy Indicator section for more details. The sequencer can also be used with the busy indicator and details for these timings can be found in the General Timing with a Busy Indicator section and the Read/Write Spanning Conversion with a Busy Indicator section.

For sequencer operation, the CFG register must be set during the (n − 1) phase after power-up. On phase (n), the sequencer setting takes place and acquires IN0. The first valid conversion result is available at phase (n + 1). After the last channel set in CFG[9:7] is converted, the internal temperature sensor data is output (if enabled), followed by acquisition of IN0.

Examples

With all channels configured for unipolar mode to GND, including the internal temperature sensor, the sequence scans in the following order:

IN0, IN1, IN2, IN3, IN4, IN5, IN6, IN7, TEMP, IN0, IN1, IN2… For paired channels with the internal temperature sensor

enabled, the sequencer scans in the following order: IN0, IN2, IN4, IN6, TEMP, IN0… Note that IN1, IN3, IN5, and IN7 are referenced to a GND

sense or V

/2, as detailed in the Input Configurations section.

REF

(n), IN0

EOC

CONVERSIO N

(n), IN0

MSB XXX

DATA (n – 1)

XXX

1 1

ACQUISIT ION

(n + 1), IN1

CONVERSIO N

(n + 1), IN1

DATA IN0

EOC

ACQUISIT ION

(n + 2), IN2

CNV

DIN

RAC

SDO

SCK

CNV

DIN

RSC

SDO

SCK

NOTES

1. CNV MUST BE HIGH PRIOR TO THE END O F CONVE RSION (EOC) TO AVOID THE BUSY I NDICATOR.

2. A TOT AL OF 16 SCK FALL ING EDG ES ARE REQ UIRED TO RETURN SDO TO HI GH-Z. IF CFG READBACK IS E NABLED, A TOTAL OF 30 SCK FALLING EDGES IS REQUIRED TO RETURN SDO TO HIGH-Z.

CFG (n)

DATA (n – 2)

XXX

NOTE 2

CFG (n) CFG (n)

DATA (n – 2)

XXX

116 16 16

DATA (n – 2)

XXX

nnnnn + 1 n + 1 n + 1

NOTE 2

DATA (n – 1)

XXX

DATA (n – 1)

XXX

DATA (n – 1)

XXX

1161616

DATA IN0

DATA IN1DATA IN0

DATA IN0 DATA IN1

07353-046

Figure 41. General Channel Sequencer Timing Without a Busy Indicator

Rev. F | Page 30 of 35

Data Sheet AD7682/AD7689

READ/WRITE SPANNING CONVERSION WITHOUT A BUSY INDICATOR

This mode is used when the AD7682/AD7689 are connected to any host using an SPI, serial port, or FPGA. The connection diagram is shown in Figure 42, and the corresponding timing is given in Figure 43. For the SPI, the host must use CPHA = CPOL = 0. Reading/writing spanning conversion is shown, which covers all three modes detailed in the Digital Interface section. For this mode, the host must generate the data transfer based on the conversion time. For an interrupt driven transfer that uses a busy indicator, refer to the Read/Write Spanning Conversion with a Busy Indicator section.

A rising edge on CNV initiates a conversion, forces SDO to high impedance, and ignores data present on DIN. After a conversion initiates, it continues until completion, irrespective of the state of CNV. CNV must be returned high before the safe data transfer time (t time (t

) to avoid generation of the busy signal indicator.

CONV

After the conversion is complete, the AD7682/AD7689 enter the acquisition phase and power-down. When the host brings CNV low after t

), and held high beyond the conversion

DATA

(maximum), the MSB enables on SDO. The

CONV

host also must enable the MSB of the CFG register at this time (if necessary) to begin the CFG update. While CNV is low, both a CFG update and a data readback take place. The first 14 SCK rising edges are used to update the CFG, and the first 15 SCK falling edges clock out the conversion results starting with MSB − 1. The restriction for both configuring and reading is that they both must occur before the t

time of the next

DATA

conversion elapses. All 14 bits of CFG[13:0] must be written or they are ignored. In addition, if the 16-bit conversion result is not read back before t

elapses, it is lost.

DATA

The SDO data is valid on both SCK edges. Although the rising edge can capture the data, a digital host using the SCK falling edge allows a faster reading rate, provided it has an acceptable

hold time. After the 16

(or 30th) SCK falling edge, or when CNV goes high (whichever occurs first), SDO returns to high impedance.

If CFG readback is enabled, the CFG register associated with the conversion result is read back MSB first following the LSB of the conversion result. A total of 30 SCK falling edges is required to return SDO to high impedance if this is enabled.

AD7682/ AD7689

CNV

SDO

DIN

SCK

FOR SPI USE CPHA = 0, CPOL = 0.

DIGITAL HOST

MISO

MOSI

SCK

07353-036

Figure 42. Connection Diagram for the AD7682/AD7689 Without a Busy Indicator

CONV

DATA

CNV

ACQUISITION

(n - 1)

SCK

DIN

SDO

NOTES

1. THE LSB IS FO R CONVERSION RESULT S OR THE CONFIG URATI ON REGISTER CFG (n – 1) IF 15 SCK FALLING EDGES = LSB O F CONVERSIO N RESULTS. 29 SCK FALLING EDGES = LSB OF CONFIGURATION REGISTER. ON THE 16TH OR 30TH SCK FALLING EDGE, SDO IS DRIVEN TO HIGH IMPENDANCE.

CONVERSION ( n – 1)

SCKH

SCKL

END DATA (n – 2)

DIS

SCK

CFG LSB

END CFG (n)

16/

LSB

CYC

EOC

RETURN CNV HIGH

FOR NO BUSY

(QUIET

TIME)

UPDATE (n)

CFG/S DO

CLSCK

DIS

CONV

CNVH

ACQ

ACQUISITION (n)

HDIN

SDIN

CFG

MSB

BEGIN CFG ( n + 1)

MSB

BEGIN DA TA (n – 1)

t t

HSDO DSDO

DIS

DATA

CONVERSION (n)

CFG

LSB

END CFG (n + 1)

END DATA (n – 1)

SEE NOTE

16/ 30

LSB

RETURN CNV HIGH

(QUIET

SEE NOTE

DIS

EOC

FOR NO BUSY

TIME)

UPDATE (n + 1)

CFG/SDO

07353-037

Figure 43. Serial Interface Timing for the AD7682/AD7689 Without a Busy Indicator

Rev. F | Page 31 of 35

AD7682/AD7689 Data Sheet

READ/WRITE SPANNING CONVERSION WITH A BUSY INDICATOR

This mode is used when the AD7682/AD7689 are connected to any host using an SPI, serial port, or FPGA with an interrupt input. The connection diagram is shown in Figure 44, and the corresponding timing is given in Figure 45. For the SPI, the host must use CPHA = CPOL = 1. Reading/writing spanning conversion is shown, which covers all three modes detailed in the Digital Interface section.

A rising edge on CNV initiates a conversion, ignores data present on DIN, and forces SDO to high impedance. After the conversion initiates, it continues until completion, irrespective of the state of CNV. CNV must be returned low before the safe data transfer time (t conversion time (t When the conversion is complete, SDO transitions from high impedance to low (data ready), and with a pull-up to VIO, SDO can be used to interrupt the host to begin data transfer.

After the conversion is complete, the AD7682/AD7689 enter the acquisition phase and power-down. The host must enable the MSB of the CFG register at this time (if necessary) to begin

), and then held low beyond the

DATA

) to generate the busy signal indicator.

CONV

the CFG update. While CNV is low, both a CFG update and a data readback take place. The first 14 SCK rising edges are used to update the CFG register, and the first 16 SCK falling edges clock out the conversion results starting with the MSB. The restriction for both configuring and reading is that they both occur before the t

time elapses for the next conversion. All

DATA

14 bits of CFG[13:0] must be written or they are ignored. If the 16-bit conversion result is not read back before t

elapses, it

DATA

is lost. The SDO data is valid on both SCK edges. Although the rising

edge can capture the data, a digital host using the SCK falling edge allows a faster reading rate, provided it has an acceptable

hold time. After the optional 17

(or 31st) SCK falling edge, SDO returns to high impedance. If the optional SCK falling edge is not used, the busy feature cannot be detected, as described in the General Timing with a Busy Indicator section.

If CFG readback is enabled, the CFG register associated with the conversion result is read back MSB first following the LSB of the conversion result. A total of 31 SCK falling edges is required to return SDO to high impedance if this is enabled.

AD7682/ AD7689

FOR SPI USE CPHA = 1, CPOL = 1.

Figure 44. Connection Diagram for the AD7682/AD7689 with a Busy Indicator

DIS

(QUIET

TIME)

UPDATE (n)

CYC

CFG/SDO

CFG MSB

BEIGN CFG ( n + 1)

MSB

DATA

CNV

CONVERSION

(n – 1)

SCK

DIN

SDO

NOTES:

1. THE LSB IS FO R CONVERSION RESULTS O R THE CONFIG URATION REGI STER CFG (n – 1 ) IF 16 SCK FALLING EDGES = LSB O F CONVERSIO N RESULTS. 30 SCK FALL ING ED GES = L SB OF CO NFIG URATIO N REGI STER. ON THE 17TH OR 31st SCK FALLING EDGE, SDO IS DRIVEN TO HIGH IMPENDANCE. OTHERWISE, THE LSB REMAINS ACTIVE UNTIL THE BUSY INDICATOR IS DRIVEN LOW.

CONVERSION ( n – 1)

SCK

SCKH

SCKL

END CFG (n)

END DATA (n – 2)

LSB

+ 1

17/ 31

LSB

Figure 45. Serial Interface Timing for the AD7682/AD7689 with a Busy Indicator

SDO

CNV

DIN

SCK

ACQ

ACQUISITION (n)

HDIN

SDIN

CFG

MSB –1

MSB

– 1

BEGIN DATA (n – 1 )

HSDO

DSDO

DIGITAL HOST

MISO

IRQ

MOSI

SCK

CNVH

07353-038

DIS

END DATA (n – 1)

CONV

DATA

CONVERSION ( n)

SEE NOTE

XXXX

END CFG (n + 1)

LSB

+ 1

17/ 31

LSB

SEE NOTE

(QUIET

TIME)

DIS

ACQUISITI ON

UPDATE (n + 1)

CFG/SDO

(n + 1)

07353-039

Rev. F | Page 32 of 35

Data Sheet AD7682/AD7689

APPLICATIONS INFORMATION

LAYOUT

The printed circuit board (PCB) that houses the AD7682/

AD7689 must be designed so that the analog and digital

sections are separated and confined to certain areas of the board. The pin configuration of the AD7682/AD7689, with all its analog signals on the left side and all its digital signals on the right side, eases this task.

Avoid running digital lines under the device because these couple noise onto the die unless a ground plane under the

AD7682/AD7689 is used as a shield. Fast switching signals,

such as CNV or clocks, must not run near analog signal paths. Avoid crossover of digital and analog signals.

Use at least one ground plane. It can be common or split between the digital and analog sections. In the latter case, join the planes underneath the AD7682/AD7689.

The AD7682/AD7689 voltage reference input, REF, has a dynamic input impedance and must be decoupled with minimal parasitic inductances. This is achieved by placing the reference decoupling ceramic capacitor close to (ideally, right up against)

the REF and GND pins and connecting them with wide, low impedance traces.

Finally, the power supplies of the AD7682/AD7689 (VDD and VIO) must be decoupled with ceramic capacitors, typically 100 nF, placed close to the AD7682/AD7689, and connected using short, wide traces to provide low impedance paths and to reduce the effect of glitches on the power supply lines.

The AN-617 Application Note has information on PCB layout and assembly. This information is particularly important for guiding customers who do not have experience with WLCSP.

EVALUATING THE AD7682/AD7689 PERFORMANCE

Other recommended layouts for the AD7682/AD7689 are outlined in the documentation of the evaluation board for the

AD7682/AD7689 (EVAL-AD7682EDZ/EVAL-AD7689EDZ).

The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a PC via the converter and evaluation development data capture board, EVAL-CED1Z.

Rev. F | Page 33 of 35

AD7682/AD7689 Data Sheet

OUTLINE DIMENSIONS

PIN 1

INDICATOR

0.80

0.75

0.70

SEATING

PLANE

4.10

4.00 SQ

3.90

0.50

BSC

0.50

0.40

0.30

0.05 MAX

0.02 NOM

0.20 REF

COPLANARITY

0.08

0.30

0.25

0.20

EXPOSED

PAD

BOTTOM VIEWTOP VIEW

FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.

2.65

2.50 SQ

2.35

0.25 MIN

COMPLIANTTOJEDEC STANDARDS MO-220-WGGD.

061609-B

Figure 46. 20-Lead Lead Frame Chip Scale Package (LFCSP_WQ)

4 mm × 4 mm Body, Very Very Thin Quad

(CP-20-10)

Dimensions shown in millimeters

2.430

PKG-004466

BALL A1

IDENTIFIER

0.560

0.500

0.440

SEATING

PLANE

2.390 SQ

2.350

TOP VIEW

(BALL SIDE DO WN)

SIDE VIEW

0.300

0.260

0.220

0.50 REF

0.330

0.300

0.270

0.433 REF

0.25 REF

COPLANARI TY

0.05

0.230

0.200

0.170

BOTTOM VIEW

(BALL SIDE UP )

0.50 REF

05-13-2014-A

Figure 47. 20-Ball Wafer Level Chip Scale Package (WLCSP)

(CB-20-12)

Dimensions shown in millimeters

Rev. F | Page 34 of 35

Data Sheet AD7682/AD7689

ORDERING GUIDE

Integral Nonlinearity

Model

1, 2

AD7682BCPZ ±2 LSB max 16 bits −40°C to +85°C 20-Lead LFCSP_WQ CP-20-10 Tray, 490 AD7682BCPZRL7 ±2 LSB max 16 bits −40°C to +85°C 20-Lead LFCSP_WQ CP-20-10 Reel, 1,500 AD7682BCBZ-RL7 ±2 LSB max 16 bits −40°C to +85°C 20-Ball WLCSP CB-20-12 Reel, 1,500 AD7689ACPZ ±6 LSB max 15 bits −40°C to +85°C 20-Lead LFCSP_WQ CP-20-10 Tray, 490 AD7689ACPZRL7 ±6 LSB max 15 bits −40°C to +85°C 20-Lead LFCSP_WQ CP-20-10 Reel, 1,500 AD7689BCPZ ±2 LSB max 16 bits −40°C to +85°C 20-Lead LFCSP_WQ CP-20-10 Tray, 490 AD7689BCPZRL7 ±2 LSB max 16 bits −40°C to +85°C 20-Lead LFCSP_WQ CP-20-10 Reel, 1,500 AD7689BCBZ-RL7 ±2 LSB max 16 bits −40°C to +85°C 20-Ball WLCSP CB-20-12 Reel, 1,500 EVAL-AD7682EDZ Evaluation Board EVAL-AD7689EDZ Evaluation Board EVAL-CED1Z

Z = RoHs Compliant Part.

The EVAL-CED1Z controller board allows a PC to control and communicate with all Analog Devices evaluation boards whose model numbers end in ED.

No Missing Code

Temperature Range Package Description

Converter Evaluation and Development Board

Package Option

Ordering Quantity

Rev. F | Page 35 of 35

ANALOG DEVICES AD 7689 BCPZ Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

TIMING SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

TERMINOLOGY

THEORY OF OPERATION

OVERVIEW

CONVERTER OPERATION

TRANSFER FUNCTIONS

TYPICAL CONNECTION DIAGRAMS

Unipolar or Bipolar

Bipolar Single Supply

ANALOG INPUTS

Input Structure

Selectable Low-Pass Filter

Input Configurations

Sequencer

Source Resistance

DRIVER AMPLIFIER CHOICE

VOLTAGE REFERENCE OUTPUT/INPUT

Internal Reference/Temperature Sensor

External Reference and Internal Buffer

External Reference

Reference Decoupling

POWER SUPPLY

SUPPLYING THE ADC FROM THE REFERENCE

DIGITAL INTERFACE

READING/WRITING DURING CONVERSION, FAST HOSTS

READING/WRITING AFTER CONVERSION, ANY SPEED HOSTS

READING/WRITING SPANNING CONVERSION, ANY SPEED HOST

CONFIGURATION REGISTER, CFG

GENERAL TIMING WITHOUT A BUSY INDICATOR

GENERAL TIMING WITH A BUSY INDICATOR

CHANNEL SEQUENCER

Examples

READ/WRITE SPANNING CONVERSION WITHOUT A BUSY INDICATOR

READ/WRITE SPANNING CONVERSION WITH A BUSY INDICATOR

APPLICATIONS INFORMATION

LAYOUT

EVALUATING THE AD7682/AD7689 PERFORMANCE

OUTLINE DIMENSIONS

ORDERING GUIDE