ANALOG DEVICES AD7688 Service Manual
16-Bit, 1.5 LSB INL, 500 kSPS PulSAR™
www.BDTIC.com/ADI
FEATURES
16-bit resolution with no missing codes
Throughput: 500 kSPS
INL: ±0.4 LSB typ, ±1.5 LSB max (±23 ppm of FSR)
Dynamic range: 96.5 dB
SNR: 95.5 dB @ 20 kHz
THD: −118 dB @ 20 kHz
True differential analog input range
±V
REF
0 V to V
No pipeline delay
Single-supply 5 V operation with
1.8 V/2.5 V/3 V/5 V logic interface
Serial interface SPI®/QSPI™/MICROWIRE™/DSP-compatible
Daisy-chain multiple ADCs and BUSY indicator
Power dissipation
3.75 mW @ 5 V/100 kSPS
3.75 µW @ 5 V/100 SPS
Standby current: 1 nA
10-lead MSOP (MSOP-8 size) and
3 mm × 3 mm QFN
Pin-for-pin compatible with AD7685, AD7686, and AD7687
APPLICATIONS
Battery-powered equipment
Data acquisitions
Instrumentation
Medical instruments
Process controls
1.5
1.0
with V
REF
up to VDD on both inputs
REF
1
(LFCSP) (SOT-23 size)
POSITIVE INL = +0.31LSB
NEGATIVE INL = –0.39LSB
Differential ADC in MSOP/QFN
AD7688
APPLICATION DIAGRAM
0.5V TO 5V 5V
VREF
0
VREF
0
IN+
IN–
REF
AD7688
GND
Table 1. MSOP, QFN1 (LFCSP)/SOT-23 16-Bit PulSAR ADC
Type 100 kSPS 250 kSPS 500 kSPS
True Differential AD7684 AD7687 AD7688
Pseudo AD7683 AD7685 AD7686
Differential/Unipolar AD7694
Unipolar AD7680
GENERAL DESCRIPTION
The AD7688 is a 16-bit, charge redistribution, successive
approximation, analog-to-digital converter (ADC) that operates
from a single 5 V power supply, VDD. It contains a low power,
high speed, 16-bit sampling ADC with no missing codes, an
internal conversion clock, and a versatile serial interface port.
The part also contains a low noise, wide bandwidth, short
aperture delay track-and-hold circuit. On the CNV rising edge,
it samples the voltage difference between IN+ and IN− pins.
The voltages on these pins usually swing in opposite phase
between 0 V and REF. The reference voltage, REF, is applied
externally and can be set up to the supply voltage.
Its power scales linearly with throughput.
VIO
VDD
SDI
SCK
SDO
CNV
Figure 2.
1.8V TO VDD
3- OR 4-WIRE INTERFACE
(SPI, DAISY CHAIN, CS)
02973-002
0.5
The SPI-compatible serial interface also features the ability,
using the SDI input, to daisy-chain several ADCs on a single,
0
INL (LSB)
–0.5
–1.0
3-wire bus and provides an optional BUSY indicator. It is
compatible with 1.8 V, 2.5 V, 3 V, or 5 V logic, using the separate
supply VIO.
The AD7688 is housed in a 10-lead MSOP or a 10-lead QFN
(LFCSP) with operation specified from −40°C to +85°C.
–1.5
0 16384 32768 49152 65535
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Anal og Devices. Trademarks and
registered trademarks are the property of their respective owners.
Figure 1. Integral Nonlinearity vs. Code
CODE
02973-001
1
QFN package in development. Contact sales for samples and availability.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2005 Analog Devices, Inc. All rights reserved.
1
AD7688
www.BDTIC.com/ADI
TABLE OF CONTENTS
Specifications..................................................................................... 3
Power Supply............................................................................... 15
Timing Specifications....................................................................... 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configurations and Function Descriptions ...........................7
Te r mi n ol o g y ...................................................................................... 8
Typical Performance Characteristics............................................. 9
Circuit Information.................................................................... 12
Converter Operation.................................................................. 12
Typical Connection Diagram ................................................... 13
Analog Input............................................................................... 14
Driver Amplifier Choice............................................................ 15
Single-to-Differential Driver..................................................... 15
Voltage Re feren ce Input .............................................................15
REVISION HISTORY
Supplying the ADC from the Reference.................................. 16
Digital Interface.......................................................................... 16
CS
MODE 3-Wire, No BUSY Indicator .................................. 17
CS
Mode 3-Wire with BUSY Indicator ................................... 18
CS
Mode 4-Wire, No BUSY Indicator..................................... 19
CS
Mode 4-Wire with BUSY Indicator ................................... 20
Chain Mode, No BUSY Indicator ............................................21
Chain Mode with BUSY Indicator........................................... 22
Application Hints ........................................................................... 23
Layout ..........................................................................................23
Evaluating the AD7688’s Performance.................................... 23
Outline Dimensions .......................................................................24
Ordering Guide .......................................................................... 25
4/05—Revision 0: Initial Version
Rev 0 | Page 2 of 28
AD7688
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SPECIFICATIONS
VDD = 4.5 V to 5.5 V, VIO = 2.3 V to VDD, V
Table 2.
Parameter Conditions Min Typ Max Unit
RESOLUTION 16 Bits
ANALOG INPUT
Voltage Range IN+ − IN− −V
Absolute Input Voltage IN+, IN− −0.1 V
Common-Mode Input Range IN+, IN− 0 V
Analog Input CMRR fIN = 250 kHz 65 dB
Leakage Current at 25°C Acquisition phase 1 nA
Input Impedance See the Analog Input section
ACCURACY
No Missing Codes 16 Bits
Differential Linearity Error −1 ±0.4 +1 LSB
Integral Linearity Error −1.5 ±0.4 +1.5 LSB
Transition Noise REF = VDD = 5 V 0.4 LSB
Gain Error2, T
MIN
to T
MAX
Gain Error Temperature Drift ±0.3 ppm/°C
Zero Error2, T
MIN
to T
MAX
Zero Temperature Drift ±0.3 ppm/°C
Power Supply Sensitivity
THROUGHPUT
Conversion Rate 0 500 kSPS
Transient Response Full-scale step 400 ns
AC ACCURACY
Dynamic Range V
Signal-to-Noise fIN = 20 kHz, V
f
Spurious-Free Dynamic Range fIN = 20 kHz −118 dB
Total Harmonic Distortion fIN = 20 kHz −118 dB
Signal-to-(Noise + Distortion) fIN = 20 kHz, V
f
Intermodulation Distortion
1
LSB means least significant bit. With the ±5 V input range, one LSB is 152.6 µV.
2
See the section. These specifications do include full temperature range variation but do not include the error contribution from the external reference. Terminology
3
All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified.
4
f
= 21.4 kHz, f
IN1
= 18.9 kHz, each tone at −7 dB below full-scale.
IN2
4
= VDD, TA = –40°C to +85°C, unless otherwise noted.
REF
REF
+V
/2 V
REF
REF
+ 0.1 V
REF
/2 + 0.1 V
REF
V
1
±2 ±6 LSB
±0.1 ±1.6 mV
VDD = 5V ± 5%
= 5 V 95.8 96.5 dB
REF
= 5 V 94 95.5 dB
REF
= 20 kHz, V
IN
= 20 kHz, V
IN
= 5 V 92.5 dB
REF
= 5 V 93.5 95 dB
REF
= 5 V, −60 dB input 36.5 dB
REF
±0.05 LSB
3
115 dB
Rev 0 | Page 3 of 28
AD7688
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VDD = 4.5 V to 5.5 V, VIO = 2.3 V to VDD, V
Table 3.
Parameter Conditions Min Typ Max Unit
REFERENCE
Voltage Range 0.5 VDD + 0.3 V
Load Current 500 kSPS, REF = 5 V 100 µA
SAMPLING DYNAMICS
−3 dB Input Bandwidth 9 MHz
Aperture Delay VDD = 5 V 2.5 ns
DIGITAL INPUTS
Logic Levels
V
IL
V
IH
I
IL
I
IH
–0.3 +0.3 × VIO V
0.7 × VIO VIO + 0.3 V
−1 +1 µA
−1 +1 µA
DIGITAL OUTPUTS
Data Format Serial 16 bits twos complement
Pipeline Delay
V
OL
V
OH
I
= +500 µA 0.4 V
SINK
I
= −500 µA VIO − 0.3 V
SOURCE
POWER SUPPLIES
VDD Specified performance 4.5 5.5 V
VIO Specified performance 2.3 VDD + 0.3 V
VIO Range 1.8 VDD + 0.3 V
Standby Current
1, 2
VDD and VIO = 5 V, 25°C 1 50 nA
Power Dissipation VDD = 5 V, 100 SPS throughput 3.75 µW
VDD = 5 V, 100 kSPS throughput 3.75 4.3 mW
VDD = 5 V, 500 kSPS throughput 21.5 mW
TEMPERATURE RANGE
Specified Performance T
1
With all digital inputs forced to VIO or GND as required.
2
During acquisition phase.
3
Contact sales for extended temperature range.
3
to T
MIN
= VDD, TA = –40°C to +85°C, unless otherwise noted.
REF
Conversion results available immediately
after completed
MAX
−40 +85 °C
conversion
Rev 0 | Page 4 of 28
AD7688
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TIMING SPECIFICATIONS
−40°C to +85°C, VDD = 4.5 V to 5.5 V, VIO = 2.3 V to 5.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated.
See Figure 3 and Figure 4 for load conditions.
Table 4.
Parameter Symbol Min Typ Max Unit
Conversion Time: CNV Rising Edge to Data Available t
Acquisition Time t
Time Between Conversions t
CNV Pulse Width ( CS Mode )
SCK Period ( CS Mode )
SCK Period ( Chain Mode ) t
SCK Low Time t
SCK High Time t
SCK Falling Edge to Data Remains Valid t
SCK Falling Edge to Data Valid Delay t
CNV or SDI Low to SDO D15 MSB Valid (CS Mode)
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
SDI Valid Setup Time from CNV Rising Edge (CS Mode)
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
SCK Valid Setup Time from CNV Rising Edge (Chain Mode) t
SCK Valid Hold Time from CNV Rising Edge (Chain Mode) t
SDI Valid Setup Time from SCK Falling Edge (Chain Mode) t
SDI Valid Hold Time from SCK Falling Edge (Chain Mode) t
SDI High to SDO High (Chain Mode with BUSY indicator) t
0.5 1.6 µs
400 ns
2 µs
10 ns
15 ns
t
t
CONV
ACQ
CYC
CNVH
SCK
SCK
VIO Above 4.5 V 17 ns
VIO Above 3 V 18 ns
VIO Above 2.7 V 19 ns
VIO Above 2.3 V 20 ns
SCKL
SCKH
HSDO
DSDO
7 ns
7 ns
5 ns
VIO Above 4.5 V 14 ns
VIO Above 3 V 15 ns
VIO Above 2.7 V 16 ns
VIO Above 2.3 V 17 ns
t
EN
VIO Above 4.5 V 15 ns
VIO Above 2.7 V 18 ns
VIO Above 2.3 V 22 ns
t
DIS
t
SSDICNV
t
HSDICNV
SSCKCNV
HSCKCNV
SSDISCK
HSDISCK
DSDOSDI
25 ns
15 ns
0 ns
5 ns
5 ns
3 ns
4 ns
VIO Above 4.5 V 15 ns
VIO Above 2.3 V 26 ns
Rev 0 | Page 5 of 28
AD7688
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ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Rating
Analog Inputs
IN+1, IN−1
REF GND − 0.3 V to VDD + 0.3 V
Supply Voltages
VDD, VIO to GND −0.3 V to +7 V
VDD to VIO ±7 V
Digital Inputs to GND −0.3 V to VIO + 0.3 V
Digital Outputs to GND −0.3 V to VIO + 0.3 V
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
θJA Thermal Impedance 200°C/W (MSOP-10)
θJC Thermal Impedance 44°C/W (MSOP-10)
Lead Temperature Range JEDEC J-STD-20
1
See the section. Analog Input
GND − 0.3 V to VDD + 0.3 V
or ±130 mA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
500µAI
TO SDO
Figure 3. Load Circuit for Digital Interface Timing
C
50pF
L
500µAI
30% VIO
t
DELAY
2V OR VIO – 0.5V
0.8V OR 0.5V
1
2V IF VIO ABOVE 2.5V, VIO– 0.5V IF VIO BELOW 2.5V.
2
0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.
Figure 4. Voltage Levels for Timing
OL
1.4V
OH
70% VIO
t
1
2
02973-003
DELAY
2V OR VIO – 0.5V
0.8V OR 0.5V
2
1
02973-004
Rev 0 | Page 6 of 28
AD7688
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PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
REF
1
2
VDD
IN+
IN–
GND
Figure 5. 10-Lead MSOP Pin Configuration
AD7688
3
TOP VIEW
(Not to Scale)
4
5
Table 6. Pin Function Descriptions
Pin No. Mnemonic Type1Function
1 REF AI
2 VDD P Power Supply.
3 IN+ AI Differential Positive Analog Input.
4 IN− AI Differential Negative Analog Input.
5 GND P Power Supply Ground.
6 CNV DI
7 SDO DO Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.
8 SCK DI Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock.
9 SDI DI Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as follows:
10 VIO P
1
AI = Analog Input, DI = Digital Input, DO = Digital Output, and P = Power.
VIO
10
9
SDI
SCK
8
7
SDO
CNV
6
02973-005
1
QFN package in development. Contact sales for samples and availability.
1REF
2VDD
AD7688
3IN+
TOP VIEW
(Not to Scale)
4IN–
5GND
Figure 6. 10-Lead QFN
10 VIO
9 SDI
8 SCK
7 SDO
6 CNV
1
(LFCSP) Pin Configuration
02973-006
Reference Input Voltage. The REF range is from 0.5 V to VDD. It is referred to the GND pin. This pin should
be decoupled closely to the pin with a 10 µF capacitor.
Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and
CS
selects the interface mode, chain or
. In CS mode, it enables the SDO pin when low. In chain mode, the
data should be read when CNV is high.
Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data input to
daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on
SDI is output on SDO with a delay of 16 SCK cycles.
CS
mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable
the serial output signals when low, and if SDI or CNV is low when the conversion is complete, the BUSY
indicator feature is enabled.
Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V,
or 5 V).
Rev 0 | Page 7 of 28
AD7688
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TERMINOLOGY
Integral Nonlinearity Error (INL)
It refers to the deviation of each individual code from a line
drawn from negative full scale through positive full scale. The
point used as negative full scale occurs ½ LSB before the first
code transition. Positive full scale is defined as a level 1½ LSB
beyond the last code transition. The deviation is measured from
the middle of each code to the true straight line (Figure 25).
Differential Nonlinearity Error (DNL)
I
n an ideal ADC, code transitions are 1 LSB apart. DNL is the
maximum deviation from this ideal value. It is often specified in
terms of resolution for which no missing codes are guaranteed.
Zero Error
t is the difference between the ideal midscale voltage, that is, 0
I
V, from the actual voltage producing the midscale output code,
that is, 0 LSB.
Gain Error
The f
irst transition (from 100 . . . 00 to 100 . . . 01) should occur
at a level ½ LSB above nominal negative full scale (−4.999924 V
for the ±5 V range). The last transition (from 011…10 to
011…11) should occur for an analog voltage 1½ LSB below the
nominal full scale (+4.999771 V for the ±5 V range.) The gain
error is the deviation of the difference between the actual level
of the last transition and the actual level of the first transition
from the difference between the ideal levels.
Spurious-Free Dynamic Range (SFDR)
S
FDR is the difference, in decibels (dB), between the rms
amplitude of the input signal and the peak spurious signal.
Effective Number of Bits (ENOB)
EN
OB is a measurement of the resolution with a sine wave
input. It is related to S/(N+D) by the following formula
ENOB = (S
and is expressed in bits.
Total Harmonic Distortion (THD)
HD is the ratio of the rms sum of the first five harmonic
T
components to the rms value of a full-scale input signal and is
expressed in dB.
Dynamic Range
I
t is the ratio of the rms value of the full scale to the total rms
noise measured with the inputs shorted together. The value for
dynamic range is expressed in dB.
Signal-to-Noise Ratio (SNR)
S
NR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in dB.
Signal-to-(Noise + Distortion) Ratio (S/[N+D])
S/(N+D) is t
to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc. The
value for S/(N+D) is expressed in dB.
Aperture Delay
A
perature delay is the measure of the acquisition performance.
It is the time between the rising edge of the CNV input and
when the input signal is held for a conversion.
/[N + D]
he ratio of the rms value of the actual input signal
− 1.76)/6.02
dB
Transi e nt Res p onse
I
t is the time required for the ADC to accurately acquire its
input after a full-scale step function was applied.
Rev 0 | Page 8 of 28
AD7688
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TYPICAL PERFORMANCE CHARACTERISTICS
1.5
1.0
POSITIVE INL = +0.31LSB
NEGATIVE INL = –0.39LSB
1.5
1.0
POSITIVE DNL = +0.37LSB
NEGATIVE DNL = –0.21LSB
0.5
0
INL (LSB)
–0.5
–1.0
–1.5
0 16384 32768 49152 65535
CODE
Figure 7. Integral Nonlinearity vs. Code
300000
256159
250000
200000
150000
COUNTS
100000
50000
0 0 2930 0 0
0
CODE IN HEX
VDD = REF = 5V
2031
73 74 756F 70 71 72
Figure 8. Histogram of a DC Input at the Code Center
0
–20
–40
–60
–80
–100
–120
–140
AMPLITUDE (dB of Full Scale)
–160
–180
0 25 50 75 100 125 150 200175 225 250
FREQUENCY (kHz)
16384 POINT FFT
VDD = REF = 5V
F
= 500KSPS
S
F
= 2kHz
IN
SNR = 95.6dB
THD = –117.7dB
SFDR = –117.9dB
2nd HARM = –125dB
3rd HARM = –119dB
Figure 9. FFT Plot
0.5
0
DNL (LSB)
–0.5
–1.0
02973-001
–1.5
0 16384 32768 49152 65535
CODE
02973-009
Figure 10. Differential Nonlinearity vs. Code
160000
140000
120000
100000
80000
COUNTS
60000
40000
20000
02973-007
0
0
124933
0
72
136187
74 7671 73
CODE IN HEX
VDD = REF = 5V
00
75
02973-010
Figure 11. Histogram of a DC Input at the Code Transition
100
99
98
97
96
95
94
SNR (dB)
93
92
91
02973-008
90
INPUT LEVEL (dB)
02973-011
0–10–8–6–4–2
Figure 12. SNR vs. Input Level
Rev 0 | Page 9 of 28
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