Analog Devices AD7687 pri Datasheet
16-Bit, 1.5 LSB INL, 250 kSPS PulSAR™
V
Preliminary Technical Data
FEATURES
16-bit resolution with no missing codes
Throughput: 250 kSPS
INL: ±0.5 LSB typ, ±1.5 LSB max (±0.0023 % of FSR)
S/(N + D): 95 dB @ 20 kHz
THD: −115 dB @ 20 kHz
True differential analog input range: ±V
0 V to V
with V
REF
up to VDD on both inputs
REF
No pipeline delay
Single-supply 5V operation with
1.8 V/2.5 V/3 V/5 V logic interface
Serial interface SPI®/QSPI™/µWire/DSP compatible
Daisy chain multiple ADCs and BUSY indicator
Power dissipation
1.35 mW @ 2.5 V/100 kSPS, 4 mW @ 5V/100kSPS,
1.4 µW @ 2.5 V/100 SPS
Stand-by current: 1 nA
10-lead package: MSOP (MSOP-8 size) and
QFN (LFCSP), 3 mm × 3 mm same space as SOT-23
Pin-for-pin compatible with the AD7685, AD7686, and
AD7688
APPLICATIONS
Battery-powered equipment
Data acquisition
Instrumentation
Medical instruments
Process control
1.5
1.0
0.5
0.0
INL (LSB)
-0.5
-1.0
-1.5
0 16384 32768 49152 65536
Figure 1. Integral Nonlinearity vs. Code.
Code
REF
Positive INL = +0.30LSB
Negative INL = -0.31LSB
Differential ADC in MSOP/QFN
AD7687
APPLICATION DIAGRAM
0.5 TO 5V 5V
REF
VREF
0
0
IN+
IN–
AD7687
REF
GND
VIO
VDD
SDI
SCK
SDO
CNV
Figure 2.
Table 1. MSOP, QFN (LFCSP)/SOT-23 16-Bit PulSAR ADC
Type 100 kSPS 250 kSPS 500 kSPS
True Differential AD7684 AD7687 AD7688
Pseudo
AD7683
Differential/Unipolar
Unipolar AD7680
GENERAL DESCRIPTION
The AD7687 is a 16-bit, charge redistribution successive
approximation, analog-to-digital converter (ADC) that operates
from a single 5V power supply, VDD. It contains a low power,
high speed, 16-bit sampling ADC with no missing codes, an
internal conversion clock, and a versatile serial interface port.
The part also contains a low noise, wide bandwidth, short
aperture delay track-and-hold circuit. On the CNV rising edge,
it samples the voltage difference between IN+ and IN- pins. The
voltages on these pins usually swing in opposite phase between
0 V to REF. The reference voltage, REF, is applied externally and
can be set up to the supply voltage.
Its power scales linearly with throughput.
The SPI compatible serial interface also features the ability,
using the SDI input, to daisy chain several ADCs on a single 3wire bus and provides an optional BUSY indicator. It is
compatible with 1.8 V, 2.5 V, 3 V, or 5 V logic using the separate
supply VIO.
The AD7687 is housed in a 10-lead MSOP or a 10-lead QFN
(LFCSP) with operation specified from −40°C to +85°C.
1.8 TO VDD
3- OR 4-WIRE INTERFACE
(SPI, DAISY CHAIN, CS)
AD7685
AD7694
AD7686
Rev Pr I
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Anal og Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
AD7687 Preliminary Technical Data
TABLE OF CONTENTS
Specifications..................................................................................... 3
Converter Operation.................................................................. 13
Timing Specifications....................................................................... 5
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Terminology ......................................................................................9
Typical Performance Characteristics ...........................................10
Circuit Information.................................................................... 13
REVISION HISTORY
5/04—Revision I: Preliminary
Typical Connection Diagram ................................................... 14
Digital Interface.......................................................................... 18
Application Hints ........................................................................... 25
Layout .......................................................................................... 25
Evaluating the AD7687’s Performance.................................... 25
Outline Dimensions....................................................................... 26
Ordering Guide .......................................................................... 27
Rev Pr I | Page 2 of 28
Preliminary Technical Data AD7687
SPECIFICATIONS
VDD = 2.3 V to 5.5 V, VIO = 2.3 V to VDD, V
Table 2.
Parameter Conditions Min Typ Max Unit
RESOLUTION 16 Bits
ANALOG INPUT
Voltage Range IN+ − IN− −V
Absolute Input Voltage IN+, IN− −0.1 V
Analog Input CMRR fIN = 250 kHz 65 dB
Leakage Current at 25°C Acquisition Phase 1 nA
Input Impedance See the Analog Input section.
ACCURACY
No Missing Codes 16 Bits
Differential Linearity Error −1 ±0.4 +1 LSB1
Integral Linearity Error −1.5 ±0.4 +1.5 LSB
Transition Noise REF = VDD = 5 V 0.4 LSB
Gain Error2, T
MIN
to T
±2 ±TBD LSB
MAX
Gain Error Temperature Drift ±0.3 ppm/°C
Offset Error2, T
MIN
to T
VDD = 4.5 V to 5.5 V ±TBD ±TBD mV
MAX
VDD = 2.3 V to 4.5 V ±TBD ±TBD mV
Offset Temperature Drift ±0.3 ppm/°C
Power Supply Sensitivity
THROUGHPUT
Conversion Rate VDD = 4.5 V to 5.5 V 0 250 kSPS
VDD = 2.3 V to 4.5 V 0 200 kSPS
Transient Response Full-Scale Step 1.8 µs
AC ACCURACY
Signal-to-Noise fIN = 20 kHz, V
f
Spurious-Free Dynamic Range fIN = 20 kHz −115 dB
Total Harmonic Distortion fIN = 20 kHz −115 dB
Signal-to-(Noise + Distortion) fIN = 20 kHz, V
f
Signal-to-Noise fIN = 20 kHz, V
Intermodulation Distortion4 TBD dB
= VDD, TA = –40°C to +85°C, unless otherwise noted.
REF
VDD = 5 V ± 5%
REF
= 20 kHz, V
IN
= 20 kHz, V
IN
REF
REF
REF
REF
= 5 V 93 95 dB3
= 2.5 V TBD TBD dB
= 5 V 93 95 dB
= 5 V, −60 dB Input 35 dB
= 2.5 V TBD TBD dB
±0.05 LSB
+V
REF
V
REF
+ 0.1 V
REF
1
LSB means least significant bit. With the ±5 V input range, one LSB is 152.6 µV.
2
See section. These specifications do include full temperature range variation but do not include the error contribution from the external reference. Terminology
3
All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified.
4
f
= 21.4 kHz, f
IN1
= 18.9 kHz, each tone at −7 dB below full-scale.
IN2
Rev Pr I | Page 3 of 28
AD7687 Preliminary Technical Data
VDD = 2.3 V to 5.5 V, VIO = 2.3 V to VDD, V
Table 3.
Parameter Conditions Min Typ Max Unit
REFERENCE
Voltage Range 0.5 VDD + 0.3 V
Load Current 250 kSPS, REF = 5 V 50 µA
SAMPLING DYNAMICS
−3 dB Input Bandwidth 2 MHz
Aperture Delay VDD = 5 V 2.5 ns
DIGITAL INPUTS
Logic Levels
VIL –0.3 0.3 × VIO V
VIH 0.7 × VIO VIO + 0.3 V
IIL −1 +1 µA
IIH −1 +1 µA
DIGITAL OUTPUTS
Data Format Serial 16 Bits Twos Complement
Pipeline Delay
VOL I
VOH I
= +500 µA 0.4 V
SINK
= −500 µA VIO − 0.3 V
SOURCE
POWER SUPPLIES
VDD Specified Performance 2.3 5.5 V
VIO Specified Performance 2.3 VDD + 0.3 V
VIO Range 1.8 VDD + 0.3 V
Standby Current
1, 2
VDD and VIO = 5 V, 25°C 1 50 nA
Power Dissipation VDD = 2.5 V, 100 SPS Throughput 1.4 µW
VDD = 2.5 V, 100 kSPS Throughput 1.35 2.4 mW
VDD = 2.5 V, 200 kSPS Throughput 2.7 4.8 mW
VDD = 5 V, 100 kSPS Throughput 4 6 mW
VDD = 5 V, 250 kSPS Throughput 15 mW
TEMPERATURE RANGE3
Specified Performance T
MIN
to T
= VDD, TA = –40°C to +85°C, unless otherwise noted.
REF
Conversion Results Available Immediately
after Completed Conversion
−40 +85 °C
MAX
1
With all digital inputs forced to VIO or GND as required.
2
During acquisition phase.
3
Contact Analog Devices, Inc. for extended temperature range.
Rev Pr I | Page 4 of 28
Preliminary Technical Data AD7687
TIMING SPECIFICATIONS
−40°C to +85°C, VIO = 2.3 V to 5.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated.
Table 4. VDD = 4.5 V to 5.5 V
Conversion Time: CNV Rising Edge to Data Available t
Acquisition Time t
Time between Conversions t
CNV Pulse Width (CS Mode)
SCK Period (CS Mode)
SCK Period (Chain Mode) t
VIO above 4.5 V 19 ns
VIO above 3 V 20 ns
VIO above 2.7 V 21 ns
VIO above 2.3 V 22 ns
SCK Low Time t
SCK High Time t
SCK Falling Edge to Data Remains Valid t
SCK Falling Edge to Data Valid Delay t
VIO above 4.5 V 14 ns
VIO above 3 V 15 ns
VIO above 2.7 V 16 ns
VIO above 2.3 V 17 ns
CNV or SDI Low to SDO D15 MSB Valid (CS Mode)
VIO above 4.5 V 15 ns
VIO above 2.7 V 18 ns
VIO above 2.3 V 22 ns
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
SDI Valid Setup Time from CNV Rising Edge (CS Mode)
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
SCK Valid Setup Time from CNV Rising Edge (Chain Mode) t
SCK Valid Hold Time from CNV Rising Edge (Chain Mode) t
SDI Valid Setup Time from SCK Falling Edge (Chain Mode) t
SDI Valid Hold Time from SCK Falling Edge (Chain Mode) t
SDI High to SDO High (Chain Mode with BUSY indicator) t
VIO above 4.5 V 15 ns
VIO above 2.3 V 26 ns
1
Symbol Min Typ Max Unit
0.5 2.2 µs
CONV
1.8 µs
ACQ
4 µs
CYC
t
10 ns
CNVH
t
15 ns
SCK
SCK
7 ns
SCKL
7 ns
SCKH
5 ns
HSDO
DSDO
t
EN
t
25 ns
DIS
t
15 ns
SSDICNV
t
0 ns
HSDICNV
5 ns
SSCKCNV
5 ns
HSCKCNV
5 ns
SSDISCK
4 ns
HSDISCK
DSDOSDI
1
See and for load conditions. Figure 3 Figure 4
Rev Pr I | Page 5 of 28
AD7687 Preliminary Technical Data
−40°C to +85°C, VIO = 2.3 V to 4.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated.
1
Table 5. VDD = 2.3V to 4.5 V
Conversion Time: CNV Rising Edge to Data Available t
Acquisition Time t
Time between Conversions t
CNV Pulse Width ( CS Mode )
SCK Period ( CS Mode )
SCK Period ( Chain Mode ) t
VIO above 3 V 29 ns
VIO above 2.7 V 35 ns
VIO above 2.3 V 40 ns
SCK Low Time t
SCK High Time t
SCK Falling Edge to Data Remains Valid t
SCK Falling Edge to Data Valid Delay t
VIO above 3 V 24 ns
VIO above 2.7 V 30 ns
VIO above 2.3 V 35 ns
CNV or SDI Low to SDO D15 MSB Valid (CS Mode)
VIO above 2.7 V 18 ns
VIO above 2.3 V 22 ns
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
SDI Valid Setup Time from CNV Rising Edge (CS Mode)
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
SCK Valid Setup Time from CNV Rising Edge (Chain Mode) t
SCK Valid Hold Time from CNV Rising Edge (Chain Mode) t
SDI Valid Setup Time from SCK Falling Edge (Chain Mode) t
SDI Valid Hold Time from SCK Falling Edge (Chain Mode) t
SDI High to SDO High (Chain Mode with BUSY indicator) t
Symbol Min Typ Max Unit
0.7 3.2 µs
CONV
1.8 µs
ACQ
5 µs
CYC
t
10 ns
CNVH
t
25 ns
SCK
SCK
12 ns
SCKL
12 ns
SCKH
5 ns
HSDO
DSDO
t
EN
t
25 ns
DIS
t
30 ns
SSDICNV
t
0 ns
HSDICNV
5 ns
SSCKCNV
8 ns
HSCKCNV
5 ns
SSDISCK
4 ns
HSDISCK
TBD ns
DSDOSDI
1
See and for load conditions. Figure 3 Figure 4
Rev Pr I | Page 6 of 28
Preliminary Technical Data AD7687
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter Rating
Analog Inputs
IN+1, IN−1, REF
GND − 0.3 V to VDD + 0.3 V
or ±130 mA
Supply Voltages
VDD, VIO to GND −0.3 V to +7 V
VDD to VIO ±7 V
Digital Inputs to GND −0.3 V to VIO + 0.3 V
Digital Outputs to GND −0.3 V to VIO + 0.3 V
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
θJA Thermal Impedance 200°C/W (MSOP-10)
θJC Thermal Impedance 44°C/W (MSOP-10)
Lead Temperature Range
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C
1
See the Analog Input section.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
500µAI
TO SDO
Figure 3. Load Circuit for Digital Interface Timing
50pF
C
L
500µAI
30% VIO
t
DELAY
2V OR VIO – 0.5V
0.8V OR 0.5V
NOTES
1. 2V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V.
2. 0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.
Figure 4. Voltage Reference Levels for Timing
OL
1.4V
OH
70% VIO
1
2
02968-PrH-002
t
DELAY
2V OR VIO – 0.5V
0.8V OR 0.5V
1
2
02968-PrH-003
Rev Pr I | Page 7 of 28
AD7687 Preliminary Technical Data
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
REF
2
VDD
3
IN+
AD7687
4
IN–
5
GND
Figure 5.10-Lead MSOP and QFN (LFCSP) Pin Configuration
10
VIO
9
SDI
8
SCK
7
SDO
6
CNV
Table 7. Pin Function Descriptions
Pin No. Mnemonic Type1 Function
1 REF AI
Reference Input Voltage. The REF range is from 0.5 V to VDD. It is referred to the GND pin. This pin should
be decoupled closely to the pin with a 10 µF capacitor.
2 VDD P Power Supply.
3 IN+ AI Differential Positive Analog Input.
4 IN− AI Differential Negative Analog Input.
5 GND P Power Supply Ground.
6 CNV DI
Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and
CS
selects the interface mode of the part, chain or
mode. In CS mode, it enables the SDO pin when low. In
chain mode, the data should be read when CNV is high.
7 SDO DO Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.
8 SCK DI Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock.
9 SDI DI Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as follows:
Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data input to
daisy chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on
SDI is output on SDO with a delay of 16 SCK cycles.
CS
mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable
the serial output signals when low, and if SDI or CNV is low when the conversion is complete, the BUSY
indicator feature is enabled.
10 VIO P
Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V,
or 5 V).
1
AI = Analog Input, DI = Digital Input, DO = Digital Output, and P = Power
Rev Pr I | Page 8 of 28
Preliminary Technical Data AD7687
[
(
)
+
=
TERMINOLOGY
Integral Nonlinearity Error (INL)
Linearity error refers to the deviation of each individual code
from a line drawn from negative full scale through positive full
scale. The point used as negative full scale occurs 1/2 LSB before
the first code transition. Positive full scale is defined as a level 1
1/2 LSB beyond the last code transition. The deviation is
measured from the middle of each code to the true straight line
( ). Figure 25
Differential Nonlinearity Error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. DNL is the
maximum deviation from this ideal value. It is often specified in
terms of resolution for which no missing codes are guaranteed.
Zero Error
Zero error is the difference between the ideal midscale voltage,
i.e., 0 V, from the actual voltage producing the midscale output
code, i.e., 0 LSB.
Gain Error
The first transition (from 100 . . . 00 to 100 . . . 01) should occur
at a level 1/2 LSB above the nominal negative full scale
(−4.999924 V for the ±5 V range). The last transition (from
011…10 to 011…11) should occur for an analog voltage 1 1/2
LSB below the nominal full scale (4.999771 V for the ±5 V
range.) The gain error is the deviation of the difference between
the actual level of the last transition and the actual level of the
first transition from the difference between the idea levels.
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave
input. It is related to S/(N+D) by the following formula
]
DNSENOB
dB
and is expressed in bits.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in dB.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in dB.
Signal-to-(Noise + Distortion) Ratio (S/[N+D])
S/(N+D) is the ratio of the rms value of the actual input signal
to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc. The
value for S/(N+D) is expressed in dB.
Aperture Delay
Aperture delay is a measure of the acquisition performance and
is the time between the rising edge of the CNV input and when
the input signal is held for a conversion.
)02.6/76.1/ −
Spurious-Free Dynamic Range (SFDR)
The difference, in decibels (dB), between the rms amplitude of
the input signal and the peak spurious signal.
Transient Response
The time required for the ADC to accurately acquire its input
after a full-scale step function was applied.
Rev Pr I | Page 9 of 28
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