ANALOG DEVICES AD7687 Service Manual

16-Bit, 1.5 LSB INL, 250 kSPS PulSAR™

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FEATURES

16-bit resolution with no missing codes Throughput: 250 kSPS INL: ±0.4 LSB typ, ±1.5 LSB max (±23 ppm of FSR) Dynamic range: 96.5 dB S/(N + D): 95.5 dB @ 20 kHz THD: −118 dB @ 20 kHz True differential analog input range

±V

REF

0 V to V No pipeline delay Single-supply 2.3 V to 5.5 V operation with

1.8 V/2.5 V/3 V/5 V logic interface Serial interface SPI®/QSPI™/MICROWIRE™/DSP-compatible Daisy-chain multiple ADCs and BUSY indicator Power dissipation

1.35 mW @ 2.5 V/100 kSPS, 4 mW @ 5 V/100 kSPS, and

1.4 µW @ 2.5 V/100 SPS Standby current: 1 nA 10-lead MSOP (MSOP-8 size) and

3 mm × 3 mm QFN

Pin-for-pin compatible with AD7685, AD7686, and AD7688

APPLICATIONS

Battery-powered equipment Data acquisitions Instrumentation Medical instruments Process controls

1.5

1.0

with V

REF

up to VDD on both inputs

REF

1

(LFCSP) (SOT-23 size)

POSITIVE INL = +0.32LSB NEGATIVE INL = –0.41LSB

Differential ADC in MSOP/QFN

AD7687

APPLICATION DIAGRAM

0.5V TO 5V 2.5 TO 5V

VREF

0

VREF

0

IN+ IN–

REF

AD7687

GND

Table 1. MSOP, QFN1 (LFCSP)/SOT-23 16-Bit PulSAR ADC

Type 100 kSPS 250 kSPS 500 kSPS

True Differential AD7684 AD7687 AD7688 Pseudo AD7683 AD7685 AD7686 Differential/Unipolar AD7694 Unipolar AD7680

GENERAL DESCRIPTION

The AD7687 is a 16-bit, charge redistribution, successive approximation, analog-to-digital converter (ADC) that operates from a single power supply, VDD, between 2.3 V to 5.5 V. It contains a low power, high speed, 16-bit sampling ADC with no missing codes, an internal conversion clock, and a versatile serial interface port. The part also contains a low noise, wide bandwidth, short aperture delay track-and-hold circuit. On the CNV rising edge, it samples the voltage difference between IN+ and IN− pins. The voltages on these pins usually swing in opposite phase between 0 V to REF. The reference voltage, REF, is applied externally and can be set up to the supply voltage.

Its power scales linearly with throughput.

VIO

VDD

SDI SCK SDO CNV

Figure 2.

1.8V TO VDD

3- OR 4-WIRE INTERFACE (SPI, DAISY CHAIN, CS)

02972-002

0.5

The SPI-compatible serial interface also features the ability, using the SDI input, to daisy-chain several ADCs on a single,

0

INL (LSB)

–0.5

–1.0

–1.5

0 16384 32768 49152 65535

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Anal og Devices. Trademarks and registered trademarks are the property of their respective owners.

Figure 1. Integral Nonlinearity vs. Code

CODE

02972-001

3-wire bus and provides an optional BUSY indicator. It is compatible with 1.8 V, 2.5 V, 3 V, or 5 V logic, using the separate supply VIO.

The AD7687 is housed in a 10-lead MSOP or a 10-lead QFN (LFCSP) with operation specified from −40°C to +85°C.

1

QFN package in development. Contact sales for samples and availability.

1

AD7687

www.BDTIC.com/ADI

REVISION HISTORY

Supplying the ADC from the Reference.................................. 17

Digital Interface.......................................................................... 17

CS

MODE 3-Wire, No BUSY Indicator .................................. 18

CS

Mode 3-Wire with BUSY Indicator ................................... 19

CS

Mode 4-Wire, No BUSY Indicator..................................... 20

CS

Mode 4-Wire with BUSY Indicator ................................... 21

Chain Mode, No BUSY Indicator ............................................22

Chain Mode with BUSY Indicator........................................... 23

Application Hints ........................................................................... 24

Layout ..........................................................................................24

Evaluating the AD7687’s Performance.................................... 24

Outline Dimensions .......................................................................25

Ordering Guide .......................................................................... 26

4/05—Revision 0: Initial Version

Rev 0 | Page 2 of 28

AD7687

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SPECIFICATIONS

VDD = 2.3 V to 5.5 V, VIO = 2.3 V to VDD, V

Table 2.

Parameter Conditions Min Typ Max Unit

RESOLUTION 16 Bits ANALOG INPUT

Voltage Range IN+ − IN− −V Absolute Input Voltage IN+, IN− −0.1 V Common-Mode Input Range IN+, IN− 0 V Analog Input CMRR fIN = 250 kHz 65 dB Leakage Current at 25°C Acquisition phase 1 nA Input Impedance See the Analog Input section

ACCURACY

No Missing Codes 16 Bits Differential Linearity Error −1 ±0.4 +1 LSB Integral Linearity Error −1.5 ±0.4 +1.5 LSB Transition Noise REF = VDD = 5 V 0.35 LSB Gain Error2, T

MIN

to T

MAX

Gain Error Temperature Drift ±0.3 ppm/°C Offset Error2, T

MIN

to T

MAX

VDD = 2.3 V to 4.5 V ±0.7 ±3.5 mV Offset Temperature Drift ±0.3 ppm/°C Power Supply Sensitivity

THROUGHPUT

Conversion Rate VDD = 4.5 V to 5.5 V 0 250 kSPS VDD = 2.3 V to 4.5 V 0 200 kSPS Transient Response Full-scale step 1.8 µs

AC ACCURACY

Dynamic Range V Signal-to-Noise fIN = 20 kHz, V f Spurious-Free Dynamic Range fIN = 20 kHz −118 dB Total Harmonic Distortion fIN = 20 kHz −118 dB Signal-to-(Noise + Distortion) fIN = 20 kHz, V f f Intermodulation Distortion

1

LSB means least significant bit. With the ±5 V input range, one LSB is 152.6 µV.

2

See the Terminology section. These specifications do include full temperature range variation but do not include the error contribution from the external reference.

3

All specifications in dB are referred to a full-scale input FSR. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified.

4

f

= 21.4 kHz, f

IN1

= 18.9 kHz, each tone at −7 dB below full-scale.

IN2

4

= VDD, TA = –40°C to +85°C, unless otherwise noted.

REF

+V

/2 V

REF

+ 0.1 V

REF

/2 + 0.1 V

REF

V

1

±2 ±6 LSB

VDD = 4.5 V to 5.5 V ±0.1 ±1.6 mV

VDD = 5 V ± 5%

= 5 V 95.8 96.5 dB

REF

= 20 kHz, V

IN

= 20 kHz, V

IN

= 20 kHz, V

IN

= 5 V 94 95.5 dB

REF

= 2.5 V 92 92.5 dB

REF

= 5 V 94 95.5 dB

REF

= 5 V, −60 dB input 36.5 dB

REF

= 2.5 V 92 92.5 dB

REF

±0.05 LSB

3

115 dB

Rev 0 | Page 3 of 28

AD7687

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VDD = 2.3 V to 5.5 V, VIO = 2.3 V to VDD, V

Table 3.

Parameter Conditions Min Typ Max Unit

REFERENCE

Voltage Range 0.5 VDD + 0.3 V Load Current 250 kSPS, REF = 5 V 50 µA

SAMPLING DYNAMICS

−3 dB Input Bandwidth 2 MHz Aperture Delay VDD = 5 V 2.5 ns

DIGITAL INPUTS

Logic Levels

V

IL

V

IH

I

IL

I

IH

−0.3 +0.3 × VIO V

0.7 × VIO VIO + 0.3 V

−1 +1 µA

DIGITAL OUTPUTS

Data Format Serial 16-bits twos complement Pipeline Delay

V

OL

V

OH

I

= +500 µA 0.4 V

SINK

I

= −500 µA VIO − 0.3 V

SOURCE

POWER SUPPLIES

VDD Specified performance 2.3 5.5 V VIO Specified performance 2.3 VDD + 0.3 V VIO Range 1.8 VDD + 0.3 V Standby Current

1, 2

VDD and VIO = 5 V, 25°C 1 50 nA Power Dissipation VDD = 2.5 V, 100 SPS throughput 1.4 µW VDD = 2.5 V, 100 kSPS throughput 1.35 mW VDD = 2.5 V, 200 kSPS throughput 2.7 mW VDD = 5 V, 100 kSPS throughput 4 5.5 mW VDD = 5 V, 250 kSPS throughput 12.5 mW

TEMPERATURE RANGE

Specified Performance T

1

With all digital inputs forced to VIO or GND as required.

2

During acquisition phase.

3

Contact sales for extended temperature range.

3

to T

MIN

= VDD, TA = –40°C to +85°C, unless otherwise noted.

REF

Conversion results available immediately

MAX

−40 +85 °C

after completed

conversion

Rev 0 | Page 4 of 28

AD7687

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TIMING SPECIFICATIONS

−40°C to +85°C, VDD = 4.5 V to 5.5 V, VIO = 2.3 V to 5.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated.

See Figure 3 and Figure 4 for load conditions.

Table 4.

Parameter Symbol Min Typ Max Unit

Conversion Time: CNV Rising Edge to Data Available t Acquisition Time t Time Between Conversions t CNV Pulse Width (CS Mode)

SCK Period (CS Mode) SCK Period (Chain Mode) t

t t

CONV

ACQ

CYC

CNVH

SCK

VIO Above 4.5 V 17 ns VIO Above 3 V 18 ns VIO Above 2.7 V 19 ns

VIO Above 2.3 V 20 ns SCK Low Time t SCK High Time t SCK Falling Edge to Data Remains Valid t SCK Falling Edge to Data Valid Delay t

SCKL

SCKH

HSDO

DSDO

VIO Above 4.5 V 14 ns

VIO Above 3 V 15 ns

VIO Above 2.7 V 16 ns

VIO Above 2.3 V 17 ns CNV or SDI Low to SDO D15 MSB Valid (CS Mode)

t

EN

VIO Above 4.5 V 15 ns

VIO Above 2.7 V 18 ns

VIO Above 2.3 V 22 ns CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode) SDI Valid Setup Time from CNV Rising Edge (CS Mode) SDI Valid Hold Time from CNV Rising Edge (CS Mode) SCK Valid Setup Time from CNV Rising Edge (Chain Mode) t SCK Valid Hold Time from CNV Rising Edge (Chain Mode) t SDI Valid Setup Time from SCK Falling Edge (Chain Mode) t SDI Valid Hold Time from SCK Falling Edge (Chain Mode) t SDI High to SDO High (Chain Mode with BUSY indicator) t

t

DIS

t

SSDICNV

t

HSDICNV

SSCKCNV

HSCKCNV

SSDISCK

HSDISCK

DSDOSDI

VIO Above 4.5 V 15 ns

VIO Above 2.3 V 26 ns

0.5 2.2 µs

1.8 µs 4 µs 10 ns

15 ns

7 ns 7 ns 5 ns

25 ns 15 ns 0 ns 5 ns 5 ns 3 ns 4 ns

Rev 0 | Page 5 of 28

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−40°C to +85°C, VDD = 2.3 V to 4.5 V, VIO = 2.3 V to 4.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated.

See Figure 3 and Figure 4 for load conditions.

Table 5.

Parameter Symbol Min Typ Max Unit

Conversion Time: CNV Rising Edge to Data Available t Acquisition Time t Time Between Conversions t CNV Pulse Width ( CS Mode )

SCK Period ( CS Mode ) SCK Period ( Chain Mode ) t

t t

CONV

ACQ

CYC

CNVH

SCK

VIO Above 3 V 29 ns VIO Above 2.7 V 35 ns

VIO Above 2.3 V 40 ns SCK Low Time t SCK High Time t SCK Falling Edge to Data Remains Valid t SCK Falling Edge to Data Valid Delay t

SCKL

SCKH

HSDO

DSDO

VIO Above 3 V 24 ns

VIO Above 2.7 V 30 ns

VIO Above 2.3 V 35 ns CNV or SDI Low to SDO D15 MSB Valid (CS Mode)

t

EN

VIO Above 2.7 V 18 ns

VIO Above 2.3 V 22 ns CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode) SDI Valid Setup Time from CNV Rising Edge (CS Mode) SDI Valid Hold Time from CNV Rising Edge (CS Mode) SCK Valid Setup Time from CNV Rising Edge (Chain Mode) t SCK Valid Hold Time from CNV Rising Edge (Chain Mode) t SDI Valid Setup Time from SCK Falling Edge (Chain Mode) t SDI Valid Hold Time from SCK Falling Edge (Chain Mode) t SDI High to SDO High (Chain Mode with BUSY indicator) t

t

DIS

t

SSDICNV

t

HSDICNV

SSCKCNV

HSCKCNV

SSDISCK

HSDISCK

DSDOSDI

0.7 3.2 µs

1.8 µs 5 µs 10 ns

25 ns

12 ns 12 ns 5 ns

25 ns 30 ns 0 ns 5 ns 8 ns 5 ns 4 ns 36 ns

Rev 0 | Page 6 of 28

AD7687

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ABSOLUTE MAXIMUM RATINGS

Table 6.

Parameter Rating

Analog Inputs

IN+1, IN−1

GND − 0.3 V to VDD + 0.3 V or ±130 mA

REF GND − 0.3 V to VDD + 0.3 V

Supply Voltages

VDD, VIO to GND −0.3 V to +7 V VDD to VIO ±7 V Digital Inputs to GND −0.3 V to VIO + 0.3 V

Digital Outputs to GND −0.3 V to VIO + 0.3 V Storage Temperature Range −65°C to +150°C Junction Temperature 150°C θJA Thermal Impedance 200°C/W (MSOP-10) θJC Thermal Impedance 44°C/W (MSOP-10) Lead Temperature Range JEDEC J-STD-20

1

See the section. Analog Input

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

500µAI

TO SDO

Figure 3. Load Circuit for Digital Interface Timing

C

50pF

L

500µAI

30% VIO

t

DELAY

2V OR VIO – 0.5V

0.8V OR 0.5V

1

2V IF VIO ABOVE 2.5V, VIO– 0.5V IF VIO BELOW 2.5V.

2

0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.

Figure 4. Voltage Levels for Timing

OL

1.4V

OH

70% VIO

t

1

2

02972-003

DELAY

2V OR VIO – 0.5V

0.8V OR 0.5V

2

1

02972-004

Rev 0 | Page 7 of 28

AD7687

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PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

REF

1 2

VDD

IN+ IN–

GND

Figure 5. 10-Lead MSOP Pin Configuration

AD7687

3

TOP VIEW

(Not to Scale)

4 5

Table 7. Pin Function Descriptions

Pin No. Mnemonic Type1Function

1 REF AI

2 VDD P Power Supply. 3 IN+ AI Differential Positive Analog Input. 4 IN− AI Differential Negative Analog Input. 5 GND P Power Supply Ground. 6 CNV DI

7 SDO DO Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK. 8 SCK DI Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock. 9 SDI DI Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as follows:

10 VIO P

1

AI = Analog Input, DI = Digital Input, DO = Digital Output, and P = Power.

VIO

10

9

SDI SCK

8 7

SDO CNV

6

02972-005

1

QFN package in development. Contact sales for samples and availability.

1REF 2VDD

AD7687

3IN+

TOP VIEW

(Not to Scale)

4IN– 5GND

Figure 6. 10-Lead QFN

10 VIO 9 SDI 8 SCK 7 SDO 6 CNV

1

(LFCSP) Pin Configuration

02972-006

Reference Input Voltage. The REF range is from 0.5 V to VDD. It is referred to the GND pin. This pin should be decoupled closely to the pin with a 10 µF capacitor.

Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and

CS

selects the interface mode, chain or

. In CS mode, it enables the SDO pin when low. In chain mode, the

data should be read when CNV is high.

Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data input to daisy chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on SDI is output on SDO with a delay of 16 SCK cycles.

CS

mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable the serial output signals when low, and if SDI or CNV is low when the conversion is complete, the BUSY indicator feature is enabled.

Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V, or 5 V).

Rev 0 | Page 8 of 28

AD7687

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TERMINOLOGY

Integral Nonlinearity Error (INL)

It refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line (Figure 26).

Differential Nonlinearity Error (DNL)

I

n an ideal ADC, code transitions are 1 LSB apart. DNL is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed.

Zero Error

t is the difference between the ideal midscale voltage, that is, 0

I V, from the actual voltage producing the midscale output code, that is, 0 LSB.

Gain Error

The f

irst transition (from 100 . . . 00 to 100 . . . 01) should occur at a level ½ LSB above nominal negative full scale (−4.999924 V for the ±5 V range). The last transition (from 011…10 to 011…11) should occur for an analog voltage 1½ LSB below the nominal full scale (+4.999771 V for the ±5 V range.) The gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels.

Spurious-Free Dynamic Range (SFDR)

S

FDR is the difference, in decibels (dB), between the rms

amplitude of the input signal and the peak spurious signal.

Effective Number of Bits (ENOB)

EN

OB is a measurement of the resolution with a sine wave

input. It is related to S/(N+D) by the following formula

ENOB = (S

and is expressed in bits.

Total Harmonic Distortion (THD)

HD is the ratio of the rms sum of the first five harmonic

T components to the rms value of a full-scale input signal and is expressed in dB.

Dynamic Range

I

t is the ratio of the rms value of the full scale to the total rms noise measured with the inputs shorted together. The value for dynamic range is expressed in dB.

Signal-to-Noise Ratio (SNR)

S

NR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in dB.

Signal-to-(Noise + Distortion) Ratio (S/[N+D])

S/(N+D) is t to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/(N+D) is expressed in dB.

Aperture Delay

A

perture delay is the measure of the acquisition performance. It is the time between the rising edge of the CNV input and when the input signal is held for a conversion.

/[N + D]

he ratio of the rms value of the actual input signal

− 1.76)/6.02

dB

Transi e nt Res p onse

I

t is the time required for the ADC to accurately acquire its

input after a full-scale step function was applied.

Rev 0 | Page 9 of 28

ANALOG DEVICES AD7687 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

APPLICATION DIAGRAM

GENERAL DESCRIPTION

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

TIMING SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

TERMINOLOGY