Analog Devices AD7685 a Datasheet

16-Bit, 250 kSPS PulSAR™

FEATURES

16-bit resolution with no missing codes Throughput: 250 kSPS INL: ±0.6 LSB typ, ±2 LSB max (±0.003 % of FSR) S/(N + D): 93.5 dB @ 20 kHz THD: −110 dB @ 20 kHz Pseudo differential analog input range

0 V to V

with V

REF

No pipeline delay Single-supply operation 2.3 V to 5.5 V with

1.8 V to 5 V logic interface Serial interface SPI®/QSPI™/MICROWIRE™/DSP-compatible Daisy-chain multiple ADCs, BUSY indicator Power dissipation

1.35 mW @ 2.5 V/100 kSPS, 4 mW @ 5 V/100 kSPS,

1.4 µW @ 2.5 V/100 SPS Standby current: 1 nA 10-lead package: MSOP (MSOP-8 size) and

3 mm × 3 mm QFN

Pin-for-pin compatible with AD7686, AD7687, and AD7688

APPLICATIONS

Battery-powered equipment

Medical instruments Mobile communications

Personal digital assistants Data acquisition Instrumentation Process controls

2.0

1.5

1.0

up to VDD

REF

1

(LFCSP) (SOT-23 size)

POSITIVE INL = +0.33LSB NEGATIVE INL =–0.50LSB

ADC in MSOP/QFN

AD7685

APPLICATION DIAGRAM

0.5V TO VDD 2.5V TO 5V

0 TO VREF

IN+ IN–

REF

AD7685

GND

VDD

VIO

SDI SCK SDO CNV

Figure 2.

Table 1. MSOP, QFN1 (LFCSP)/SOT-23 16-Bit PulSAR ADCs

Type 100 kSPS 250 kSPS 500 kSPS

True Differential AD7684 AD7687 AD7688 Pseudo AD7683 AD7685 AD7686 Differential/Unipolar AD7694 Unipolar AD7680

GENERAL DESCRIPTION

The AD7685 is a 16-bit, charge redistribution successive approximation, analog-to-digital converter (ADC) that operates from a single power supply, VDD, between 2.3 V to 5.5 V. It contains a low power, high speed, 16-bit sampling ADC with no missing codes, an internal conversion clock, and a versatile serial interface port. The part also contains a low noise, wide bandwidth, short aperture delay track-and-hold circuit. On the CNV rising edge, it samples an analog input IN+ between 0 V to REF with respect to a ground sense IN−. The reference voltage, REF, is applied externally and can be set up to the supply voltage.

Power dissipation scales linearly with throughput.

1.8V TO VDD

3- OR 4-WIRE INTERFACE (SPI, DAISY CHAIN, CS)

02968-001

0.5

0

INL (LSB)

–0.5

–1.0

–1.5

–2.0

CODE

Rev A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Anal og Devices. Trademarks and registered trademarks are the property of their respective owners.

Figure 1. Integral Nonlinearity vs. Code.

655360 16384 32768 49152

02968-005

The SPI-compatible serial interface also features the ability, using the SDI input, to daisy chain several ADCs on a single 3-wire bus or provides an optional BUSY indicator. It is compatible with 1.8 V, 2.5 V, 3 V, or 5 V logic using the separate supply VIO.

1

The AD7685 is housed in a 10-lead MSOP or a 10-lead QFN (LFCSP) with operation specified from −40°C to +85°C.

1

QFN package in development. Contact sales for samples and availability.

www.analog.com

AD7685

SPECIFICATIONS

VDD = 2.3 V to 5.5 V, VIO = 2.3 V to VDD, V

Table 2.

A Grade B Grade C Grade Parameter Conditions Min Typ Max Min Typ Max Min Typ Max Unit

RESOLUTION 16 16 16 Bits ANALOG INPUT

Voltage Range IN+ − IN− 0 V Absolute Input Voltage IN+ −0.1 VDD +

IN− −0.1 +0.1 −0.1 +0.1 −0.1 +0.1 V Analog Input CMRR fIN = 250 kHz 65 65 65 dB Leakage Current at 25°C Acquisition Phase 1 1 1 nA Input Impedance See the Analog Input section

ACCURACY

No Missing Codes 15 16 16 Bits Differential Linearity Error −1 ±0.7 −1 ±0.5 +1.5 LSB Integral Linearity Error −6 +6 −3 ±1 +3 −2 ±0.6 +2 LSB Transition Noise REF = VDD = 5 V 0.5 0.5 0.45 LSB Gain Error2, T Gain Error Temperature

MIN

to T

MAX

±2 ±30 ±2 ±30 ±2 ±15 LSB ±0.3 ±0.3 ±0.3 ppm/°C

Drift

Offset Error2, T

to T

MIN

MAX

VDD = 4.5 V to 5.5 V ±0.1 ±1.6 ±0.1 ±1.6 ±0.1 ±1.6 mV VDD = 2.3 V to 4.5 V ±0.7 ±3.5 ±0.7 ±3.5 ±0.7 ±3.5 mV Offset Temperature Drift ±0.3 ±0.3 ±0.3 ppm/°C Power Supply Sensitivity VDD = 5 V ± 5% ±0.05 ±0.05 ±0.05 LSB

THROUGHPUT

Conversion Rate VDD = 4.5 V to 5.5 V 0 250 0 250 0 250 kSPS VDD = 2.3 V to 4.5 V 0 200 0 200 0 200 kSPS Transient Response Full-Scale Step 1.8 1.8 1.8 µs

AC ACCURACY

Signal-to-Noise fIN = 20 kHz,

= 5 V

V

REF

f

Spurious-Free Dynamic

= 20 kHz,

IN

= 2.5 V

V

REF

fIN = 20 kHz −100 −106 −110 dB

Range Total Harmonic Distortion fIN = 20 kHz −100 −106 −110 dB Signal-to-(Noise +

Distortion) f

fIN = 20 kHz,

= 5 V

V

REF

= 20 kHz,

IN

V

= 5 V,

REF

−60 dB Input

f

= 20 kHz,

IN

= 2.5 V

V

REF

Intermodulation Distortion4 −110 −115 dB

1

LSB means least significant bit. With the 5 V input range, 1 LSB is 76.3 µV.

2

See section. These specifications do include full temperature range variation but do not include the error contribution from the external reference. Terminology

3

All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified.

4

f

= 21.4 kHz, f

IN1

= 18.9 kHz, each tone at −7 dB below full scale.

IN2

= VDD, TA = –40°C to +85°C, unless otherwise noted.

REF

0 V

−0.1 VDD +

0.1

90 90 92 91.5 93.5 dB

86 86 88 87.5 88.5 dB

89 90 92 91.5 93.5 dB

32 33.5 dB

86 85.5 87.5 87 88.5 dB

REF

0 V

REF

−0.1 VDD +

V V

0.1

1

3

Rev A | Page 3 of 28

AD7685

VDD = 2.3 V to 5.5 V, VIO = 2.3 V to VDD, V

Table 3.

Parameter Conditions Min Typ Max Unit

REFERENCE

Voltage Range 0.5 VDD + 0.3 V Load Current 250 kSPS, REF = 5 V 50 µA

SAMPLING DYNAMICS

−3 dB Input Bandwidth 2 MHz Aperture Delay VDD = 5 V 2.5 ns

DIGITAL INPUTS

Logic Levels

V

IL

V

IH

I

IL

I

IH

–0.3 0.3 × VIO V

0.7 × VIO VIO + 0.3 V

−1 +1 µA

DIGITAL OUTPUTS

Data Format Serial 16 Bits Straight Binary Pipeline Delay

V

OL

V

OH

I

= +500 µA 0.4 V

SINK

I

= −500 µA VIO − 0.3 V

SOURCE

POWER SUPPLIES

VDD Specified Performance 2.3 5.5 V VIO Specified Performance 2.3 VDD + 0.3 V VIO Range 1.8 VDD + 0.3 V Standby Current

1, 2

VDD and VIO = 5 V, 25°C 1 50 nA Power Dissipation VDD = 2.5 V, 100 SPS Throughput 1.4 µW VDD = 2.5 V, 100 kSPS Throughput 1.35 2.4 mW VDD = 2.5 V, 200 kSPS Throughput 2.7 4.8 mW VDD = 5 V, 100 kSPS Throughput 4 6 mW VDD = 5 V, 250 kSPS Throughput 15 mW

TEMPERATURE RANGE

Specified Performance T

3

to T

MIN

1

With all digital inputs forced to VIO or GND as required.

2

During acquisition phase.

3

Contact sales for extended temperature range.

= VDD, TA = –40°C to +85°C, unless otherwise noted.

REF

Conversion Results Available Immediately

MAX

−40 +85 °C

after Completed Conversion

Rev A | Page 4 of 28

AD7685

TIMING SPECIFICATIONS

−40°C to +85°C, VIO = 2.3 V to 5.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated.

Table 4. VDD = 4.5 V to 5.5 V

Conversion Time: CNV Rising Edge to Data Available t Acquisition Time t Time between Conversions t CNV Pulse Width (CS Mode) SCK Period (CS Mode) SCK Period (Chain Mode) t

VIO above 4.5 V 17 ns VIO above 3 V 18 ns VIO above 2.7 V 19 ns

VIO above 2.3 V 20 ns SCK Low Time t SCK High Time t SCK Falling Edge to Data Remains Valid t SCK Falling Edge to Data Valid Delay t

VIO above 4.5 V 14 ns

VIO above 3 V 15 ns

VIO above 2.7 V 16 ns

VIO above 2.3 V 17 ns CNV or SDI Low to SDO D15 MSB Valid (CS Mode)

VIO above 4.5 V 15 ns

VIO above 2.7 V 18 ns

VIO above 2.3 V 22 ns CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode) SDI Valid Setup Time from CNV Rising Edge (CS Mode) SDI Valid Hold Time from CNV Rising Edge (CS Mode) SCK Valid Setup Time from CNV Rising Edge (Chain Mode) t SCK Valid Hold Time from CNV Rising Edge (Chain Mode) t SDI Valid Setup Time from SCK Falling Edge (Chain Mode) t SDI Valid Hold Time from SCK Falling Edge (Chain Mode) t SDI High to SDO High (Chain Mode with BUSY Indicator) t

VIO above 4.5 V 15 ns

VIO above 2.3 V 26 ns

1

See and for load conditions. Figure 3 Figure 4

1

Symbol Min Typ Max Unit

CONV

ACQ

CYC

t

CNVH

t

SCK

SCKL

SCKH

HSDO

DSDO

t

EN

t

DIS

t

SSDICNV

t

HSDICNV

SSCKCNV

HSCKCNV

SSDISCK

HSDISCK

DSDOSDI

0.5 2.2 µs

1.8 µs 4 µs 10 ns 15 ns

7 ns 7 ns 5 ns

25 ns 15 ns 0 ns 5 ns

5 ns 3 ns 4 ns

Rev A | Page 5 of 28

AD7685

−40°C to +85°C, VIO = 2.3 V to 4.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated.

Table 5. VDD = 2.3V to 4.5 V

Conversion Time: CNV Rising Edge to Data Available t Acquisition Time t Time between Conversions t CNV Pulse Width ( CS Mode ) SCK Period ( CS Mode ) SCK Period ( Chain Mode ) t

VIO above 3 V 29 ns VIO above 2.7 V 35 ns

VIO above 2.3 V 40 ns SCK Low Time t SCK High Time t SCK Falling Edge to Data Remains Valid t SCK Falling Edge to Data Valid Delay t

VIO above 3 V 24 ns

VIO above 2.7 V 30 ns

VIO above 2.3 V 35 ns CNV or SDI Low to SDO D15 MSB Valid (CS Mode)

VIO above 2.7 V 18 ns

VIO above 2.3 V 22 ns CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode) SDI Valid Setup Time from CNV Rising Edge (CS Mode) SDI Valid Hold Time from CNV Rising Edge (CS Mode) SCK Valid Setup Time from CNV Rising Edge (Chain Mode) t SCK Valid Hold Time from CNV Rising Edge (Chain Mode) t SDI Valid Setup Time from SCK Falling Edge (Chain Mode) t SDI Valid Hold Time from SCK Falling Edge (Chain Mode) t SDI High to SDO High (Chain Mode with BUSY Indicator) t

1

See and for load conditions. Figure 3 Figure 4

1

Symbol Min Typ Max Unit

CONV

ACQ

CYC

t

CNVH

t

SCK

SCKL

SCKH

HSDO

DSDO

t

EN

t

DIS

t

SSDICNV

t

HSDICNV

SSCKCNV

HSCKCNV

SSDISCK

HSDISCK

DSDOSDI

0.7 3.2 µs

1.8 µs 5 µs 10 ns 25 ns

12 ns 12 ns 5 ns

25 ns 30 ns 0 ns 5 ns

8 ns 5 ns 4 ns 36 ns

Rev A | Page 6 of 28

AD7685

ABSOLUTE MAXIMUM RATINGS

Table 6.

Parameter Ratings

Analog Inputs

IN+1, IN−1, REF

GND − 0.3 V to VDD + 0.3 V or ±130 mA

Supply Voltages

VDD, VIO to GND −0.3 V to +7 V

VDD to VIO ±7 V Digital Inputs to GND −0.3 V to VIO + 0.3 V Digital Outputs to GND −0.3 V to VIO + 0.3 V Storage Temperature Range −65°C to +150°C Junction Temperature 150°C θJA Thermal Impedance 200°C/W (MSOP-10) θJC Thermal Impedance 44°C/W (MSOP-10) Lead Temperature Range

Vapor Phase (60 sec) 215°C

Infrared (15 sec) 220°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

1

See the section. Analog Input

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

500µAI

TO SDO

Figure 3. Load Circuit for Digital Interface Timing

50pF

C

L

500µAI

30% VIO

t

DELAY

2V OR VIO – 0.5V

0.8V OR 0.5V

NOTES:

1. 2V IF VIO ABOVE 2.5V, VIO– 0.5V IF VIO BELOW 2.5V.

2. 0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.

Figure 4. Voltage Levels for Timing

OL

1.4V

OH

70% VIO

1

2

02968-002

t

DELAY

2V OR VIO – 0.5V

0.8V OR 0.5V

1

2

02968-003

Rev A | Page 7 of 28

AD7685

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

REF

2

VDD

IN+

3

AD7685

IN–

4

GND

5

Figure 5. 10-Lead MSOP and QFN

10

VIO

9

SDI SCK

8

SDO

7

CNV

6

1

(LFCSP) Pin Configuration

02968-004

Table 7. Pin Function Descriptions

Pin No.

Mnemonic Type

1 REF AI

2

Function

Reference Input Voltage. The REF range is from 0.5 V to VDD. It is referred to the GND pin. This pin should be

decoupled closely to the pin with a 10 µF capacitor. 2 VDD P Power Supply. 3 IN+ AI Analog Input. It is referred to IN−. The voltage range, i.e., the difference between IN+ and IN−, is 0 V to V

REF

. 4 IN− AI Analog Input Ground Sense. To be connected to the analog ground plane or to a remote sense ground. 5 GND P Power Supply Ground. 6 CNV DI

Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and selects the interface mode of the part, chain, or

CS mode. In CS mode, it enables the SDO pin when low. In chain

mode, the data should be read when CNV is high. 7 SDO DO Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK. 8 SCK DI Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock. 9 SDI DI Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as follows:

Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data input to

daisy chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on SDI is

output on SDO with a delay of 16 SCK cycles.

CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable the

serial output signals when low, and if SDI or CNV is low when the conversion is complete, the BUSY indicator

feature is enabled. 10 VIO P Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V, or 5 V).

1

QFN package in development. Contact sales for samples and availability.

2

AI = Analog Input, DI = Digital Input, DO = Digital Output, and P = Power.

Rev A | Page 8 of 28

AD7685

[

(

)

+

=

TERMINOLOGY

Integral Nonlinearity Error (INL)

It refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs 1/2 LSB before the first code transition. Positive full scale is defined as a level 1 1/2 LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line (Figure 25).

Differential Nonlinearity Error (DNL)

In an ideal ADC, code transitions are 1 LSB apart. DNL is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed.

Offset Error

The first transition should occur at a level 1/2 LSB above analog ground (38.1 µV for the 0 V to 5 V range). The offset error is the deviation of the actual transition from that point.

Gain Error

The last transition (from 111 . . . 10 to 111 . . . 11) should occur for an analog voltage 1 1/2 LSB below the nominal full scale (4.999886 V for the 0 V to 5 V range). The gain error is the deviation of the actual level of the last transition from the ideal level after the offset has been adjusted out.

Spurious-Free Dynamic Range (SFDR)

The difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal.

Effective Number of Bits (ENOB)

ENOB is a measurement of the resolution with a sine wave input. It is related to S/(N+D) by the following formula

]

DNSENOB

dB

and is expressed in bits.

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in dB.

Signal-to-Noise Ratio (SNR)

SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in dB.

Signal-to-(Noise + Distortion) Ratio (S/[N+D])

S/(N+D) is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/(N+D) is expressed in dB.

Aperture Delay

Aperture delay is a measure of the acquisition performance and is the time between the rising edge of the CNV input and when the input signal is held for a conversion.

/6.021.76/

−

Transient Response

The time required for the ADC to accurately acquire its input after a full-scale step function was applied.

Rev A | Page 9 of 28

Analog Devices AD7685 a Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

APPLICATION DIAGRAM

GENERAL DESCRIPTION

TABLE OF CONTENTS

SPECIFICATIONS

TIMING SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TERMINOLOGY