ANALOG DEVICES AD7685 Service Manual

16-Bit, 250 kSPS PulSAR

FEATURES

16-bit resolution with no missing codes Throughput: 250 kSPS INL: ±0.6 LSB typical, ±2 LSB maximum (±0.003% of FSR) SINAD: 93.5 dB @ 20 kHz THD: −110 dB @ 20 kHz Pseudo differential analog input range

0 V to V No pipeline delay Single-supply operation 2.3 V to 5.5 V with

1.8 V to 5 V logic interface Serial interface SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible Daisy-chain multiple ADCs, BUSY indicator Power dissipation

1.4 μW @ 2.5 V/100 SPS

1.35 mW @ 2.5 V/100 kSPS, 4 mW @ 5 V/100 kSPS Standby current: 1 nA 10-lead package: MSOP (MSOP-8 size) and

3 mm × 3 mm QFN (LFCSP) (SOT-23 size)

Pin-for-pin-compatible with 10-lead MSOP/QFN PulSAR® ADCs

APPLICATIONS

Battery-powered equipment

Medical instruments Mobile communications

Personal digital assistants (PDAs) Data acquisition Instrumentation Process controls

INL (LSB)

2.0

1.5

1.0

0.5

–0.5

–1.0

–1.5

–2.0

with V

REF

0

up to VDD

REF

POSITIVE INL = +0.33LSB NEGATIVE INL = –0.50LSB

CODE

Figure 1. Integral Nonlinearity vs. Code.

655360 16384 32768 49152

02968-005

ADC in MSOP/QFN

AD7685

APPLICATION DIAGRAM

0.5VTO VDD 2.5VTO 5V

0 TO VREF

IN+

IN–

REF

AD7685

GND

VDD

Figure 2.

VIO

SDI

SCK

SDO

CNV

Table 1. MSOP, QFN (LFCSP)/SOT-23 14-/16-/18-Bit PulSAR ADC

Type

18-Bit True AD7691 AD7690 AD7982 ADA4941

Differential AD7982 ADA4841

16-Bit True AD7684 AD7687 AD7688 ADA4941

Differential AD7693 ADA4841

16-Bit Pseudo AD7680 AD7685 AD7686 AD7980 ADA4841

Differential AD7683 AD7694

14-Bit Pseudo AD7940 AD7942 AD7946 ADA4841

Differential

100 kSPS

250 kSPS

GENERAL DESCRIPTION

The AD7685 is a 16-bit, charge redistribution successive approximation, analog-to-digital converter (ADC) that operates from a single power supply, VDD, between 2.3 V to 5.5 V. It contains a low power, high speed, 16-bit sampling ADC with no missing codes, an internal conversion clock, and a versatile serial interface port. The part also contains a low noise, wide bandwidth, short aperture delay, track-and-hold circuit. On the CNV rising edge, it samples an analog input IN+ between 0 V to REF with respect to a ground sense IN−. The reference voltage, REF, is applied externally and can be set up to the supply voltage.

Power dissipation scales linearly with throughput. The SPI-compatible serial interface also features the ability,

using the SDI input, to daisy chain several ADCs on a single 3-wire bus or provides an optional BUSY indicator. It is compatible with 1.8 V, 2.5 V, 3 V, or 5 V logic using the separate supply VIO.

The AD7685 is housed in a 10-lead MSOP or a 10-lead QFN (LFCSP) with operation specified from −40°C to +85°C.

1.8V TO VDD

400 kSPS to 500 kSPS

3- OR 4-WIRE I NTERFACE (SPI, DAISY CHAIN, CS)

1000 kSPS

ADC Driver

02968-001

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD7685

REVISION HISTORY

8/11—Rev. B to Rev. C

Changes to Figure 6 and Table 7..................................................... 8

Updated Outline Dimensions....................................................... 26

Changes to Ordering Guide.......................................................... 27

3/07—Rev. A to Rev. B

Changes to Features and Table 1 .................................................... 1

Changes to Table 3............................................................................ 4

Moved Figure 3 and Figure 4 to Page............................................. 6

Inserted Figure 6; Renumbered Sequentially................................ 8

Changes to Figure 13 and Figure 14............................................. 11

Changes to Figure 27...................................................................... 14

Changes to Table 9.......................................................................... 16

Changes to Figure 32...................................................................... 17

Changes to Figure 43...................................................................... 22

Changes to Figure 45...................................................................... 23

Updated Outline Dimensions....................................................... 26

Changes to Ordering Guide.......................................................... 27

12/04—Rev. 0 to Rev. A

Changes to Specifications.................................................................3

Changes to Figure 17 Captions..................................................... 11

Changes to Power Supply Section................................................ 17

Changes to Digital Interface Section ........................................... 18

Changes to Changes to

Changes to Chain Mode, No Busy Indicator Section................ 23

Changes to Chain Mode with Busy Indicator Section .............. 24

Added True 16-Bit Isolated Application Example Section ....... 26

Added Figure 47 ............................................................................. 26

Changes to Ordering Guide.......................................................... 28

4/04—Revision 0: Initial Revision

Mode 4-Wire No Busy Indicator Section ......... 21

CS

Mode 4-Wire with Busy Indicator Section....... 22

CS

Rev. C | Page 2 of 28

AD7685

SPECIFICATIONS

VDD = 2.3 V to 5.5 V, VIO = 2.3 V to VDD, V

Table 2.

A Grade B Grade C Grade Parameter Conditions Min Typ Max Min Typ Max Min Typ Max Unit

RESOLUTION 16 16 16 Bits ANALOG INPUT

Voltage Range IN+ − IN− 0 V Absolute Input Voltage IN+ −0.1 VDD +

IN− −0.1 +0.1 −0.1 +0.1 −0.1 +0.1 V Analog Input CMRR fIN = 250 kHz 65 65 65 dB Leakage Current at 25°C Acquisition phase 1 1 1 nA Input Impedance See the

ACCURACY

No Missing Codes 15 16 16 Bits Differential Linearity Error −1 ±0.7 −1 ±0.5 +1.5 LSB1 Integral Linearity Error −6 +6 −3 ±1 +3 −2 ±0.6 +2 LSB Transition Noise REF = VDD = 5 V 0.5 0.5 0.45 LSB Gain Error2, T Gain Error Temperature Drift ±0.3 ±0.3 ±0.3 ppm/°C Offset Error2, T VDD = 2.3 V to 4.5 V ±0.7 ±3.5 ±0.7 ±3.5 ±0.7 ±3.5 mV Offset Temperature Drift ±0.3 ±0.3 ±0.3 ppm/°C Power Supply Sensitivity VDD = 5 V ± 5% ±0.05 ±0.05 ±0.05 LSB

THROUGHPUT

Conversion Rate VDD = 4.5 V to 5.5 V 0 250 0 250 0 250 kSPS VDD = 2.3 V to 4.5 V 0 200 0 200 0 200 kSPS Transient Response Full-scale step 1.8 1.8 1.8 μs

AC ACCURACY

Signal-to-Noise Ratio fIN = 20 kHz,

f

Spurious-Free Dynamic

Range Total Harmonic Distortion fIN = 20 kHz −100 −106 −110 dB Signal-to-(Noise + Distortion) fIN = 20 kHz,

f

Intermodulation Distortion4 −110 −115 dB

1

LSB means least significant bit. With the 5 V input range, 1 LSB is 76.3 μV.

2

See Terminology section. These specifications do include full temperature range variation but do not include the error contribution from the external reference.

3

All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified.

4

f

= 21.4 kHz, f

IN1

to T

MIN

±2 ±30 ±2 ±30 ±2 ±15 LSB

MAX

to T

MAX

VDD = 4.5 V to 5.5 V ±0.1 ±1.6 ±0.1 ±1.6 ±0.1 ±1.6 mV

= 5 V

V

REF

= 20 kHz,

IN

= 2.5 V

V

REF

fIN = 20 kHz −100 −106 −110 dB

= 5 V

V

REF

= 20 kHz,

IN

= 5 V,

V

REF

−60 dB input = 20 kHz,

IN

= 2.5 V

V

REF

= 18.9 kHz, each tone at −7 dB below full scale.

IN2

= VDD, TA = –40°C to +85°C, unless otherwise noted.

REF

0 V

REF

0.1

Analog Inputs section

−0.1 VDD +

See the

Analog Inputs section

0 V

REF

−0.1 VDD +

0.1

See the

Analog Inputs section

REF

0.1

90 90 92 91.5 93.5 dB

86 86 88 87.5 88.5 dB

89 90 92 91.5 93.5 dB

32 33.5 dB

86 85.5 87.5 87 88.5 dB

V

3

Rev. C | Page 3 of 28

AD7685

VDD = 2.3 V to 5.5 V, VIO = 2.3 V to VDD, V

Table 3.

Parameter Conditions Min Typ Max Unit

REFERENCE

Voltage Range 0.5 VDD + 0.3 V Load Current 250 kSPS, REF = 5 V 50 μA

SAMPLING DYNAMICS

−3 dB Input Bandwidth 2 MHz Aperture Delay VDD = 5 V 2.5 ns

DIGITAL INPUTS

Logic Levels

VIL –0.3 0.3 × VIO V VIH 0.7 × VIO VIO + 0.3 V IIL −1 +1 μA IIH −1 +1 μA

DIGITAL OUTPUTS

Data Format Serial 16 bits straight binary Pipeline Delay

VOL I VOH I

= +500 μA 0.4 V

SINK

= −500 μA VIO − 0.3 V

SOURCE

POWER SUPPLIES

VDD Specified performance 2.3 5.5 V VIO Specified performance 2.3 VDD + 0.3 V VIO Range 1.8 VDD + 0.3 V Standby Current

1, 2

VDD and VIO = 5 V, 25°C 1 50 nA Power Dissipation VDD = 2.5 V, 100 SPS throughput 1.4 μW VDD = 2.5 V, 100 kSPS throughput 1.35 2.4 mW VDD = 2.5 V, 200 kSPS throughput 2.7 4.8 mW VDD = 5 V, 100 kSPS throughput 4 6 mW VDD = 5 V, 250 kSPS throughput 10 15 mW

TEMPERATURE RANGE3

Specified Performance T

1

With all digital inputs forced to VIO or GND as required.

2

During acquisition phase.

3

Contact sales for extended temperature range.

MIN

to T

= VDD, TA = –40°C to +85°C, unless otherwise noted.

REF

Conversion results available immediately

after completed conversion

−40 +85 °C

MAX

Rev. C | Page 4 of 28

AD7685

TIMING SPECIFICATIONS

−40°C to +85°C, VIO = 2.3 V to 5.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated.

Table 4. VDD = 4.5 V to 5.5 V

Parameter Symbol Min Typ Max Unit

Conversion Time: CNV Rising Edge To Data Available t Acquisition Time t Time Between Conversions t CNV Pulse Width (CS Mode)

SCK Period (CS Mode) SCK Period (Chain Mode) t

VIO Above 4.5 V 17 ns VIO Above 3 V 18 ns VIO Above 2.7 V 19 ns

VIO Above 2.3 V 20 ns SCK Low Time t SCK High Time t SCK Falling Edge to Data Remains Valid t SCK Falling Edge to Data Valid Delay t

VIO Above 4.5 V 14 ns

VIO Above 3 V 15 ns

VIO Above 2.7 V 16 ns

VIO Above 2.3 V 17 ns CNV or SDI Low to SDO D15 MSB Valid (CS Mode)

VIO Above 4.5 V 15 ns

VIO Above 2.7 V 18 ns

VIO Above 2.3 V 22 ns CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode) SDI Valid Setup Time from CNV Rising Edge (CS Mode) SDI Valid Hold Time from CNV Rising Edge (CS Mode) SCK Valid Setup Time from CNV Rising Edge (Chain Mode) t SCK Valid Hold Time from CNV Rising Edge (Chain Mode) t SDI Valid Setup Time from SCK Falling Edge (Chain Mode) t SDI Valid Hold Time from SCK Falling Edge (Chain Mode) t SDI High to SDO High (Chain Mode with Busy Indicator) t

VIO Above 4.5 V 15 ns

VIO Above 2.3 V 26 ns

1

See Figure 3 and Figure 4 for load conditions.

1

0.5 2.2 μs

CONV

1.8 μs

ACQ

4 μs

CYC

t

10 ns

CNVH

t

15 ns

SCK

7 ns

SCKL

7 ns

SCKH

5 ns

HSDO

DSDO

t

EN

t

25 ns

DIS

t

15 ns

SSDICNV

t

0 ns

HSDICNV

5 ns

SSCKCNV

5 ns

HSCKCNV

3 ns

SSDISCK

4 ns

HSDISCK

DSDOSDI

Rev. C | Page 5 of 28

AD7685

−40°C to +85°C, VIO = 2.3 V to 4.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated.

Table 5. VDD = 2.3V to 4.5 V

Parameter Symbol Min Typ Max Unit

Conversion Time: CNV Rising Edge to Data Available t Acquisition Time t Time Between Conversions t CNV Pulse Width (CS Mode) SCK Period (CS Mode) SCK Period (Chain Mode) t

VIO Above 3 V 29 ns VIO Above 2.7 V 35 ns

VIO Above 2.3 V 40 ns SCK Low Time t SCK High Time t SCK Falling Edge to Data Remains Valid t SCK Falling Edge to Data Valid Delay t

VIO Above 3 V 24 ns

VIO Above 2.7 V 30 ns

VIO Above 2.3 V 35 ns CNV or SDI Low to SDO D15 MSB Valid (CS Mode)

VIO Above 2.7 V 18 ns

VIO Above 2.3 V 22 ns CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode) SDI Valid Setup Time from CNV Rising Edge (CS Mode) SDI Valid Hold Time from CNV Rising Edge (CS Mode) SCK Valid Setup Time from CNV Rising Edge (Chain Mode) t SCK Valid Hold Time from CNV Rising Edge (Chain Mode) t SDI Valid Setup Time from SCK Falling Edge (Chain Mode) t SDI Valid Hold Time from SCK Falling Edge (Chain Mode) t SDI High to SDO High (Chain Mode with Busy Indicator) t

1

See Figure 3 and Figure 4 for load conditions.

1

0.7 3.2 μs

CONV

1.8 μs

ACQ

5 μs

CYC

t

10 ns

CNVH

t

25 ns

SCK

12 ns

SCKL

12 ns

SCKH

5 ns

HSDO

DSDO

t

EN

t

25 ns

DIS

t

30 ns

SSDICNV

t

0 ns

HSDICNV

5 ns

SSCKCNV

8 ns

HSCKCNV

5 ns

SSDISCK

4 ns

HSDISCK

36 ns

DSDOSDI

70% VIO

t

DELAY

1

2

2V OR VIO – 0.5V

0.8V OR 0.5V

1

2

02968-003

TO SDO

50pF

C

L

500µA I

OL

1.4V

OH

02968-002

Figure 3. Load Circuit for Digital Interface Timing

30% VIO

t

DELAY

2V OR VIO – 0.5V

0.8V OR 0.5V

NOTES

1. 2V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V.

2. 0.8V IF VI O ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.

Figure 4. Voltage Levels for Timing

Rev. C | Page 6 of 28

AD7685

ABSOLUTE MAXIMUM RATINGS

Table 6.

Parameter Rating

Analog Inputs

IN+1, IN−1, REF

Supply Voltages

VDD, VIO to GND −0.3 V to +7 V

VDD to VIO ±7 V Digital Inputs to GND −0.3 V to VIO + 0.3 V Digital Outputs to GND −0.3 V to VIO + 0.3 V Storage Temperature Range −65°C to +150°C Junction Temperature 150°C θJA Thermal Impedance 200°C/W (MSOP-10) θJC Thermal Impedance 44°C/W (MSOP-10) Lead Temperature

Vapor Phase (60 sec) 215°C

Infrared (15 sec) 220°C

1

See the Analog Inputs section.

GND − 0.3 V to VDD + 0.3 V or ±130 mA

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. C | Page 7 of 28

AD7685

T

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

REF

VDD

IN+

IN–

GND

1

2

AD7685

3

TOP VIEW

(Not to Scale)

4

5

VIO

10

SDI

9

SCK

8

7

SDO

CNV

6

02968-004

Figure 5. 10-Lead MSOP Pin Configuration

1REF

2VDD

AD7685

3IN+

TOP VIEW

(Not to Scale)

4IN–

5GND

NOTES

1. EXPOSED PAD CONNECTED TO GND. THIS CONNECTI ON IS NO T REQUI RED TO MEE THE ELECTRICAL PERFORMANCES.

Figure 6. 10-Lead QFN (LFCSP) Pin Configuration

10 VIO

9SDI

8SCK

7SDO

6CNV

02968-005

Table 7. Pin Function Descriptions

Pin No Mnemonic Type1 Description

1 REF AI

Reference Input Voltage. The REF range is from 0.5 V to VDD. It is referred to the GND pin. This pin should

be decoupled closely to the pin with a 10 μF capacitor. 2 VDD P Power Supply. 3 IN+ AI Analog Input. It is referred to IN−. The voltage range, that is, the difference between IN+ and IN−, is 0 V to V

.

REF

4 IN− AI Analog Input Ground Sense. Connect to the analog ground plane or to a remote sense ground. 5 GND P Power Supply Ground. 6 CNV DI

Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and

selects the interface mode of the part, chain, or CS

mode. In CS mode, it enables the SDO pin when low.

In chain mode, the data should be read when CNV is high. 7 SDO DO Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK. 8 SCK DI Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock. 9 SDI DI Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as follows:

Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data input

to daisy chain the conversion results of two or more ADCs onto a single SDO line. The digital data level

on SDI is output on SDO with a delay of 16 SCK cycles.

CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable

the serial output signals when low, and if SDI or CNV is low when the conversion is complete, the BUSY

indicator feature is enabled. 10 VIO P Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V, or 5 V). EPAD

Exposed Pad. Exposed pad connected to GND. This connection is not required to meet the electrical

performances.

1

AI = analog input, DI = digital input, DO = digital output, and P = power.

Rev. C | Page 8 of 28

AD7685

TERMINOLOGY

Integral Nonlinearity Error (INL)

INL refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line (see Figure 26).

Differential Nonlinearity Error (DNL)

In an ideal ADC, code transitions are 1 LSB apart. DNL is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed.

Offset Error

The first transition should occur at a level ½ LSB above analog ground (38.1 μV for the 0 V to 5 V range). The offset error is the deviation of the actual transition from that point.

Gain Error

The last transition (from 111 . . . 10 to 111 . . . 11) should occur for an analog voltage 1½ LSB below the nominal full scale (4.999886 V for the 0 V to 5 V range). The gain error is the deviation of the actual level of the last transition from the ideal level after the offset is adjusted out.

Spurious-Free Dynamic Range (SFDR)

The difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal.

Effective Number of Bits (ENOB)

ENOB is a measurement of the resolution with a sine wave input. It is related to SINAD by

ENOB = (SINAD

and is expressed in bits.

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in dB.

Signal-to-Noise Ratio (SNR)

SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in dB.

Signal-to-(Noise + Distortion), SINAD

SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in dB.

Aperture Delay

Aperture delay is a measure of the acquisition performance and is the time between the rising edge of the CNV input and when the input signal is held for a conversion.

Transi ent Res p ons e

The time required for the ADC to accurately acquire its input after a full-scale step function is applied.

− 1.76)/6.02

dB

Rev. C | Page 9 of 28

ANALOG DEVICES AD7685 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

APPLICATION DIAGRAM

GENERAL DESCRIPTION

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

TIMING SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TERMINOLOGY