The AD7683 is a 16-bit, charge redistribution, successive
approximation, PulSAR™ analog-to-digital converter (ADC)
that operates from a single power supply, VDD, between 2.7 V
to 5.5 V. It contains a low power, high speed, 16-bit sampling
ADC with no missing codes (B grade), an internal conversion
clock, and a serial, SPI-compatible interface port. The part also
contains a low noise, wide bandwidth, short aperture delay,
track-and-hold circuit. On the
analog input, +IN, between 0 V to REF with respect to a ground
sense, –IN. The reference voltage, REF, is applied externally and
can be set up to the supply voltage. Its power scales linearly with
throughput.
VDD
DCLOCK
AD7683
GND
Figure 1.
D
OUT
CS
AD7685
AD7694
falling edge, it samples an
CS
3-WIRE SPI
INTERFACE
AD7686
04301-001
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Anal og Devices. Trademarks and
registered trademarks are the property of their respective owners.
The AD7683 is housed in an 8-lead MSOP or an 8-lead QFN
(LFCSP) package, with an operating temperature specified from
−40°C to +85°C.
1
QFN package in development. Contact factory for samples and availability.
= VDD; TA = –40°C to +85°C, unless otherwise noted.
REF
− V
= V
+IN
−IN
/2 = 2.5 V 50 µA
REF
−0.3 0.3 × VDD V
0.7 × VDD VDD + 0.3 V
−1 +1 µA
−1 +1 µA
I
= −500 µA VDD − 0.3 V
SOURCE
I
= +500 µA 0.4 V
SINK
2.0 5.5 V
2, 3
VDD = 5 V, 25°C
to T
MIN
MAX
REF
V
1 50 nA
−40 +85
°C
1
See the section for more information. Typical Performance Characteristics
2
With all digital inputs forced to VDD or GND, as required.
3
During acquisition phase.
Rev. 0 | Page 3 of 16
AD7683
VDD = 5 V; V
Table 3.
A Grade B Grade
Parameter Conditions Min Typ Max Min Typ Max Unit
ACCURACY
No Missing Codes 15 16 Bits
Integral Linearity Error −6 ±3 +6 −3 ±1 +3 LSB
Transition Noise 0.5 0.5 LSB
Gain Error1, T
Gain Error Temperature Drift ±0.3 ±0.3 ppm/°C
Offset Error1, T
Offset Temperature Drift ±0.3 ±0.3 ppm/°C
Power Supply Sensitivity
AC ACCURACY
Signal-to-Noise fIN = 1 kHz 90 88 91 dB
Spurious-Free Dynamic Range fIN = 1 kHz −100 −108 dB
Total Harmonic Distortion fIN = 1 kHz −100 −106 dB
Signal-to-(Noise + Distortion) fIN = 1 kHz 90 88 91 dB
Effective Number of Bits fIN = 1 kHz 14.7 14.8 Bits
= VDD; TA = –40°C to +85°C, unless otherwise noted.
REF
MIN
MIN
to T
to T
MAX
MAX
±2 ±24 ±2 ±15 LSB
±0.7 ±1.6 ±0.4 ±1.6 mV
VDD = 5 V ±5%
±0.05 ±0.05 LSB
2
1
See the section. These specifications include full temperature range variation, but do not include the error contribution from the external reference. Terminology
2
All specifications in dB are referred to a full-scale input, FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
VDD = 2.7 V; V
= 2.5V; TA = –40°C to +85°C, unless otherwise noted.
REF
Table 4.
A Grade B Grade
Parameter Conditions Min Typ Max Min Typ Max Unit
ACCURACY
No Missing Codes 15 16 Bits
Integral Linearity Error −6 ±3 +6 −3 ±1 +3 LSB
Transition Noise 0.85 0.85 LSB
Gain Error1, T
MIN
to T
MAX
±2 ±30 ±2 ±15 LSB
Gain Error Temperature Drift ±0.3 ±0.3 ppm/°C
Offset Error1, T
MIN
to T
MAX
±0.7 ±3.5 ±0.7 ±3.5 mV
Offset Temperature Drift ±0.3 ±0.3 ppm/°C
Power Supply Sensitivity
VDD = 2.7 V ±5%
±0.05 ±0.05 LSB
AC ACCURACY
Signal-to-Noise fIN = 1 kHz 85 86 dB
2
Spurious-Free Dynamic Range fIN = 1 kHz −96 −100 dB
Total Harmonic Distortion fIN = 1 kHz −94 −98 dB
Signal-to-(Noise + Distortion) fIN = 1 kHz 85 86 dB
Effective Number of Bits fIN = 1 kHz 13.8 14 Bits
1
See the section. These specifications do include full temperature range variation, but do not include the error contribution from the external reference. Terminology
2
All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
Rev. 0 | Page 4 of 16
AD7683
TIMING SPECIFICATIONS
VDD = 2.7 V to 5.5 V; TA = −40°C to +85°C, unless otherwise noted.
Table 5.
Parameter Symbol Min Typ Max Unit
Throughput Rate t
CS Falling to DCLOCK Low
CS Falling to DCLOCK Rising
DCLOCK Falling to Data Remains Valid t
CS Rising Edge to D
High Impedance
OUT
DCLOCK Falling to Data Valid t
Acquisition Time t
D
Fall Time t
OUT
D
Rise Time t
OUT
t
CYC
CS
t
SUCS
DCLOCK
D
OUT
145
t
CSD
Hi-Z
NOTE:
A MINIMUM OF 22 CLOCK CYCLES ARE REQUIRED FOR 16-BIT CONVERSION. SHOWN ARE 24 CLOCK CYCLES.
GOES LOW ON THE DCLOCK FALLING EDGE FOLLOWING THE LSB READING.