Analog Devices AD7678 pa Datasheet

PRELIMINAR Y TECHNICAL D A T A

a

Preliminary Technical Data

FEATURES
18 Bits Resolution with No Missing Codes
No Pipeline Delay ( SAR architecture )
Differential Input Range: 5V
Throughput: 100 kSPS
INL: 2.5 LSB Max (9.5 ppm of Full-Scale)
Dynamic Range : 102 dB Typ
S/(N+D): 100 dB Typ @ 10 kHz
THD: –115 dB Typ @ 10 kHz
Parallel (18, 16 or 8 bits bus) and Serial 5 V/3 V Interface
On-board Reference Buffer
Single 5 V Supply Operation
Power Dissipation: 15 mW @ 100 kSPS

20 mW Typ with internal buffer
Power-Down Mode: 7
Package: 48-Lead Quad Flat Pack (LQFP)
48-Lead Frame Chip Scale Package (LFCSP)
Pin-to-Pin Compatible with the AD7675/AD7679/AD7674

APPLICATIONS
CT Scanners
High Dynamic Data Acquisition
Geophone and hydrophone sensor
Instrumentation
Spectrum Analysis
Medical Instruments

␮␮

␮W Max

␮␮

AGND
AVDD

REFBUFIN

IN+

RESET

18-Bit, 100 kSPS SAR ADC

FUNCTIONAL BLOCK DIAGRAM

REF

REFGND

AD7678

SWITCHED

CAP DAC

CLOCK

CONTROL LOGIC AND

CNVST

SERIAL

PARALLEL

INTERFACE

IN-

PD

PDBUF

CALIBRATION CIRCUITRY

AD7678

DGNDDVDD

PORT

18

OVDD
OGND

DATA[17:0]
BUSY

RD
CS
MODE0

MODE1

GENERAL DESCRIPTION

The AD7678 is a 18-bit, 100 kSPS, charge redistribution
SAR, fully differential analog-to-digital converter that
operates from a single 5 V power supply. The part con­tains a high-speed 18-bit sampling ADC, an internal
conversion clock, an internal reference buffer, error cor­rection circuits, and both serial and parallel system
interface ports.

The AD7678 is hardware factory calibrated and is compre­hensively tested to ensure such ac parameters as
signal-to-noise ratio (SNR) and total harmonic distortion
(THD), in addition to the more traditional dc parameters
of gain, offset, and linearity.

It is fabricated using Analog Devices’ high-performance,

0.6 micron CMOS process and is available in a 48-lead
LQFP or a 48-lead LFCSP with operation specified from
–40°C to +85°C.

REV. PrA

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

PRODUCT HIGHLIGHTS

1. High resolution and Fast Throughput
The AD7678 is a 100 kSPS, charge redistribution, 18­bit SAR ADC ( no latency ).

2. Excellent accuracy
The AD7678 has a maximum integral nonlinearity of 2.5
LSB with no missing 18-bit code.

3. Single-Supply Operation
The AD7678 operates from a single 5 V supply and can
typically dissipate only 15 mW. Its power dissipation
decreases with the throughput to, for instance, 150W at
1kSPS. It consumes 7 ␮W maximum when in
power-down.

5. Serial or Parallel Interface
Versatile parallel (18, 16 or 8 bits bus) or 2-wire serial
interface arrangement compatible with both 3 V or 5 V
logic.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © Analog Devices, Inc., 2002

PRELIMINAR Y TECHNICAL D A TA

(–40C to +85C, V

AD7678–SPECIFICATIONS

Parameter Conditions Min Typ Ma x Unit

RESOLUTION 18 Bits

ANALOG INPUT

Voltage Range V
Operating Input Voltage V
Analog Input CMRR f
Input Current TBD kSPS Throughput TBD µA
Input Impedance See Analog Input Section

THROUGHPUT SPEED

Complete Cycle 10 µs
Throughput Rate 0 100 kSPS

DC ACCURACY

Integral Linearity Error –2.5 +2.5 LSB
No Missing Codes 18 Bits
Transition Noise 0.7 LSB

Gain Error, T

MIN

to T
Gain Error Temperature Drift ±TBD ppm/°C
Zero Error, T

MIN

to T
Zero Error Temperature Drift ±TBD ppm/°C
Power Supply Sensitivity AVDD = 5 V ± 5% ±TBD LSB

AC ACCURACY

Signal-to-Noise f
Spurious Free Dynamic Range fIN = 10 kHz 115 dB
Total Harmonic Distortion f
Signal-to-(Noise+Distortion) f

–3 dB Input Bandwidth TBD MHz

SAMPLING DYNAMICS

Aperture Delay 2ns
Aperture Jitter TBD ps rms
Transient Response Full-Scale Step 8.5 s

REFERENCE

External Reference Voltage Range REF 2.5 4.096 AVDD V
REF Voltage with reference buffer REFBUFIN = 2.5V 4.05 4.096 4.15 V
Reference Buffer Input Voltage Range REFBUFIN 1.5 2.5 TBD V
REFBUFIN Input Current –1 +1 µA
REF Current Drain 100 kSPS Throughput TBD µA

DIGITAL INPUTS
Logic Levels

V

IL

V

IH

I

IL

I

IH

DIGITAL OUTPUTS

Data Format Parallel or Serial 18-Bits
Pipeline Delay Conversion Results Available Immediately

V

OL

V

OH

POWER SUPPLIES

Specified Performance

AVDD 4.75 5 5.25 V
DVDD 4.75 5 5.25 V
OVDD 2.7 DVDD+0.3

Operating Current 100 kSPS Throughput

AVDD TBD mA

5

DVDD

5

OVDD

MAX

MAX

2

2

f

I
I

otherwise noted.)

– V

IN+

IN-

to AGND –0.1 AVDD V

IN+, VIN-

= TBD kHz TBD dB

IN

= 10 kHz 98 100 dB

IN

= 10 kHz –115 dB

IN

= 10 kHz, 100 dB

IN

= 10 kHz,–60 dB Input 42 dB

IN

= 1.6 mA 0.4 V

SINK

= –500 µA OVDD – 0.6 V

SOURCE

= 4.096V, AVDD = DVDD= 5 V, OVDD = 2.7 V to 5.25 V, unless

REF

-V

REF

+V

REF

±TBD % of FSR

±TBD ±TBD LSB

–0.3 +0.8 V
+2.0 DVDD + 0.3 V
–1 +1 µA
–1 +1 µA

After Completed Conversion

4

TBD mA
TBD µA

V

1

3

V

REV. PrA

–2–

PRELIMINAR Y TECHNICAL D A T A

Preliminary Technical Data

AD7678

Parameter Conditions Min Typ Ma x Unit

Power Dissipation

5

REFBUF high @100 kSPS 15 TBD mW
REFBUF low @100 kSPS 21 mW
REFBUF high @1 k SPS 150 µW
In Power-Down Mode

TEMPERATURE RANGE

Specified Performance T

NOTES

1

LSB means Least Significant Bit. With the ±4.096 V input range, one LSB is 31.25 µV.

2

See Definition of Specifications section. These specifications do not include the error contribution from the external reference.

3

All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale unless otherwise specified.

4

The max should be the minimum of 5.25V and DVDD+0.3V.

5

Tested in parallel reading mode.

6

With all digital inputs forced to DVDD or DGND respectively.

7

Contact factory for extended temperature range.

Specifications subject to change without notice.

TIMING SPECIFICATIONS

REFER TO FIGURES 11 AND 12

Convert Pulsewidth t
Time Between Conversions t
CNVST LOW to BUSY HIGH Delay t
BUSY HIGH All Modes Except in Master Serial Read After t
Convert
Aperture Delay t
End of Conversion to BUSY LOW Delay t
Conversion Time t
Acquisition Time t
RESET Pulsewidth t

REFER TO FIGURES 13, 14, AND 15 (Parallel Interface Modes)

CNVST LOW to DATA Valid Delay t
DATA Valid to BUSY LOW Delay t
Bus Access Request to DATA Valid t
Bus Relinquish Time t

REFER TO FIGURES 16 AND 17 (Master Serial Interface Modes)

CS LOW to SYNC Valid Delay t
CS LOW to Internal SCLK Valid Delay t
CS LOW to SDOUT Delay t
CNVST LOW to SYNC Delay t

SYNC Asserted to SCLK First Edge Delay
Internal SCLK Period
Internal SCLK HIGH
Internal SCLK LOW
SDOUT Valid Setup Time
SDOUT Valid Hold Time
SCLK Last Edge to SYNC Delay

CS HIGH to SYNC HI-Z t
CS HIGH to Internal SCLK HI-Z t
CS HIGH to SDOUT HI-Z t

BUSY HIGH in Master Serial Read after Convert
CNVST LOW to SYNC Asserted Delay t
SYNC Deasserted to BUSY LOW Delay t

7

to T

MIN

MAX

(–40C to +85C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)

2

2

2

2

2

2

2

2

6

7µW

–40 +85 °C

Symbol Min Typ Max Unit

1

2

3

4

5

6

7

8

9

10

11

12

13

1

14

15

16

17

t

18

t

19

t

20

t

21

t

22

t

23

t

24

25

26

27

t

28

29

30

5ns
10 µs

30 ns

1.5 µs

2ns

10 ns

1.5 µs

8.5 µs
10 ns

1.5 µs

45 ns

40 ns

515ns

10 ns
10 ns
10 ns

525 ns
3ns
25 40 ns
12 ns
7ns
4ns
2ns
3

10 ns
10 ns
10 ns

See Table I µs

1.5 µs

25 ns

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–3–

PRELIMINAR Y TECHNICAL D A TA

AD7678

TIMING SPECIFICATIONS (continued)

Symbol Min Typ Max Unit

REFER TO FIGURES 18 AND 20 (Slave Serial Interface Modes)

External SCLK Setup Time t
External SCLK Active Edge to SDOUT Delay t
SDIN Setup Time t
SDIN Hold Time t
External SCLK Period t
External SCLK HIGH t
External SCLK LOW t

NOTES

1

In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.

2

In serial master read during convert mode. See Table I for serial master read after convert mode.

Specifications subject to change without notice.

31

32

33

34

35

36

37

Table I. Serial clock timings in Master Read after Convert

5ns
318ns
5ns
5ns
25 ns
10 ns
10 ns

DIVSCLK[1] 0011unit
DIVSCLK[0] 0101

SYNC to SCLK First Edge Delay Minimum t
Internal SCLK Period minimum t
Internal SCLK Period typical t
Internal SCLK HIGH Minimum t
Internal SCLK LOW Minimum t
SDOUT Valid Setup Time Minimum t
SDOUT Valid Hold Time Minimum t
SCLK Last Edge to SYNC Delay Minimum t
Busy High Width Maximum t

18

19

19

20

21

22

23

24

28

3 171717ns
25 50 100 200 ns
40 70 140 280 ns
12 22 50 100 ns
7 214999ns
4 181818ns
2 4 3089ns
3 60 140 300 ns

2.25 2.75 3.75 6 µs

–4–

REV. PrA

PRELIMINAR Y TECHNICAL D A TA

WARN­ING!

ESD SENSITIVE

DEVICE

AD7678

ABSOLUTE MAXIMUM RATINGS

Analog Inputs

2

, IN-2, REF, REFBUFIN, REFGND to AGND

IN+

1

. . . . . . . . . . . . . . . . . AVDD + 0.3 V to AGND – 0.3 V

Ground Voltage Differences

AGND, DGND, OGND . . . . . . . . . . . . . . . . . . .±0.3 V

Supply Voltages

AVDD, DVDD, OVDD . . . . . . . . . . . . . -0.3V to +7 V

AVDD to DVDD,

AVDD to OVDD . . . . . . . . . ±7 V

DVDD to OVDD . . . . . . . . . . . . . . . . . . -0.3V to +7 V

Digital Inputs . . . . . . . . . . . . –0.3 V to DVDD + 0.3V

Internal Power Dissipation
Internal Power Dissipation

3

. . . . . . . . . . . . . . . . 700 mW

4

. . . . . . . . . . . . . . . . . . . 2.5W

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . 150°C

Storage Temperature Range . . . . . . . . . –65°C to +150°C

Lead Temperature Range

(Soldering 10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 300°C

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may

cause permanent damage to the device. This is a stress rating only;
functional operation of the device at these or any other conditions above
those indicated in the operational section of this specification is not
implied. Exposure to absolute maximum rating conditions for ex­tended periods may affect device reliability.

2

See Analog Input section.

3

Specification is for device in free air: 48-Lead LQFP: θJA = 91°C/W, θ

30°C/W.

4

Specification is for device in free air: 48-Lead LFCSP: θ

= 26°C/W.

JA

=

JC

1.6mA

TO OUTPUT

PIN

C

L

60pF*

500A

IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND

*

SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD
CL OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.

I

OL

1.4V

I

OH

Figure 1. Load Circuit for Digital Interface Timing,
SDOUT, SYNC, SCLK Outputs, C

0.8V

t

DELAY

2V

0.8V

= 10 pF

L

2V

t

DELAY

2V

0.8V

Figure 2. Voltage Reference Levels for Timing

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD7678AST –40°C to +85°C Quad Flatpack (LQFP) ST-48
AD7678ASTRL –40°C to +85°C Quad Flatpack (LQFP) ST-48
AD7678ACP –40°C to +85°C Chip Scale (LFCSP) CP-48
AD7678ACPRL –40°C to +85°C Chip Scale (LFCSP) CP-48
EVAL-AD7678CB
EVAL-CONTROL BRD2

NOTES

1

This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD2 for evaluation/demonstration
purposes.

2

This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.

1

2

Evaluation Board
Controller Board

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7678 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

REV. PrA

–5–

AD7678

PRELIMINAR Y TECHNICAL DAT A

PIN CONFIGURATION

48-Lead LQFP

(ST-48)

PDBUF

AVDD

REFBUFINNCAGND

AGND

AVDD
MODE0
MODE1

D0/OB/2C

NC

NC
D1/A0
D2/A1

D3
D4/DIVSCLK[0]
D5/DIVSCLK[1]

NC = NO CONNECT

48

47 46

1

PIN 1

2

IDENTIFIER
3
4
5
6
7

8
9

10
11
12

13 14

15 16 17 18

IN+NCNCNCIN-

45 44 39 38 3743 42 41 40

AD7678

TOP VIEW

(Not to Scale)

19 20

21 22

REFGND

23 24

REF

36
35
34
33
32
31
30
29
28
27
26
25

AGND
CNVST
PD
RESET
CS
RD
DGND
BUSY
D17
D16
D15
D14

D6/EXT/INT

D8/INVSCLK

D7/INVSYNC

DVDD

OVDD

OGND

D9/RDC/SDIN

DGND

D10/SDOUT

D11/SCLK

D12/SYNC

D13/RDERROR

–6–

REV. PrA