Analog Devices AD7678 Datasheet
18-Bit, 2.5 LSB INL, 100 kSPS SAR ADC
FEATURES
18-bit resolution with no missing codes
No pipeline delay (SAR architecture)
(V
Differential input range: ±V
Throughput: 100 kSPS
INL: ±2.5 LSB max (±9.5 ppm of full scale)
Dynamic range: 103 dB typ (V
S/(N+D): 100 dB typ @ 2 kHz (V
Parallel (18-,16-, or 8-bit bus) and serial 5 V/3 V interface
®/QSPI™/MICROWIRE™/DSP compatible
SPI
On-board reference buffer
Single 5 V supply operation
Power dissipation: 18 mW @ 100 kSPS
180 µW @ 1 kSPS
48-lead LQFP or 48-lead LFCSP package
Pin-to-pin compatible upgrade of AD7674/AD7676/AD7679
APPLICATIONS
CT scanners
High dynamic data acquisition
Geophone and hydrophone sensors
-∆ replacement (low power, multichannel)
Σ
Instrumentation
Spectrum analysis
Medical instruments
GENERAL DESCRIPTION
The AD7678 is an 18-bit, 100 kSPS, charge redistribution SAR,
fully differential analog-to-digital converter that operates on a
single 5 V power supply. The part contains a high speed 18-bit
sampling ADC, an internal conversion clock, an internal
reference buffer, error correction circuits, and both serial and
parallel system interface ports.
The part is available in 48-lead LQFP or 48-lead LFCSP
packages with operation specified from –40°C to +85°C.
REF
REF
REF
REF
= 5 V)
= 5 V)
up to 5 V)
AD7678
FUNCTIONAL BLOCK DIAGRAM
PDBUF
AGND
AVDD
REFBUFIN
IN+
IN–
PD
RESET
CALIBRATION CIRCUITRY
Table 1. PulSAR Selection
Type/kSPS 100–250 500–570
PseudoDifferential
True Bipolar AD7663 AD7665 AD7671
True
Differential
18-Bit AD7678 AD7679 AD7674
Multichannel/
Simultaneous
PRODUCT HIGHLIGHTS
1. High Resolution, Fast Throughput.
The AD7678 is a 100 kSPS, charge redistribution, 18-bit
SAR ADC (no latency).
2. Excellent Accuracy.
The AD7678 has a maximum integral nonlinearity of
2.5 LSB with no missing 18-bit codes.
3. Serial or Parallel Interface.
Versatile parallel (18-, 16-, or 8-bit bus) or 2-wire serial
interface arrangement compatible with both 3 V and
5 V logic.
REF
REFGND
AD7678
SWITCHED
CAP DAC
PARALLEL
CLOCK
CONTROL LOGIC AND
CNVST
Figure 1. Functional Block Diagram
INTERFACE
SERIAL
PORT
DGNDDVDD
OVDD
OGND
18
D[17:0]
BUSY
RD
CS
MODE0
MODE1
03084–0–001
800–
1000
AD7651
AD7660/AD7661
AD7650/AD7652
AD7664/AD7666
AD7653
AD7667
AD7675 AD7676 AD7677
AD7654
AD7655
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved.
www.analog.com
AD7678
TABLE OF CONTENTS
Specifications..................................................................................... 3
Digital Interface.......................................................................... 20
Timing Specifications....................................................................... 5
Absolute Maximum Ratings............................................................ 7
Pin Configuration and Functional Descriptions.......................... 8
Definition of Specifications........................................................... 11
Typical Performance Characteristics ...........................................12
Circuit Information........................................................................ 15
Converter Operation.................................................................. 15
Typical Connection Diagram ................................................... 17
Power Dissipation versus Throughput.................................... 19
Conversion Control.................................................................... 19
REVISION HISTORY
Revision 0: Initial Version
Parallel Interface......................................................................... 20
Serial Interface............................................................................ 20
Master Serial Interface............................................................... 21
Slave Serial Interface.................................................................. 22
Microprocessor Interfacing ...................................................... 24
Application Hints ........................................................................... 25
Layout .......................................................................................... 25
Evaluating the AD7678’s Performance.................................... 25
Outline Dimensions....................................................................... 26
Ordering Guide .......................................................................... 26
Rev. 0 | Page 2 of 28
AD7678
SPECIFICATIONS
Table 2. –40°C to +85°C, V
Parameter Conditions Min Typ Max Unit
RESOLUTION 18 Bits
ANALOG INPUT
Voltage Range V
Operating Input Voltage V
Analog Input CMRR fIN = 100 kHz 65 dB
Input Current 100 kSPS Throughput 4 µA
Input Impedance1
THROUGHPUT SPEED
Complete Cycle 10 µs
Throughput Rate 0 100 kSPS
DC ACCURACY
Integral Linearity Error –2.5 +2.5 LSB2
Differential Linearity Error –1 +1.75 LSB
No Missing Codes 18 Bits
Transition Noise V
Zero Error, T
MIN
to T
MAX
Zero Error Temperature Drift ±0.5 ppm/°C
Gain Error, T
MIN
to T
MAX
Gain Error Temperature Drift ±1.6 ppm/°C
Power Supply Sensitivity AVDD = 5 V ± 5% ±4 LSB
AC ACCURACY
Signal-to-Noise
Dynamic Range V
Spurious-Free Dynamic Range
Total Harmonic Distortion
–3 dB Input Bandwidth 900 kHz
SAMPLING DYNAMICS
Aperture Delay 2 ns
Aperture Jitter 5 ps rms
Transient Response Full-Scale Step 8.5 µs
Overvoltage Recovery 8.5 µs
REFERENCE
External Reference Voltage Range REF 3 4.096 AVDD + 0.1 V
REF Voltage with Reference Buffer REFBUFIN = 2.5 V 4.05 4.096 4.15 V
Reference Buffer Input Voltage Range REFBUFIN 1.8 2.5 2.6 V
REFBUFIN Input Current –1 +1 µA
REF Current Drain 100 kSPS Throughput 42 µA
= 4.096 V, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.
REF
– V
–V
IN+
IN–
, V
to AGND –0.1 AVDD + 0.1 V
IN+
IN–
= 5 V 0.7 LSB
3
–40 ±40 LSB
3
–0.048 See Note 3 +0.048 % of FSR
REF
fIN = 2 kHz, V
V
= 4.096 V 98 100 dB
REF
fIN = 10 kHz, V
= 45 kHz, V
f
IN
= V
IN+
= 5 V 101 dB4
REF
= 4.096 V 99.5 dB
REF
= 4.096 V 98 dB
REF
= V
IN–
/2 = 2.5 V 103 dB
REF
+V
REF
V
REF
fIN = 2 kHz 120 dB
fIN = 10 kHz 117 dB
f
= 45 kHz 110 dB
IN
fIN = 2 kHz –118 dB
fIN = 10 kHz –115 dB
f
= 45 kHz –110 dB
IN
fIN = 2 kHz 100 dB Signal-to-(Noise + Distortion)
= 2 kHz, –60 dB Input 41 dB
f
IN
Rev. 0 | Page 3 of 28
AD7678
Parameter Conditions Min Typ Max Unit
DIGITAL INPUTS
Logic Levels
VIL –0.3 +0.8 V
VIH 2.0 DVDD + 0.3 V
IIL –1 +1 µA
IIH –1 +1 µA
DIGITAL OUTPUTS
Data Format5
Pipeline Delay6
VOL I
VOH I
POWER SUPPLIES
Specified Performance
AVDD 4.75 5 5.25 V
DVDD 4.75 5 5.25 V
OVDD 2.7 DVDD + 0.37 V
Operating Current 100 kSPS Throughput
AVDD PDBUF High 2.6 mA
DVDD8 1 mA
OVDD8 40 µA
PDBUF High @ 100 kSPS 18 26 mW
PDBUF High @ 1 kSPS 180 µW
PDBUF Low @ 100 kSPS 31 mW
TEMPERATURE RANGE9
Specified Performance T
= 1.6 mA 0.4 V
SINK
= –500 µA OVDD – 0.6 V
SOURCE
to T
MIN
–40 +85 °C
MAX
1
See section. Analog Inputs
2
LSB means Least Significant Bit. With the ±4.096 V input range, 1 LSB is 31.25 µV.
3
See section. The nominal gain error is not centered at zero and is +0.273% of FSR. This specification is the deviation from this nominal
Definition of Specifications
value. These specifications do not include the error contribution from the external reference, but do include the error contribution from the reference buffer if used.
4
All specifications in dB are referred to a full-scale input, FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
5
Data format parallel or serial 18-bit.
6
Conversion results are available immediately after completed conversion.
7
The maximum should be the minimum of 5.25 V and DVDD + 0.3 V.
8
Tested in Parallel Reading mode.
9
Contact factory for extended temperature range.
Rev. 0 | Page 4 of 28
AD7678
TIMING SPECIFICATIONS
Table 3. –40°C to +85°C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.
Parameter Symbol Min Typ Max Unit
Refer to Figure 27 and Figure 28
Convert Pulse Width t1 10 ns
Time between Conversions t2 10 µs
t
CNVST LOW to BUSY HIGH Delay
BUSY HIGH All Modes Except Master Serial Read after Convert t4 1.5 µs
Aperture Delay t5 2 ns
End of Conversion to BUSY LOW Delay t6 10 ns
Conversion Time t7 1.5 µs
Acquisition Time t8 8.5 µs
RESET Pulsewidth t9 10 ns
Refer to Figure 29, Figure 30, and Figure 31 (Parallel Interface Modes)
CNVST LOW to Data Valid Delay
Data Valid to BUSY LOW Delay t11 20 ns
Bus Access Request to Data Valid t12 45 ns
Bus Relinquish Time t13 5 15 ns
Refer to Figure 33 and Figure 34 (Master Serial Interface Modes)1
CS LOW to SYNC Valid Delay
CS LOW to Internal SCLK Valid Delay
CS LOW to SDOUT Delay
CNVST LOW to SYNC Delay
SYNC Asserted to SCLK First Edge Delay2 t
Internal SCLK Period2 t
Internal SCLK HIGH2 t
Internal SCLK LOW2 t
SDOUT Valid Setup Time2 t
SDOUT Valid Hold Time2 t
SCLK Last Edge to SYNC Delay2 t
CS HIGH to SYNC HI-Z
CS HIGH to Internal SCLK HI-Z
CS HIGH to SDOUT HI-Z
BUSY HIGH in Master Serial Read after Convert2 t
CNVST LOW to SYNC Asserted Delay
SYNC Deasserted to BUSY LOW Delay t30 25 ns
Refer to Figure 35 and Figure 36 (Slave Serial Interface Modes)
External SCLK Setup Time t31 5 ns
External SCLK Active Edge to SDOUT Delay t32 3 18 ns
SDIN Setup Time t33 5 ns
SDIN Hold Time t34 5 ns
External SCLK Period t35 25 ns
External SCLK HIGH t36 10 ns
External SCLK LOW t37 10 ns
1
In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.
2
In Serial Master Read during Convert mode. See for Serial Master Read after Convert mode. Table 4
35 ns
3
t
1.5 µs
10
t
10 ns
14
t
10 ns
15
t
10 ns
16
t
525 ns
17
3 ns
18
25 40 ns
19
12 ns
20
7 ns
21
4 ns
22
2 ns
23
3 ns
24
t
10 ns
25
t
10 ns
26
t
10 ns
27
See Table 4
28
1.5 µs
t
29
Rev. 0 | Page 5 of 28
AD7678
Table 4. Serial Clock Timings in Master Read after Convert
DIVSCLK[1] 0 0 1 1
DIVSCLK[0] Symbol 0 1 0 1
SYNC to SCLK First Edge Delay Minimum t18 3 17 17 17 ns
Internal SCLK Period Minimum t19 25 60 120 240 ns
Internal SCLK Period Maximum t19 40 80 160 320 ns
Internal SCLK HIGH Minimum t20 12 22 50 100 ns
Internal SCLK LOW Minimum t21 7 21 49 99 ns
SDOUT Valid Setup Time Minimum t22 4 18 18 18 ns
SDOUT Valid Hold Time Minimum t23 2 4 30 89 ns
SCLK Last Edge to SYNC Delay Minimum t24 3 60 140 300 ns
Busy High Width Maximum t28 2.25 3 4.5 7.5 µs
Unit
Rev. 0 | Page 6 of 28
AD7678
ABSOLUTE MAXIMUM RATINGS
Table 5. AD7678 Absolute Maximum Ratings1
Parameter Rating
Analog Inputs
IN+2, IN–2, REF, REFBUFIN, REFGND
to AGND
AVDD + 0.3 V to
AGND – 0.3 V
Ground Voltage Differences
AGND, DGND, OGND ±0.3 V
Supply Voltages
AVDD, DVDD, OVDD –0.3 V to +7 V
AVDD to DVDD, AVDD to OVDD ±7 V
DVDD to OVDD –0.3 V to +7 V
Digital Inputs –0.3 V to DVDD + 0.3 V
Internal Power Dissipation3 700 mW
Internal Power Dissipation4 2.5 W
Junction Temperature 150°C
Storage Temperature Range –65°C to +150°C
Lead Temperature Range
(Soldering 10 sec)
300°C
1
Stresses above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional
operation of the device at these or any other conditions above those
indicated in the operational section of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
2
See An section. alog Inputs
3
Specification is for device in free air: 48-Lead LQFP: θJA = 91°C/W,
θJC = 30°C/W.
4
Specification is for device in free air: 48-Lead LFCSP: θJA = 26°C/W.
I
1.6mA
TO OUTPUT
PIN
C
L
1
60pF
500µA
1
IN SERIAL INTERFACE MODES,THE SYNC, SCLK, AND
SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD
CL OF 10pF; OTHERWISE,THE LOAD IS 60pF MAXIMUM.
Figure 2. Load Circuit for Digital Interface Timing,
SDOUT, SYNC, SCLK Outputs, C
0.8V
t
DELAY
2V
0.8V
Figure 3. Voltage Reference Levels for Timing
OL
1.4V
I
OH
= 10 pF
L
03084–0–002
2V
t
DELAY
2V
0.8V
03084–0–003
Rev. 0 | Page 7 of 28
AD7678
PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS
PDBUF
AVDD
REFBUFINNCAGND
IN+NCNCNCIN–
AD7678
TOP VIEW
(Not to Scale)
OVDD
OGND
D8/INVSCLK
D9/RDC/SDIN
DVDD
AGND
AVD D
MODE0
MODE1
D0/OB/2C
NC
NC
D1/A0
D2/A1
D3
D4/DIVSCLK[0]
D5/DIVSCLK[1]
NC = NO CONNECT
48 47 46 45 4 4 39 38 3 743 42 41 40
1
PIN 1
2
IDENTIFIER
3
4
5
6
7
8
9
10
11
12
13 14 15 16 17 18 19 20 21 22 23 24
D6/EXT/INT
D7/INVSYNC
Figure 4. 48-Lead LQFP and 48-Lead LFCSP (ST-48 and CP-48)
Table 6. Pin Function Descriptions
Pin No. Mnemonic Type1 Description
1, 44 AGND P Analog Power Ground Pin.
2, 47 AVDD P Input Analog Power Pins. Nominally 5 V.
3 MODE0 DI Data Output Interface Mode Selection.
4 MODE1 DI Data Output Interface Mode Selection:
Interface MODE # MODE1 MODE0 Description
0 0 0 18-Bit Interface
1 0 1 16-Bit Interface
2 1 0 Byte Interface
3 1 1 Serial Interface
5
D0/OB/2C
DI/O
When MODE = 0 (18-bit interface mode), this pin is Bit 0 of the parallel port data output bus and the
data coding is straight binary. In all other modes, this pin allows choice of straight binary/binary twos
complement. When OB/2C
is HIGH, the digital output is straight binary; when LOW, the MSB is
inverted, resulting in a twos complement output from its internal shift register.
6, 7,
NC No Connect.
40–42,
45
8 D1/A0 DI/O
When MODE = 0 (18-bit interface mode), this pin is Bit 1 of the parallel port data output bus. In all
other modes, this input pin controls the form in which data is output, as shown in Table 7.
9 D2/A1 DI/O
When MODE = 0 or 1 (18-bit or 16-bit interface mode), this pin is Bit 2 of the parallel port data output
bus. In all other modes, this input pin controls the form in which data is output, as shown in Table 7.
10 D3 DO
In all modes except MODE = 3, this output is used as Bit 3 of the parallel port data output bus. This pin
is always an output, regardless of the interface mode.
11, 12 D[4:5]or
DIVSCLK[0:1]
DI/O In all modes except MODE = 3, these pins are Bit 4 and Bit 5 of the parallel port data output bus.
When MODE = 3 (serial mode), EXT/INT
convert), these inputs, part of the serial port, are used to slow down, if desired, the internal serial clock
that clocks the data output. In other serial modes, these pins are not used.
REFGND
DGND
D11/SCLK
D12/SYNC
D10/SDOUT
is LOW, and RDC/SDIN is LOW (serial master read after
REF
D13/RDERROR
36
AGND
35
CNVST
34
PD
33
RESET
32
CS
31
RD
30
DGND
29
BUSY
28
D17
27
D16
26
D15
25
D14
03084–0–004
Rev. 0 | Page 8 of 28
AD7678
Pin No. Mnemonic Type1 Description
13 D6
or EXT/INT
14 D7
or INVSYNC
15 D8
or INVSCLK
16 D9
or RDC/SDIN
17 OGND P Input/Output Interface Digital Power Ground.
18 OVDD P
19 DVDD P Digital Power. Nominally at 5 V.
20 DGND P Digital Power Ground.
21 D10
or SDOUT
22 D11
or SCLK
23 D12
or SYNC
24 D13
or RDERROR
25–28 D[14:17] DO
29 BUSY DO
30 DGND P Must Be Tied to Digital Ground.
31
32
33 RESET DI
RD
CS
DI/O In all modes except MODE = 3, this output is used as Bit 6 of the parallel port data output bus.
DI/O In all modes except MODE = 3, this output is used as Bit 7 of the parallel port data output bus.
DI/O In all modes except MODE = 3, this output is used as Bit 8 of the parallel port data output bus.
DI/O In all modes except MODE = 3, this output is used as Bit 9 of the parallel port data output bus.
DO In all modes except MODE = 3, this output is used as Bit 10 of the parallel port data output bus.
DI/O In all modes except MODE = 3, this output is used as Bit 11 of the parallel port data output bus.
DO In all modes except MODE = 3, this output is used as Bit 12 of the parallel port data output bus.
DO In all modes except MODE = 3, this output is used as Bit 13 of the parallel port data output bus.
DI
DI
When MODE = 3 (serial mode), this input, part of the serial port, is used as a digital select input for
choosing the internal data clock or an external data clock. With EXT/INT
selected on the SCLK output. With EXT/INT set to a logic HIGH, output data is synchronized to an
external clock signal connected to the SCLK input.
When MODE = 3 (serial mode), this input, part of the serial port, is used to select the active state of the
SYNC signal. When LOW, SYNC is active HIGH. When HIGH, SYNC is active LOW.
When MODE = 3 (serial mode), this input, part of the serial port, is used to invert the SCLK signal. It is
active in both master and slave modes.
When MODE = 3 (serial mode), this input, part of the serial port, is used as either an external data
input or a read mode selection input depending on the state of EXT/INT
RDC/SDIN could be used as a data input to daisy-chain the conversion results from two or more ADCs
onto a single SDOUT line. The digital data level on SDIN is output on SDOUT with a delay of 18 SCLK
periods after the initiation of the read sequence. When EXT/INT
read mode. When RDC/SDIN is HIGH, the data is output on SDOUT during conversion. When
RDC/SDIN is LOW, the data can be output on SDOUT only when the conversion is complete.
Output Interface Digital Power. Nominally at the same supply as the host interface (5 V or 3 V). Should
not exceed DVDD by more than 0.3 V.
When MODE = 3 (serial mode), this output, part of the serial port, is used as a serial data output
synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7678 provides the
conversion result, MSB first, from its internal shift register. The data format is determined by the logic
level of OB/2C
mode when EXT/INT
valid on the next falling edge; if INVSCLK is HIGH, SDOUT is updated on the SCLK falling edge and is
valid on the next rising edge.
When MODE = 3 (serial mode), this pin, part of the serial port, is used as a serial data clock input or
output, depending upon the logic state of the EXT/INT
updated depends upon the logic state of the INVSCLK pin.
When MODE = 3 (serial mode), this output, part of the serial port, is used as a digital output frame
synchronization for use with the internal data clock (EXT/INT = Logic LOW). When a read sequence is
initiated and INVSYNC is LOW, SYNC is driven HIGH and remains HIGH while the SDOUT output is
valid. When a read sequence is initiated and INVSYNC is HIGH, SYNC is driven LOW and remains LOW
while SDOUT output is valid.
In MODE = 3 (serial mode) and when EXT/INT is HIGH, this output, part of the serial port, is used as an
incomplete read error flag. In slave mode, when a data read is started and not complete when the
following conversion is complete, the current data is lost and RDERROR is pulsed high.
Bit 14 to Bit 17 of the Parallel Port Data Output Bus. These pins are always outputs regardless of the
interface mode.
Busy Output. Transitions HIGH when a conversion is started. Remains HIGH until the conversion is
complete and the data is latched into the on-chip shift register. The falling edge of BUSY could be
used as a data ready clock signal.
Read Data. When CS and RD are both LOW, the interface parallel or serial output bus is enabled.
Chip Select. When CS and RD are both LOW, the interface parallel or serial output bus is enabled. CS is
also used to gate the external clock.
Reset Input. When set to a logic HIGH, reset the AD7678. Current conversion, if any, is aborted. If not
used, this pin could be tied to DGND.
. In serial mode when EXT/INT is LOW, SDOUT is valid on both edges of SCLK. In serial
is HIGH and INVSCLK is LOW, SDOUT is updated on the SCLK rising edge and is
pin. The active edge where the data SDOUT is
is LOW, RDC/SDIN is used to select the
tied LOW, the internal clock is
. When EXT/INT is HIGH,
Rev. 0 | Page 9 of 28
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