Analog Devices AD7677ASTRL, AD7677AST Datasheet

16-Bit, 1 LSB INL, 1 MSPS

a

FEATURES
Throughput: 1 MSPS
INL: ⴞ1 LSB Max (ⴞ0.0015% of Full-Scale)
16 Bits Resolution with No Missing Codes
S/(N+D): 94 dB Typ @ 45 kHz
THD: –110 dB Typ @ 45 kHz
Differential Input Range: ⴞ2.5 V
Both AC and DC Specifications
No Pipeline Delay
Parallel (8/16 Bits) and Serial 5 V/3 V Interface
Single 5 V Supply Operation
115 mW Typical Power Dissipation, 15 ␮W @ 100 SPS
Power-Down Mode: 7 ␮W Max
Package: 48-Lead Quad Flat Pack (LQFP)
Pin-to-Pin Compatible Upgrade of the AD7664/AD7675/

AD7676

APPLICATIONS
CT Scanners
Data Acquisition
Instrumentation
Spectrum Analysis
Medical Instruments
Battery-Powered Systems
Process Control

FUNCTIONAL BLOCK DIAGRAM

AVDD AGND REF REFGND

AD7677

IN+

IN–

PD

RESET

CONTROL LOGIC AND

CALIBRATION CIRCUITRY

SWITCHED

CAP DAC

IMPULSEWARP

Differential ADC

AD7677

DVD D

DGND

SERIAL

PORT

16

CLOCK

CNVST

PARALLEL

INTERFACE

*

OVD D

OGND

SER/PAR

BUSY

DATA[15:0]

CS

RD

OB/2C

BYTESWAP

GENERAL DESCRIPTION

The AD7677 is a 16-bit, 1 MSPS, charge redistribution SAR,
fully differential, analog-to-digital converter that operates from a
single 5 V power supply. The part contains a high-speed 16-bit
sampling ADC, an internal conversion clock, error correction
circuits, and both serial and parallel system interface ports.

The AD7677 is hardware factory calibrated and comprehen­sively tested to ensure such ac parameters as signal-to-noise
ratio (SNR) and total harmonic distortion (THD), in addition
to the more traditional dc parameters of gain, offset, and linearity.

It features a very high sampling rate mode (Warp) and, for
asynchronous conversion rate applications, a fast mode (Normal)
and, for low power applications, a reduced power mode (Impulse)
where the power is scaled with the throughput.

It is available in a 48-lead LQFP with operation specified from
–40°C to +85°C.

*Patent pending

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

PRODUCT HIGHLIGHTS

1. Excellent INL
The AD7677 has a maximum integral nonlinearity of 1 LSB
with a no missing 16-bit code.

2. Superior AC Performances
The AD7677 has a minimum dynamic of 92 dB, 94 dB typical.

3. Fast Throughput
The AD7677 is a 1 MSPS, charge redistribution, 16-bit SAR
ADC with internal error correction circuitry.

4. Single-Supply Operation
The AD7677 operates from a single 5 V supply and typically
dissipates only 115 mW. Its power dissipation decreases
with the throughput. It consumes 7 µW maximum when in
power-down.

5. Serial or Parallel Interface
Versatile parallel (8 or 16 bits) or 2-wire serial interface
arrangement compatible with both 3 V or 5 V logic.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]www.analog.com
Fax: [phone] © Analog Devices, Inc., 2001

AD7677–SPECIFICATIONS

(–40ⴗC to +85ⴗC, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise stated.)

Parameter Conditions Min Typ Max Unit

RESOLUTION 16 Bits

ANALOG INPUT

Voltage Range V
Operating Input Voltage V
Analog Input CMRR f

– V

IN+

IN–

IN+, VIN–

IN

to AGND –0.1 +3 V

= 10 kHz 85 dB

–V

REF

+V

REF

V

Input Current 1 MSPS Throughput 11 µA
Input Impedance See Analog Input Section

THROUGHPUT SPEED

Complete Cycle In Warp Mode 1 µs
Throughput Rate In Warp Mode 0.001 1 MSPS
Time Between Conversions In Warp Mode 1 ms
Complete Cycle In Normal Mode 1.25 µs
Throughput Rate In Normal Mode 0 800 kSPS
Complete Cycle In Impulse Mode 1.5 µs
Throughput Rate In Impulse Mode 0 666 kSPS

DC ACCURACY

Integral Linearity Error –1 +1 LSB
Differential Linearity Error –1 +1 LSB

1, 2

2

No Missing Codes 16 Bits
Transition Noise 0.35 LSB
+Full-Scale Error
–Full Scale Error
Zero Error
+Full-Scale Error
–Full Scale Error
Zero Error

3

3

3

3

3

3

In Warp Mode –25 +25 LSB
In Warp Mode –20 +20 LSB
In Warp Mode –15 +15 LSB
In Impulse or Normal Mode –40 +40 LSB
In Impulse or Normal Mode –20 +20 LSB
In Impulse or Normal Mode –23 +23 LSB

Power Supply Sensitivity AVDD = 5 V ± 5% ±1.4 LSB

AC ACCURACY

Signal-to-Noise f

Spurious Free Dynamic Range f

Total Harmonic Distortion f

Signal-to-(Noise+Distortion) f

= 20 kHz 92 94 dB

IN

fIN = 45 kHz 94 dB

= 20 kHz 104.5 110 dB

IN

fIN = 45 kHz 110 dB

= 20 kHz –110 –103.5 dB

IN

fIN = 45 kHz –110 dB

= 20 kHz 92 94 dB

IN

2, 4

2

2

2

fIN = 45 kHz 94
f

= 45 kHz, –60 dB Input 34 dB

IN

–3 dB Input Bandwidth 15.8 MHz

SAMPLING DYNAMICS

Aperture Delay 2ns
Aperture Jitter 5 ps rms
Transient Response Full-Scale Step 250 ns

REFERENCE

External Reference Voltage Range 2.3 2.5 AVDD – 1.85 V
External Reference Current Drain 1 MSPS Throughput 37 µA

DIGITAL INPUTS

Logic Levels

V

IL

V

IH

I

IL

I

IH

–0.3 +0.8 V

2.0 DVDD + 0.3 V
–1 +1 µA
–1 +1 µA

DIGITAL OUTPUTS

Data Format Parallel or Serial 16-Bit Conversion
Pipeline Delay Results Available Immediately after

Completed Conversion

V

OL

V

OH

I

= 1.6 mA 0.4 V

SINK

I

= –100 µA OVDD – 0.6 V

SOURCE

–2–

REV. 0

AD7677

Parameter Conditions Min Typ Max Unit

POWER SUPPLIES

Specified Performance

AVDD 4.75 5 5.25 V
DVDD 4.75 5 5.25 V
OVDD 2.7 5.25 V

Operating Current

AVDD 16.7 mA

5

DVDD

5

OVDD

Power Dissipation

In Power-Down Mode

TEMPERATURE RANGE

Specified Performance T

NOTES

1

LSB means Least Significant Bit. With the ± 2.5 V input range, one LSB is 76.3 µV.

2

In Warp Mode.

3

Tested with V

4

All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full scale unless otherwise specified.

5

Tested in parallel reading mode.

6

In Impulse Mode.

7

With all digital inputs forced to OVDD or OGND respectively.

8

Contact factory for extended temperature range.

Specifications subject to change without notice.

REF

2

1 MSPS Throughput

6.4 mA

5

666 kSPS Throughput
100 SPS Throughput

7

8

= 2.5 V. See Definition of Specifications section. These specifications do not include the error contribution from the external reference.

1 MSPS Throughput

to T

MIN

MAX

6

6

2

–40 +85 °C

69 µA
87 98 mW
15 µW
115 130 mW

7 µW

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–3–

AD7677

TIMING SPECIFICATIONS

(–40ⴗC to +85ⴗC, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise stated.)

Symbol Min Typ Max Unit

Refer to Figures 11 and 12

Convert Pulsewidth t
Time Between Conversions t

1

2

5ns
1/1.25/1.5 Note 1 µs

(Warp Mode/Normal Mode/Impulse Mode)
CNVST LOW to BUSY HIGH Delay t
BUSY HIGH All Modes Except in t

3

4

Master Serial Read after Convert Mode
(Warp Mode/Normal Mode/Impulse Mode)
Aperture Delay t
End of Conversion to BUSY LOW Delay t
Conversion Time t

5

6

7

10 ns

2ns

(Warp Mode/Normal Mode/Impulse Mode)
Acquisition Time t
RESET Pulsewidth t

8

9

250 ns
10 ns

Refer to Figures 13, 14, and 15 (Parallel Interface Modes)

CNVST LOW to DATA Valid Delay t

10

(Warp Mode/Normal Mode/Impulse Mode)
DATA Valid to BUSY LOW Delay t
Bus Access Request to DATA Valid t
Bus Relinquish Time t

Refer to Figures 17 and 18 (Master Serial Interface Modes)

2

CS LOW to SYNC Valid Delay t
CS LOW to Internal SCLK Valid Delay t
CS LOW to SDOUT Delay t
CNVST LOW to SYNC Delay (Read During Convert) t

(Warp Mode/Normal Mode/Impulse Mode)
SYNC Asserted to SCLK First Edge Delay
Internal SCLK Period
Internal SCLK HIGH
Internal SCLK LOW
SDOUT Valid Setup Time
SDOUT Valid Hold Time
SCLK Last Edge to SYNC Delay

3

3

3

3

3

3

3

CS HIGH to SYNC HI-Z t
CS HIGH to Internal SCLK HI-Z t
CS HIGH to SDOUT HI-Z t

BUSY HIGH in Master Serial Read After Convert

3

CNVST LOW to SYNC Asserted Delay t

11

12

13

14

15

16

17

t

18

t

19

t

20

t

21

t

22

t

23

t

24

25

26

27

t

28

29

45 ns

515ns

25/275/525 ns

3ns
25 40 ns
12 ns
7ns
4ns
2ns
3

See Table I

0.75/1/1.25 µs

(Warp Mode/Normal Mode/Impulse Mode)
SYNC Deasserted to BUSY LOW Delay t

30

25 ns

Refer to Figures 19 and 20 (Slave Serial Interface Modes)

External SCLK Setup Time t
External SCLK Active Edge to SDOUT Delay t
SDIN Setup Time t
SDIN Hold Time t
External SCLK Period t
External SCLK HIGH t
External SCLK LOW t

NOTES

1

In warp mode only, the maximum time between conversions is 1 ms, otherwise, there is no required maximum time.

2

In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C

3

In serial master read during convert mode. See Table I for serial master read after convert mode.

Specifications subject to change without notice.

31

32

33

34

35

36

37

5ns
318ns
5ns
5ns
25 ns
10 ns
10 ns

of 10 pF; otherwise, the load is 60 pF maximum.

L

30 ns

0.75/1/1.25 µs

0.75/1/1.25 µs

0.75/1/1.25 µs

40 ns

10 ns
10 ns
10 ns

10 ns
10 ns
10 ns

–4–

REV. 0

WARNING!

ESD SENSITIVE DEVICE

Table I. Serial Clock Timings in Master Read after Convert

DIVSCLK[1] 0 0 1 1
DIVSCLK[0] 0 1 0 1 Unit

SYNC to SCLK First Edge Delay Minimum t
Internal SCLK Period Minimum t
Internal SCLK Period Maximum t
Internal SCLK HIGH Minimum t
Internal SCLK LOW Minimum t
SDOUT Valid Setup Time Minimum t
SDOUT Valid Hold Time Minimum t
SCLK Last Edge to SYNC Delay Minimum t
Busy High Width Maximum (Warp) t
Busy High Width Maximum (Normal) t
Busy High Width Maximum (Impulse) t

18

3171717ns
25 50 100 200 ns

19

40 70 140 280 ns

19

12 22 50 100 ns

20

7214999ns

21

4181818ns

22

2 4 30 89 ns

23

3 60 140 300 ns

24

1.5 2 3 5.25 µs

24

1.75 2.25 3.25 5.55 µs

24

2 2.5 3.5 5.75 µs

24

AD7677

ABSOLUTE MAXIMUM RATINGS

Analog Inputs

2

IN+

, IN–2, REF, REFGND . . . . . . . . . . . . . . . . . . . . . . . .

1

. . . . . . . . . . . . . . . . . . . . AVDD + 0.3 V to AGND – 0.3 V

Ground Voltage Differences

AGND, DGND, OGND . . . . . . . . . . . . . . . . . . . . . ±0.3 V

Supply Voltages

AVDD, DVDD, OVDD . . . . . . . . . . . . . . . . . . . . . . . . . 7 V

AVDD to DVDD,

AVDD to OVDD . . . . . . . . . . . . . . ±7 V

DVDD to OVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±7 V

Digital Inputs . . . . . . . . . . . . . . . . . –0.3 V to DVDD + 0.3 V

Internal Power Dissipation

3

. . . . . . . . . . . . . . . . . . . . 700 mW

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature Range

(Soldering 10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

2

See Analog Input section.

3

Specification is for device in free air: 48-Lead LQFP: ␪JA = 91°C/W, ␪JC = 30°C/W.

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD7677AST –40°C to +85°C Quad Flatpack (LQFP) ST-48
AD7677ASTRL –40°C to +85°C Quad Flatpack (LQFP) ST-48
EVAL-AD7677CB
EVAL-CONTROL BRD2

NOTES

1

This board can be used as a stand-alone evaluation board or in conjunction with the EVAL-CONTROL BRD2 for evaluation/
demonstration purposes.

2

This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.

1

2

I

1.6mA

TO OUTPUT

PIN

C

L
1

60pF

500␮A

NOTE

1

IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND
SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD

OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.

C

L

OL

1.4V

I

OH

Figure 1. Load Circuit for Digital Interface Timing,
SDOUT, SYNC, SCLK Outputs, C

0.8V

t

DELAY

2V

0.8V

L

2V

=10pF

t

DELAY

2V

0.8V

Figure 2. Voltage Reference Levels for Timings

Evaluation Board
Controller Board

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7677 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

REV. 0

–5–

AD7677

PIN FUNCTION DESCRIPTIONS

Pin
No. Mnemonic Type Description

1 AGND P Analog Power Ground Pin
2 AVDD P Analog Power Pin. Nominally 5 V
3, NC No Connect
40–42,
44–48
4 BYTESWAP DI Parallel Mode Selection (8/16 bit). When LOW, the LSB is output on D[7:0] and the

MSB is output on D[15:8]. When HIGH, the LSB is output on D[15:8] and the MSB is
output on D[7:0].

5OB/2C DI Straight Binary/Binary Two’s Complement. When OB/2C is HIGH, the digital output is

straight binary; when LOW, the MSB is inverted resulting in a two’s complement output from
its internal shift register.

6 WARP DI Mode Selection. When HIGH and IMPULSE LOW, this input selects the fastest mode, the

maximum throughput is achievable, and a minimum conversion rate must be applied in order to
guarantee full specified accuracy. When LOW, full accuracy is maintained independent of the
minimum conversion rate.

7 IMPULSE DI Mode Selection. When HIGH and WARP LOW, this input selects a reduced power mode.

In this mode, the power dissipation is approximately proportional to the sampling rate.

8 SER/PAR DI Serial/Parallel Selection Input. When LOW, the parallel port is selected; when HIGH, the

serial interface mode is selected and some bits of the DATA bus are used as a serial port.

9, 10 DATA[0:1] DO Bit 0 and Bit 1 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, these outputs

are in high impedance.

11, 12 DATA[2:3] or DI/O When SER/PAR is LOW, these outputs are used as Bit 2 and Bit 3 of the Parallel Port Data

Output Bus.

DIVSCLK[0:1] When SER/PAR is HIGH, EXT/INT is LOW and RDC/SDIN is LOW, which is the serial

master read after convert mode. These inputs, part of the serial port, are used to slow down if
desired the internal serial clock which clocks the data output. In the other serial modes, these
inputs are not used.

13 DATA[4] DI/O When SER/PAR is LOW, this output is used as the Bit 4 of the Parallel Port Data Output Bus.

or EXT/INT When SER/PAR is HIGH, this input, part of the serial port, is used as a digital select input for

choosing the internal or an external data clock. With EXT/INT tied LOW, the internal clock
is selected on SCLK output. With EXT/INT set to a logic HIGH, output data is synchro­nized to an external clock signal connected to the SCLK input.

14 DATA[5] DI/O When SER/PAR is LOW, this output is used as the Bit 5 of the Parallel Port Data Output Bus.

or INVSYNC When SER/PAR is HIGH, this input, part of the serial port, is used to select the active state

of the SYNC signal. When LOW, SYNC is active HIGH. When HIGH, SYNC is active LOW.

15 DATA[6] DI/O When SER/PAR is LOW, this output is used as the Bit 6 of the Parallel Port Data Output Bus.

or INVSCLK When SER/PAR is HIGH, this input, part of the serial port, is used to invert the SCLK sig-

nal. It is active in both master and slave mode.

16 DATA[7] DI/O When SER/PAR is LOW, this output is used as the Bit 7 of the Parallel Port Data Output Bus.

or RDC/SDIN When SER/PAR is HIGH, this input, part of the serial port, is used as either an external data

input or a read mode selection input depending on the state of EXT/INT. When EXT/INT is
HIGH, RDC/SDIN could be used as a data input to daisy chain the conversion results from
two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on
DATA with a delay of 16 SCLK periods after the initiation of the read sequence. When EXT/
INT is LOW, RDC/SDIN is used to select the read mode. When RDC/SDIN is HIGH, the
data is output on SDOUT during conversion. When RDC/SDIN is LOW, the data is output

on SDOUT only when the conversion is complete.
17 OGND P Input/Output Interface Digital Power Ground
18 OVDD P Input/Output Interface Digital Power. Nominally at the same supply than the supply of the

host interface (5 V or 3 V).

–6–

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