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AD7675CB
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Analog Devices AD7663CB, AD7662CB, AD7660CB, AD7650CB, AD7677CB Datasheet

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PRELIMINAR Y TECHNICAL DATA
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Preliminary Technical Data
FEATURES Versatile Analog Signal Conditioning Circuitry On-Board Reference, Crystal Oscillator and Buffers 16-Bit Parallel Buffered Outputs Ideal For DSP and Data Acquisition Card Interfaces Analog and Digital Prototyping Area EVAL-CONTROL BOARD Compatibility PC Software for Control and Data Analysis
GENERAL DESCRIPTION
The EVAL-AD766XCB/AD767XCB is an evaluation board for the AD766X/AD767X 16-bit A/D converter family. The AD766X/AD767X family ( see ordering guide for product list ) is a high speed, successive approximation based architecture with very high performance, low power family of 16-Bit ADCs which operate from a single +5V supply with a 100kSPS to 1MSPS throughput rate range, and a flexible parallel or serial interface. The AD766X/AD767X evaluation board is designed to demonstrate the ADC's performance and to provide an easy to understand interface for a variety of system applications. A full description of the AD766X/AD767X is available in the Analog Devices AD766X/AD767X data sheets and should be consulted when utilizing this evaluation board.
Evaluation Board AD766X/AD767X
EV AL-AD766XCB/AD767XCB
The EVAL-AD766XCB/AD767XCB is ideal for use with either the Analog Devices EVAL-CONTROL BOARD, or as a stand-alone evaluation board. The design offers the flexibility of applying external control signals and is capable of generating 16-bit conversion results on a parallel buffered outputs.
On-board components include an AD780, a +2.5V ultrahigh precision bandgap reference, a signal conditioning circuit with two op-amps and digital logic. The board interfaces with a 96-way connector for the EVAL-CONTROL BOARD, a 20-pin IDC connector for serial output interface, and a 40­pin IDC connector for parallel output data. SMB connectors are provided for the low noise analog signal source, an exter­nal master clock and an external start/convert input.

ORDERING GUIDE

Evaluation board Model Product
EVAL-AD7650CB AD7650AST EVAL-AD7660CB AD7660AST EVAL-AD7662CB AD7662YST EVAL-AD7663CB AD7663AST EVAL-AD7664CB AD7664AST EVAL-AD7665CB AD7665AST EVAL-AD7668CB AD7668YST EVAL-AD7671CB AD7671AST EVAL-AD7675CB AD7675AST EVAL-AD7676CB AD7676AST EVAL-AD7677CB AD7677AST EVAL-CONTROL BRD2 Controller Board

FUNCTIONAL BLOCK DIAGRAM

REF 2.5V AD780
REF
AD766x or
AUX_IN
SIGNAL CONDITIONING
IN
REV. PrK
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
AD767x
IN
Configuration switches
+/-5 V
+/-12 V
+5 V
V
L
96 PIN CONN
MCLK
CNVST
Clock
40 PIN CONN
20 PIN CONN
CNVST
BUSY
DIGITAL LOGIC
DATA
MCLK
PRELIMINARY TECHNICAL DATA
EVAL-AD766XCB/AD767XCB

OPERATING THE EVAL-AD766XCB/AD767XCB

The EVAL-AD766XCB/AD767XCB is a four-layer board carefully laid out and tested to demonstrate the specific high accuracy performance of the AD766X/AD767X. Figure 1 shows the schematics of the evaluation board. The layouts of the board are given in : Top side silk-screen - Figure 2 Top side layer - Figure 3 Ground layer - Figure 4 Shield layer - Figure 5 Bottom side layer - Figure 6 Bottom side silk-screen - Figure 7. The EVAL-AD766XCB/AD767XCB is a flexible design that enables the user to choose among many different board con­figurations. A description of each selectable jumper/switch is listed in Table II and the available test points are listed in Table III. Note that the button of a switch in position A ( U3 side ) defines a low level.
The EVAL-AD766XCB/AD767XCB is configured in factory with 0 to 2.5 V ADC input range for the AD7660, AD7664, and AD7675/7676/7677 and +/-5V for the AD7663/7665/ 7671; front-end amplifiers U6 and U7 set with a gain of +1, powered through the EVAL-CONTROL BOARD, and the on-board CNVST generation used.
On-board or external CNVST could be used. When an exter­nal CNVST signal is applied, this signal should have very low jitter and sharp edges to get the best noise performance of the part. Meanwhile, it is recommended to use the on-board CNVST generation which is done by dividing MCLK signal (20MHZ) by the numbers shown in Table I, which are en­tered in the software. Activity on BUSY pin of the ADC turns on the LED.
Table I. CNVST GENERATION
Part Division Factor Throughput Rate
AD7660 200 100KSPS
AD7662/68 40 500KSPS
AD7663 80 250KSPS
AD7664/50 35 571KSPS
AD7665 35 571KSPS
AD7671 20 1MSPS
AD7675 200 100KSPS
AD7676 35 571KSPS
AD7677 20 1MSPS
Conversion data is available at the output bus BD on U3, on the 40-pin connector P2, and on the 96-pin connector P3. Additionally, BD data is updated on the falling/rising edge of DBUSY and BBUSY on P3, low when BD data is valid are delayed from the BD data by about 20 ns to ease the inter­face. When either parallel or serial reading mode of the ADC is used, the data is available on this parallel bus. When serial reading mode of the ADC is used, the serial interface signals of the ADC are buffered and available on the 20-pin connec-
tor P1. When slave serial reading mode of the AD766X/AD767X is used, the external serial clock SCLK applied to the ADC is at half the MCLK frequency.
Power Supplies and Grounding
The evaluation board ground plane is separated into two sections: a plane for the digital interface circuitry and an ana­log plane for the analog input and external reference circuitry. To attain high resolution performance, the board was designed to ensure that all digital ground return paths do not cross the analog ground return paths.
The EVAL-AD766XCB/AD767XCB has three power supply blocks: a single 5V supply VA and the reference voltage circuitry, a digital 5V supply VL for the digital interface circuitry and the digital section of the ADC, and a selectable +/-12V (with a possibility of +/-15V with control Brd2) or +/-5V supply for the analog signal con­ditioning circuitry (SJ3). All supplies are decoupled to ground with 10 ␮F tantalum and 0.1 ␮F ceramic capacitors.
Analog Input Ranges
The analog front-end amplifier circuitry U6 and U7 allows flexible configuration changes such as positive or negative gain, input range scaling, filtering, addition of a DC compo­nent, use of different op-amp and supplies. Figure 1 shows the front end op-amp configuration used with the AD7660/7663/7664/7665/7671/7675/7676/7677. In some applications, it is desired to use a bipolar or wider analog input range like, for instance, ± 10V, ± 5V, ± 2.5V, or 0 to +5V. For the AD76XX parts which do not have directly those input ranges like the AD7660/7664/7675/7676/7677, by simple modifications of the input driver circuitry of the EVAL-AD766XCB/AD767XCB, bipolar and wider input ranges can be used without any performance degradation. Components values required and resulting full-scale ranges are shown in table IV and table V. In factory, the analog input of U6 is set at mid-scale (R6=R7=590⍀) for the AD7660/7664/7675/7676/7677. For AD7663/7665/7671, R7 is not connected to maintain the input at 0V (mid-scale). This allows a transition noise test without any other equipment. An FFT test can be done by applying a very low distortion AC source.

EVAL-CONTROL BOARD INTERFACE

The EVAL-AD766XCB/AD767XCB interfaces to the EVAL­CONTROL BRD2 through the 96-way connector.

RUNNING THE EVAL-AD766X/AD767XCB SOFTWARE

Software Description
The EVAL-AD766XCB/AD767XCB comes with software for analyzing the AD766X/AD767X. Through the EVAL-CON­TROL BRD2 one can perform a histogram to determine code transition noise, and Fast Fourier Transforms (FFT's) to determine the Signal-to-Noise Ratio (SNR), Signal-to-Noise­plus-Distortion (SNRD) and Total-Harmonic-Distortion (THD). The front-end PC software has four screens as shown in Figure 8,9,10 and 11. Figure 8 is the Setup Screen where input voltage range, sample rate, number of samples are selected. Figure 9 is the Histogram Screen, which allows the code distribution for DC input and computes the mean and standard deviation.
–2–
(SJ1) for the AD766X/AD767X
REV. PrK
(SJ2)
PRELIMINARY TECHNICAL DATA
EVAL-AD766XCB/AD767XCB
Figure 10 is the FFT Screen, which performs an FFT on the captured data, computes the Signal-to-Noise Ratio (SNR), Signal-to-Noise-plus-Distortion (SINAD) and total-Har­monic-Distortion (THD). Figure 11 is the time domain representation of the output. When the on-board CNVST generation is used, a synchronous FFT could be achieved by synchronizing the external AC generator with the Fsync signal (TP11) which is an exact division by 2 of MCLK.
TABLE II. JUMPER DESCRIPTION
Jumper Default position Function
Designation with the control
board ( Factory settings)
JP1 A Selection of the positive supply of the front-end amplifier U6. When JP1 is in posi-
tion A, the +12V supply from the control board is applied to JP3 otherwise VS+ on SJ3 is used.
Software Installation
- Double-Click on Setup.exe from the CD-ROM and follow the installation instructions.
NOTE: The software runs under Windows 95/98 only.
JP2 A Selection of the negative supply of the front-end amplifier U6. When JP2 is in posi-
tion A, the -12V supply from the control board is applied to JP4 otherwise VS- on SJ3 is used.
JP3 A Selection of the positive supply of the front-end amplifier U6. When JP3 is in posi-
tion A, the +5V supply from the control board is used otherwise JP1 output is used.
JP4 A Selection of the negative supply of the front-end amplifier U6. When JP4 is in posi-
tion A, the -5V supply from the control board is used otherwise JP2 output is used.
JP5 not A Selection of the master clock MCLK signal. When JP5 is in position A, the signal on
J4 is used otherwise the on-board 20 MHz clock is used as a MCLK signal. MCLK signal is used to generate the on-board CNVST signal and the external serial clock SCLK.
JP6 A, U3 side Selection of RDC ( Read during convert ). When the button of the switch is close to
J4 connector ( not A position ) and when the serial reading mode is selected, the data are read during conversion otherwise the data are read after conversion. JP6 has no use in parallel reading mode.
JP7 A, U3 side Selection of PD ( Powerdown ). When the button of the switch is close to J4 connec-
tor ( not A position ), the ADC is in power-down mode.
JP8 A, U3 side Spare switch.
JP9 A, U3 side Selection of RESET. When the button of the switch is close to J4 connector ( not A
position ), the ADC is reset.
JP10 A, U3 side Selection of SER/PAR ( serial/parallel reading mode ). When the button of the switch
is close to J4 connector ( not A position ), the data are read in serial mode otherwise the data are read in parallel mode.
JP11 not A, SJ4 side Selection of OC/2C ( coding ). When the button of the switch is close to J4 connector
( not A position ), the ADC uses a straight binary coding otherwise the twos comple­ment coding is used.
JP12 A, U3 side Selection of WARP. When the button of the switch is close to J4 connector ( not A
position ), the ADC uses the WARP mode which is the fastest one. With the AD7660, JP12 is a spare switch.
REV PrK
–3–
PRELIMINARY TECHNICAL DATA
EVAL-AD766XCB/AD767XCB
TABLE II. JUMPER DESCRIPTION
Jumper Default position Function
Designation with the control
board ( Factory settings)
JP13 A, U3 side Selection of IMPULSE. When the button of the switch is close to J4 connector
( not A position ), the ADC uses the IMPULSE mode which is the mode with the lowest power dissipation. With the AD7660, JP13 is a spare switch.
JP14 A, U3 side TEST1. For factory use only and it is pull down.
JP15 A, U3 side TEST0. For factory use only and it is pull down.
JP16 A, U3 side Selection of EXT/INT ( use of external or internal serial clock ). When the button of
the switch is close to J4 connector ( not A position ) and when the serial reading mode is selected, the data are read with an external serial clock SCLK generated from the master clock MCLK otherwise the data are read with the ADC serial clock. When external serial clock reading mode is selected, MCLK has to be fast enough to be able the read the data properly as explained in the AD766X data sheet. JP16 has no use in parallel reading mode.
JP17 A, U3 side Selection of INVSYNC ( SYNC active level ). When the button of the switch is close
to J4 connector ( not A position ) and when the master serial reading mode is se lected, the SYNC signal is active Low. JP17 has no use in parallel reading mode or slave serial reading mode.
JP18 A, U3 side Selection of INVSCLK ( SCLK active edge ). When the button of the switch is close
to J4 connector ( not A position ) and when the serial reading mode is selected, INVSCLK is high. JP18 has no use in parallel reading mode.
JP19 not A Selection of CNVST signal. When JP19 is in position A, the signal on J3 is used
otherwise the on-board CNVST generation is used. MCLK signal is used to generate the on-board CNVST signal.
JP20 not A Selection of REF signal. When JP20 is in position A, the REF is buffered. When
JP20 is not in position A, the REF is not buffered.
Table III. EVAL-AD766XCB/AD767XCB Test Points
Test Point Available Signal
TP1 DGND Digital ground TP2 DGND Digital ground TP3 SIG+ ADC Analog input TP4 AGND Analog ground close to SIG+ TP 5 REF ADC Reference input TP6 BUSY ADC BUSY signal TP7 RD ADC RD signal TP8 CS ADC CS signal TP9 AGND Analog ground close to REF TP10 CNVST ADC CNVST signal TP11 F TP12 OVDD ADC digital output supply TP13 DVDD ADC digital core supply TP14 VANA1 ADC analog supply TP15 AGND Analog ground close to SIG­TP16 SI G- ADC Analog input
SYNC
MCLK divided by 2
Table IV. Component values Vs. Input ranges ( AD7660 )
Input range R1 R3 R6 R7
± 10V 8k⍀ 1k⍀ 8k⍀ 10k⍀ ± 5V 8k⍀ 2k⍀ 6.67k⍀ 10k⍀
0 to -5V 8k⍀ 8k⍀ 0⍀ none
Table V. Component values Vs. Input ranges ( AD7664 )
Input range R1 R3 R6 R7
± 10V 2k⍀ 250⍀ 8k⍀ 10k⍀ ± 5V 2k⍀ 500⍀ 6.67k⍀ 10k⍀
0 to -5V 1k⍀ 1k⍀ 0⍀ none
–4–
REV. PrK
PRELIMINARY TECHNICAL DATA
EVAL-AD766XCB/AD767XCB

TESTING METHODS

Histogram
To perform a histogram test, apply a DC signal to the input. It is advised to filter the signal to make the DC Source noise com­patible with that of the ADC. C26 provides this filtering.
AC Testing
To perform an AC test, apply a sinusoidal signal to the evaluation board. Low distortion, better than 100dB, is required to allow true evaluation of the part. One possibility is to filter the input signal from the AC source. There is no suggested bandpass filter but consideration should be taken in the choice. Furthermore, when the full-scale input range is more than a few Vpp, it is recommended that you use the on board amplifier to amplify the signal, thus preventing the filter from distorting the input signal.
Please refer to Figures 8,9,10 and 11 to see the screens of the software.
Software Description
The AD16bit.exe is the software which allows you to analyze different performance characteristics of the AD766X, AD767X, AD97X and AD67X 16-bit ADC family. The soft­ware allows you to test the histogram as well as perform different AC tests.
Setup Requirements
- Evaluation Control Board 2 (ADSP2189)
- Evaluation Board
- Power Supply (AC 15V/1A source could be bought from ADI)
- Parallel Port Cable (provided with the evaluation control board)
- AC Source (low distortion)
- DC Source (low noise)
- Bandpass Filter (value based on your signal frequency, low distortion)
USE OF EVAL-AD766XCB/AD767XCB AS STAND­ALONE EVALUATION BOARD
You have the option of using the EVAL-AD766XCB/AD767XCB as a stand-alone evaluation board. This method does not require the control board, nor does it require use of the accompanied software. The digital output will now be available on P1 (20-pin connector, for use in serial mode) or P2 (40-pin connector, for use in parallel mode). Cer­tain modifications have to be made on the board to allow proper operation of the evaluation board. Refer to Table II to obtain the jumper positions for stand-alone operation. When in stand­alone, CNVST could be externally applied or is generated internally according to Table I.
Please refer to Figure 1 to obtain the data output pins on the connectors.
Data is updated on the falling edge of BUSY. BCS and BWR are inputs to the FPGA and are connected to P1 and P2. When BCS, CONTROL are low and BWR is high, which is the default value defined by the on-board pull-up/pull-down resistors, the data bus BD available on the P2 connector is enabled.
SUPPLYING THE BOARD FOR STAND-ALONE USE
SJ1 is the analog supply. Connect VA+ to +5V and AGND to GND. SJ2 is the digital supply. SJ2 requires the same values as SJ1, and SJ2 may be connected to SJ1. SJ3 is the supply for the front end amplifier (U6). Connect +12V to VS+, GND to AGND, and -12V to VS-.
REV PrK
–5–
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