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AD7675 a
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Analog Devices AD7675 a Datasheet

16-Bit, 100 kSPS,
a
FEATURES Throughput: 100 kSPS INL: 1.5 LSB Max (0.0015% of Full Scale) 16 Bits Resolution with No Missing Codes S/(N+D): 94 dB Typ @ 45 kHz THD: –110 dB Typ @ 45 kHz Differential Input Range: 2.5 V Both AC and DC Specifications No Pipeline Delay Parallel (8 Bits/16 Bits) and Serial 5 V/3 V Interface SPI™/QSPI™/MICROWIRE™/DSP Compatible Single 5 V Supply Operation 15 mW Typical Power Dissipation, 15 W @ 100 SPS Power-Down Mode: 7 W Max Packages: 48-Lead Quad Flatpack (LQFP),
46-Lead Frame Chip Scale (LFCSP) Pin-to-Pin Compatible with the AD7660 Replacement of AD676, AD677
APPLICATIONS CT Scanners Data Acquisition Instrumentation Spectrum Analysis Medical Instruments Battery-Powered Systems Process Control
Differential ADC
AD7675

FUNCTIONAL BLOCK DIAGRAM

AV DD AGND REF REFGND
AD7675
IN+
IN–
PD
RESET
SWITCHED
CAP DAC
CLOCK
CONTROL LOGIC AND
CALIBRATION CIRCUITRY
CNVST

PulSAR Selection

Type/kSPS 100–250 500–570 1000
Pseudo AD7660 AD7650 Differential AD7664
True Bipolar AD7663 AD7665 AD7671
True Differential AD7675 AD7676 AD7677
DGNDDVD D
SERIAL
PORT
PARALLEL
INTERFACE
16
OVD D
OGND
SER/PAR
BUSY
DATA[15:0]
CS
RD
OB/2C
BYTESWAP
*

GENERAL DESCRIPTION

The AD7675 is a 16-bit, 100 kSPS, charge redistribution SAR, fully differential analog-to-digital converter that operates from a single 5 V power supply. The part contains a high speed 16-bit sampling ADC, an internal conversion clock, error correction circuits, and both serial and parallel system interface ports.
The AD7675 is hardware factory calibrated and is comprehensively tested to ensure such ac parameters as signal-to-noise ratio (SNR) and total harmonic distortion (THD), in addition to the more traditional dc parameters of gain, offset, and linearity.
It is fabricated using Analog Devices’ high performance, 0.6 micron CMOS process and is available in a 48-lead LQFP or a tiny 48-lead LFCSP with operation specified from –40°C to +85°C.
*Patent pending
SPI and QSPI are trademarks of Motorola Inc. MICROWIRE is a trademark of National Semiconductor Inc.
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

PRODUCT HIGHLIGHTS

1. Excellent INL The AD7675 has a maximum integral nonlinearity of 1.5 LSB with no missing 16-bit code.
2. Superior AC Performances The AD7675 has a minimum dynamic of 92 dB, 94 dB typical.
3. Fast Throughput The AD7675 is a 100 kSPS, charge redistribution, 16-bit SAR ADC with internal error correction circuitry.
4. Single-Supply Operation The AD7675 operates from a single 5 V supply and typically dissipates only 17 mW. Its power dissipation decreases with the throughput to, for instance, only 15 µW at a 100 SPS throughput. It consumes 7 µW maximum when in power-down.
5. Serial or Parallel Interface Versatile parallel (8 bits or 16 bits) or 2-wire serial interface arrangement compatible with either 3 V or 5 V logic.
AD7675–SPECIFICATIONS
(–40C to +85C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)
Parameter Conditions Min Typ Max Unit
RESOLUTION 16 Bits
ANALOG INPUT
Voltage Range V Operating Input Voltage V Analog Input CMRR f Input Current 100 kSPS Throughput 1 µA
– V
IN+
IN–
to AGND –0.1 +3 V
IN+, VIN–
= 10 kHz 79 dB
IN
–V
REF
+V
REF
V
Input Impedance See Analog Input Section
THROUGHPUT SPEED
Complete Cycle 10 µs Throughput Rate 0 100 kSPS
DC ACCURACY
Integral Linearity Error –1.5 +1.5 LSB
1
No Missing Codes 16 Bits Transition Noise 0.35 LSB +Full-Scale Error –Full-Scale Error Zero Error
2
2
2
–22 +22 LSB –22 +22 LSB –8 +8 LSB
Power Supply Sensitivity AVDD = 5 V ± 5% ±0.5 LSB
AC ACCURACY
Signal-to-Noise f
= 20 kHz 92 94 dB
IN
fIN = 45 kHz 94 dB
Spurious Free Dynamic Range fIN = 20 kHz 104.5 110 dB
fIN = 45 kHz 110 dB
Total Harmonic Distortion fIN = 20 kHz –110 –103.5 dB
fIN = 45 kHz –110 dB
Signal-to-(Noise+Distortion) fIN = 20 kHz 92 94 dB
fIN = 45 kHz 94 dB fIN = 45 kHz, –60 dB Input 34 dB
3
3
3
3
3
3
3
3
3
–3 dB Input Bandwidth 3.9 MHz
SAMPLING DYNAMICS
Aperture Delay 2ns Aperture Jitter 5 ps rms Transient Response Full-Scale Step 8.75 µs
REFERENCE
External Reference Voltage Range 2.3 2.5 AVDD – 1.85 V External Reference Current Drain 100 kSPS Throughput 35 µA
DIGITAL INPUTS
Logic Levels
V
IL
V
IH
I
IL
I
IH
–0.3 +0.8 V
2.0 DVDD + 0.3 V –1 +1 µA –1 +1 µA
DIGITAL OUTPUTS
Data Format Parallel or Serial 16-Bit Conversion Results Available Pipeline Delay Immediately After Completed Conversion
I
V
OL
V
OH
= 1.6 mA 0.4 V
SINK
I
= –100 µA OVDD – 0.6 V
SOURCE
POWER SUPPLIES
Specified Performance
AVDD 4.75 5 5.25 V DVDD 4.75 5 5.25 V OVDD 2.7 5.25
4
V
Operating Current 300 kSPS Throughput
AVDD 3mA
5
DVDD
5
OVDD
Power Dissipation
In Power-Down Mode
TEMPERATURE RANGE
Specified Performance T
NOTES
1
LSB means Least Significant Bit. With the ± 2.5 V input range, one LSB is 76.3 µV.
2
See Definition of Specifications section. These specifications do not include the error contribution from the external reference.
3
All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale unless otherwise specified.
4
The max should be the minimum of 5.25 V and DVDD + 0.3 V.
5
Tested in Parallel Reading Mode.
6
With OVDD below DVDD + 0.3 V and all digital inputs forced to DVDD or DGND, respectively.
7
Contact factory for extended temperature range.
5
5
7
100 kSPS Throughput 17 25 mW 100 SPS Throughput 15 µW
MIN
to T
MAX
–40 +85 °C
Specifications subject to change without notice.
–2–
750 µA
7.5 µA
7 µW
REV. A
AD7675
TIMING SPECIFICATIONS
(–40C to +85C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)
Symbol Min Typ Max Unit
Refer to Figures 11 and 12
Convert Pulsewidth t Time Between Conversions t CNVST LOW to BUSY HIGH Delay t BUSY HIGH All Modes Except in Master Serial Read t
1
2
3
4
5ns 10 µs
30 ns
1.25 µs
After Convert Mode Aperture Delay t End of Conversion to BUSY LOW Delay t Conversion Time t Acquisition Time t RESET Pulsewidth t
5
6
7
8
9
10 ns
8.75 µs 10 ns
2ns
1.25 µs
Refer to Figures 13, 14, and 15 (Parallel Interface Modes)
CNVST LOW to DATA Valid Delay t DATA Valid to BUSY LOW Delay t Bus Access Request to DATA Valid t Bus Relinquish Time t
Refer to Figures 16 and 17 (Master Serial Interface Modes)
1
CS LOW to SYNC Valid Delay t CS LOW to Internal SCLK Valid Delay t CS LOW to SDOUT Delay t CNVST LOW to SYNC Delay t
SYNC Asserted to SCLK First Edge Delay Internal SCLK Period Internal SCLK HIGH Internal SCLK LOW SDOUT Valid Setup Time SDOUT Valid Hold Time SCLK Last Edge to SYNC Delay
2
2
2
2
2
2
2
CS HIGH to SYNC HI-Z t CS HIGH to Internal SCLK HI-Z t CS HIGH to SDOUT HI-Z t
BUSY HIGH in Master Serial Read After Convert
2
CNVST LOW to SYNC Asserted Delay t SYNC Deasserted to BUSY LOW Delay t
10
11
12
13
14
15
16
17
t
18
t
19
t
20
t
21
t
22
t
23
t
24
25
26
27
t
28
29
30
45 ns
515ns
525 ns 3ns 25 40 ns 12 ns 7ns 4ns 2ns 3ns
See Table I µs
1.25 µs
25 ns
1.25 µs
40 ns
10 ns 10 ns 10 ns
10 ns 10 ns 10 ns
Refer to Figures 18 and 19 (Slave Serial Interface Modes)
External SCLK Setup Time t External SCLK Active Edge to SDOUT Delay t SDIN Setup Time t SDIN Hold Time t External SCLK Period t External SCLK HIGH t External SCLK LOW t
NOTES
1
In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.
2
In serial master read during convert mode. See Table I for serial master read after convert mode.
Specifications subject to change without notice.
31
32
33
34
35
36
37
5ns 318ns 5ns 5ns 25 ns 10 ns 10 ns
REV. A
–3–
AD7675

Table I. Serial Clock Timings in Master Read after Convert

DIVSCLK[1] 0011 DIVSCLK[0] 0101Unit
SYNC to SCLK First Edge Delay Minimum t Internal SCLK Period Minimum t Internal SCLK Period Typical t Internal SCLK HIGH Minimum t Internal SCLK LOW Minimum t SDOUT Valid Setup Time Minimum t SDOUT Valid Hold Time Minimum t SCLK Last Edge to SYNC Delay Minimum t Busy High Width Maximum t
18
19
19
20
21
22
23
24
28
3171717ns 25 50 100 200 ns 40 70 140 280 ns 12 22 50 100 ns 7214999ns 4181818ns 243089ns 360140 300 ns 2 2.5 3.5 5.75 µs

ABSOLUTE MAXIMUM RATINGS

Analog Inputs
2
IN+
, IN–2, REF, REFGND . . . . . . . . . . . . . . . . . . . . . . . .
1
. . . . . . . . . . . . . . . . . . . . AVDD + 0.3 V to AGND – 0.3 V
Ground Voltage Differences
AGND, DGND, OGND . . . . . . . . . . . . . . . . . . . . . ±0.3 V
Supply Voltages
AVDD, DVDD, OVDD . . . . . . . . . . . . . . . . –0.3 V to +7 V
AVDD to DVDD,
AVDD to OVDD . . . . . . . . . . . . . . ±7 V
DVDD to OVDD . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Digital Inputs . . . . . . . . . . . . . . . . –0.3 V to DVDD + 0.3 V
Internal Power Dissipation Internal Power Dissipation
3
. . . . . . . . . . . . . . . . . . . . 700 mW
4
. . . . . . . . . . . . . . . . . . . . . . 2.5 W
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150° C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range
(Soldering 10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2
See Analog Input section.
3
Specification is for device in free air: 48-Lead LQFP: ␪JA = 91°C/W, ␪JC = 30°C/W.
4
Specification is for device in free air: LFCSP: ␪JA = 26°C/W

ORDERING GUIDE

I
1.6mA
TO OUTPUT
PIN
C
L 1
60pF
500A
NOTE
1
IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD
OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.
C
L
OL
1.4V
I
OH
Figure 1. Load Circuit for Digital Interface Timing, SDOUT, SYNC, SCLK Outputs, CL = 10 pF
0.8V
t
DELAY
2V
0.8V
2V
t
DELAY
2V
0.8V
Figure 2. Voltage Reference Levels for Timing
Model Temperature Range Package Description Option
AD7675AST –40°C to +85°C Quad Flatpack (LQFP) ST-48 AD7675ASTRL –40°C to +85°C Quad Flatpack (LQFP) ST-48 AD7675ACP –40°C to +85°CChip Scale (LFCSP) CP-48 AD7675ACPRL –40°C to +85°CChip Scale (LFCSP) CP-48 EVAL-AD7675CB EVAL-CONTROL BRD2
NOTES
1
This board can be used as a stand-alone evaluation board or in conjunction with the EVAL-CONTROL BRD2 for evaluation/ demonstration purposes.
2
This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.
1
2
Evaluation Board Controller Board
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7675 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
–4–
Package
WARNING!
ESD SENSITIVE DEVICE
REV. A
AD7675

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Type Description
1 AGND P Analog Power Ground Pin 2 AVDD P Input Analog Power Pins. Nominally 5 V. 3, 6, 7, NC No Connect 40–42, 44–48 4 BYTESWAP DI
5OB/2C DI Straight Binary/Binary Two’s Complement. When OB/2C is HIGH, the digital output is
8 SER/PAR DI Serial/Parallel Selection Input. When LOW, the parallel port is selected; when HIGH, the
9, 10 DATA[0:1] DO Bit 0 and Bit 1 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, these outputs are
11, 12 DATA[2:3] or DI/O When SER/PAR is LOW, these outputs are used as Bit 2 and Bit 3 of the Parallel Port
DIVSCLK[0:1] When SER/PAR is HIGH, EXT/INT is LOW and RDC/SDIN is LOW, which is the serial
13 DATA[4] DI/O When SER/PAR is LOW, this output is used as the Bit 4 of the Parallel Port Data Output Bus.
or EXT/INT When SER/PAR is HIGH, this input, part of the serial port, is used as a digital select input for
14 DATA[5] DI/O When SER/PAR is LOW, this output is used as the Bit 5 of the Parallel Port Data Output Bus.
or INVSYNC When SER/PAR is HIGH, this input, part of the serial port, is used to select the active state of
15 DATA[6] DI/O When SER/PAR is LOW, this output is used as the Bit 6 of the Parallel Port Data Output Bus.
or INVSCLK
16 DATA[7] DI/O When SER/PAR is LOW, this output is used as the Bit 7 of the Parallel Port Data Output Bus.
or RDC/SDIN When SER/PAR is HIGH, this input, part of the serial port, is used as either an external data
17 OGND P Input/Output Interface Digital Power Ground 18 OVDD P Input/Output Interface Digital Power. Nominally at the same supply than the supply of the
19 DVDD P Digital Power. Nominally at 5 V. 20 DGND P Digital Power Ground
Parallel Mode Selection (8-Bit/16-Bit). When LOW, the LSB is output on D[7:0] and the MSB is output on D[15:8]. When HIGH, the LSB is output on D[15:8] and the MSB is output on D[7:0].
straight binary; when LOW, the MSB is inverted resulting in a two’s complement output from its internal shift register.
serial interface mode is selected and some bits of the DATA bus are used as a serial port.
in high impedance.
Data Output Bus.
master read after convert mode. These inputs, part of the serial port, are used to slow down, if desired, the internal serial clock that clocks the data output. In the other serial modes, these pins are high impedance outputs.
choosing the internal or an external data clock. With EXT/INT tied LOW, the internal clock is selected on SCLK output. With EXT/INT set to a logic HIGH, output data is synchronized to an external clock signal connected to the SCLK input.
the SYNC signal. When LOW, SYNC is active HIGH. When HIGH, SYNC is active LOW.
When SER/PAR is HIGH, this input, part of the serial port, is used to invert the SCLK signal. It is active in both master and slave mode.
input or a read mode selection input depending on the state of EXT/INT. When EXT/INT is HIGH, RDC/SDIN could be used as a data input to daisy-chain the con-
version results from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on DATA with a delay of 16 SCLK periods after the initiation of the read sequence. When EXT/INT is LOW, RDC/SDIN is used to select the read mode. When RDC/ SDIN is HIGH, the data is output on SDOUT during conversion. When RDC/SDIN is LOW, the data is output on SDOUT only when the conversion is complete.
host interface (5 V or 3 V).
REV. A
–5–
AD7675
PIN FUNCTION DESCRIPTIONS (continued)
Pin No. Mnemonic Type Description
21 DATA[8] DO When SER/PAR is LOW, this output is used as the Bit 8 of the Parallel Port Data Output Bus.
or SDOUT When SER/PAR is HIGH, this output, part of the serial port, is used as a serial data output
synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7675 provides the conversion result, MSB first, from its internal shift register. The DATA format is determined by the logic level of OB/2C. In serial mode, when EXT/INT is LOW, SDOUT is valid on both edges of SCLK. In serial mode, when EXT/INT is HIGH: If INVSCLK is LOW, SDOUT is updated on SCLK rising edge and valid on the next falling edge. If INVSCLK is HIGH, SDOUT is updated on SCLK falling edge and valid on the next rising edge.
22 DATA[9] DI/O When SER/PAR is LOW, this output is used as the Bit 9 of the Parallel Port Data Output Bus.
or SCLK When SER/PAR is HIGH, this pin, part of the serial port, is used as a serial data clock input
or output, dependent upon the logic state of the EXT/INT Pin. The active edge where the data SDOUT is updated depends upon the logic state of the INVSCLK Pin.
23 DATA[10] DO When SER/PAR is LOW, this output is used as the Bit 10 of the Parallel Port Data Output Bus.
or SYNC When SER/PAR is HIGH, this output, part of the serial port, is used as a digital output frame
synchronization for use with the internal data clock (EXT/INT = Logic LOW). When a read sequence is initiated and INVSYNC is LOW, SYNC is driven HIGH and remains HIGH while SDOUT output is valid. When a read sequence is initiated and INVSYNC is HIGH, SYNC is driven LOW and remains LOW while SDOUT output is valid.
24 DATA[11] DO When SER/PAR is LOW, this output is used as the Bit 11 of the Parallel Port Data Output Bus.
or RDERROR When SER/PAR is HIGH and EXT/INT is HIGH, this output, part of the serial port, is used
as an incomplete read error flag. In slave mode, when a data read is started and not complete when the following conversion is complete, the current data is lost and RDERROR is pulsed high.
25–28 DATA[12:15] DO Bit 12 to Bit 15 of the Parallel Port Data output bus. These pins are always outputs regardless
of the state of SER/PAR.
29 BUSY DO Busy Output. Transitions HIGH when a conversion is started, and remains HIGH until the
conversion is complete and the data is latched into the on-chip shift register. The falling edge of BUSY could be used as a data ready clock signal.
30 DGND P Must Be Tied to Digital Ground 31 RD DI Read Data. When CS and RD are both LOW, the interface parallel or serial output bus is enabled. 32 CS DI Chip Select. When CS and RD are both LOW, the interface parallel or serial output bus is
enabled. CS is also used to gate the external serial clock.
33 RESET DI Reset Input. When set to a logic HIGH, reset the AD7675. Current conversion if any is aborted. 34 PD DI Power-Down Input. When set to a logic HIGH, power consumption is reduced and conver-
sions are inhibited after the current one is completed.
35 CNVST DI Start Conversion. If CNVST is HIGH when the acquisition phase (t
falling edge on CNVST puts the internal sample/hold into the hold state and initiates a conversion. This mode is the most appropriate if low sampling jitter is desired. If CNVST is LOW when the acquisition phase (t
) is complete, the internal sample/hold is put into the hold
8
state and a conversion is immediately started. 36 AGND P Must Be Tied to Analog Ground 37 REF AI Reference Input Voltage 38 REFGND AI Reference Input Analog Ground 39 IN– AI Differential Negative Analog Input 43 IN+ AI Differential Positive Analog Input
NOTES AI = Analog Input DI = Digital Input DI/O = Bidirectional Digital DO = Digital Output P = Power
) is complete, the next
8
–6–
REV. A
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