Analog Devices AD7667CB, AD7667ASTRL, AD7667AST, AD7667ACPRL, AD7667ACP Datasheet
REV. PrA
Preliminary Technical Data
PRELIMINARY TECHNICAL DATA
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
a
AD7667
*
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2002
16-Bit 1 MSPS SAR Unipolar ADC with Ref
FUNCTIONAL BLOCK DIAGRAM
SWITCHED
CAP DAC
16
CONTROL LOGIC AND
CALIBRATION CIRCUITRY
CLOCK
AD7667
DATA[15:0]
BUSY
RD
CS
SER/PAR
OB/2C
OGND
OVDD
DGNDDVDD
AVDD
AGND
REF REFGND
IN
INGND
PD
RESET
SERIAL
PORT
PARALLEL
INTERFACE
CNVSTWARP IMPULSE
2.5 V REF
PDREF
PDBUF
REFBUFIN
BYTESWAP
FEATURES
Throughput:
1 MSPS (Warp Mode)
800 kSPS (Normal Mode)
INL: ±2.5 LSB Max (±0.0038% of Full Scale)
16 Bits Resolution with No Missing Codes
Analog Input Voltage Range: 0 V to 2.5 V
No Pipeline Delay
Parallel and Serial 5 V/3 V Interface
SPI
TM
/QSPITM/MICROWIRETM/DSP Compatible
Single 5 V Supply Operation
Power Dissipation
112 mW Typ without REF, 122 mW Typ with REF
15 W @ 100 SPS
Power-Down Mode: 7 W Max
Package: 48-Lead Quad Flat Pack (LQFP);
48-Lead Chip Scale Package (LFCSP);
Pin-to-Pin Compatible with PulSAR ADCs
APPLICATIONS
Data Acquisition
Instrumentation
Digital Signal Processing
Spectrum Analysis
Medical Instruments
Battery-Powered Systems
Process Control
GENERAL DESCRIPTION
The AD7667 is a 16-bit, 1 MSPS, charge redistribution SAR,
analog-to-digital converter that operates from a single 5 V
power supply. The part contains a high-speed 16-bit sampling
ADC, an internal conversion clock, internal reference, error
correction circuits, and both serial and parallel system interface ports.
It features a very high sampling rate mode (Warp) and, for
asynchronous conversion rate applications, a fast mode
(Normal) and, for low power applications, a reduced power
mode (Impulse) where the power is scaled with the throughput.
It is fabricated using Analog Devices’ high-performance, 0.6 micron
CMOS process, with correspondingly low cost and is available in a
48-lead LQFP and a tiny 48-lead LFCSP with operation specified from –40°C to +85°C.
PRODUCT HIGHLIGHTS
1. Fast Throughput
The AD7667 is a 1 MSPS, charge redistribution, 16-bit
SAR ADC with internal error correction circuitry.
2. Internal Reference
The AD7667 has an internal reference and allows for an
external reference to be used.
3. Superior INL
The AD7667 has a maximum integral nonlinearity of 2.5
LSB with no missing 16-bit code.
4. Single-Supply Operation
The AD7667 operates from a single 5 V supply and dissipates
a typical of 112 mW. In impulse mode, its power dissipation decreases with the throughput. It consumes 7 µW
maximum when in power-down.
5. Serial or Parallel Interface
Versatile parallel or 2-wire serial interface arrangement
compatible with both 3 V or 5 V logic.
*Patent pending.
SPI and QSPI are trademarks of Motorola Inc.
MICROWIRE ia a trademark of National Semiconductor Corporation
Pseudo AD7651 AD7650/52 AD7653
Differential AD7660/61 AD7664/66 AD7667
True Bipolar AD7663 AD7665 AD7671
True AD7675 AD7676 AD7677
Differential
Type / kSPS
100 - 250
500 - 570
1000
PulSAR Selection
PRELIMINARY TECHNICAL DATA
REV. PrA
–2–
AD7667
Parameter Conditions Min Typ Max Unit
RESOLUTION 16 Bits
ANALOG INPUT
Voltage Range V
IN
– V
INGND
0V
REF
V
Operating Input Voltage V
IN
–0.1 +3 V
V
INGND
–0.1 +0.5 V
Analog Input CMRR fIN = 10 kHz TB D dB
Input Current 1 MSPS Throughput 11 µA
Input Impedance See Analog Input Section
THROUGHPUT SPEED
Complete Cycle In Warp Mode 1 µs
Throughput Rate In Warp Mode 1 1000 kSPS
Time Between Conversions In Warp Mode 1 ms
Complete Cycle In Normal Mode 1.25 µs
Throughput Rate In Normal Mode 0 800 kSPS
Complete Cycle In Impulse Mode 1.5 µs
Throughput Rate In Impulse Mode 0 666 kSPS
DC ACCURACY
Integral Linearity Error –2.5 +2.5 LSB
1
No Missing Codes 16 Bits
Transition Noise 0.7 LSB
Full-Scale Error
2
REF = 2.5 V ±TBD % of FSR
Unipolar Zero Error
2
±TBD ±TBD LSB
Power Supply Sensitivity AVDD = 5 V ± 5% ±TBD LSB
AC ACCURACY
Signal-to-Noise f
IN
= 100 kHz 90 d B
Spurious Free Dynamic Range fIN = 100 kHz 100 dB
Total Harmonic Distortion fIN = 45 kHz -100 dB
fIN = 100 kHz -100 dB
Signal-to-(Noise+Distortion) fIN = 100 kHz 90 d B
–60 dB Input, fIN = 100 kHz 30 d B
–3 dB Input Bandwidth TB D MH z
SAMPLING DYNAMICS
Aperture Delay 2ns
Aperture Jitter 5 ps rms
Transient Response Full-Scale Step 250 ns
REFERENCE
Internal Reference Voltage @
25C
TBD 2.5 TBD V
Internal Reference Source Current TBD µA
Internal Reference Temp Drift
–40C to +85C TBD ppm/C
Internal Reference Temp Drift
0C to +70C TBD ppm/C
Turn-on Settling Time TBD
External Reference Voltage Range 2.3 2.5 AVDD – 1.85 V
External Reference Current Drain 1 MSPS Throughput TBD µA
Temperature Pin
Voltage Output @
25C 313 mV
Temperature Sensitivity 1 mV/C
Output Resistance 4.3 k
DIGITAL INPUTS
Logic Levels
V
IL
–0.3 +0.8 V
V
IH
2.0 OVDD + 0.3 V
I
IL
–1 +1 µA
I
IH
–1 +1 µA
DIGITAL OUTPUTS
Data Format Parallel or Serial 16-Bits
Pipeline Delay Conversion Results Available
Immediately after
Completed Conversion
V
OL
I
SINK
= 1.6 mA 0.4 V
V
OH
I
SOURCE
= –500 µA OVDD – 0.6 V
POWER SUPPLIES
Specified Performance
AVDD 4.75 5 5.25 V
DVDD 4.75 5 5.25 V
OVDD 2.7 5.25
9
V
–SPECIFICATIONS
(–40C to +85C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)
REV. PrA
PRELIMINARY TECHNICAL DATA
–3–
AD7667
Parameter Conditions Min Typ Max Unit
TIMING SPECIFICATIONS
Symbol Min Typ Max Unit
REFER TO FIGURES 11 AND 12
Convert Pulsewidth t
1
5ns
Time Between Conversions t
2
1/1.25/1.5 Note 1 µs
(Warp Mode/Normal Mode/Impulse Mode)
CNVST LOW to BUSY HIGH Delay t
3
30 ns
BUSY HIGH All Modes Except in t
4
0.75/1/1.25 µs
Master Serial Read After Convert Mode
(Warp Mode/Normal Mode/Impulse Mode)
Aperture Delay t
5
2ns
End of Conversion to BUSY LOW Delay t
6
10 ns
Conversion Time t
7
0.75/1/1.25 µs
(Warp Mode/Normal Mode/Impulse Mode)
Acquisition Time t
8
250 ns
RESET Pulsewidth t
9
10 ns
REFER TO FIGURES 13, 14, AND 15 (Parallel Interface Modes)
CNVST LOW to DATA Valid Delay t
10
0.75/1/1.25 µs
(Warp Mode/Normal Mode/Impulse Mode)
DATA Valid to BUSY LOW Delay t
11
45 ns
Bus Access Request to DATA Valid t
12
40 ns
Bus Relinquish Time t
13
515ns
REFER TO FIGURES 16 AND 17 (Master Serial Interface Modes)
2
CS LOW to SYNC Valid Delay t
14
10 ns
CS LOW to Internal SCLK Valid Delay
2
t
15
10 ns
CS LOW to SDOUT Delay t
16
10 ns
CNVST LOW to SYNC Delay t
17
25/275/525 ns
(Warp Mode/Normal Mode/Impulse Mode)
SYNC Asserted to SCLK First Edge Delay t
18
3ns
Internal SCLK Period
3
t
19
25 40 ns
Internal SCLK HIGH
3
t
20
12 ns
Internal SCLK LOW
3
t
21
7ns
SDOUT Valid Setup Time
3
t
22
4ns
SDOUT Valid Hold Time
3
t
23
2ns
SCLK Last Edge to SYNC Delay
3
t
24
3
CS HIGH to SYNC HI-Z t
25
10 ns
CS HIGH to Internal SCLK HI-Z t
26
10 ns
CS HIGH to SDOUT HI-Z t
27
10 ns
BUSY HIGH in Master Serial Read after Convert
3
t
28
See Table I µs
(Warp Mode/Normal Mode/Impulse Mode)
CNVST LOW to SYNC Asserted Delay t
29
0.75/1/1.25 µs
(Warp Mode/Normal Mode/Impulse Mode)
SYNC Deasserted to BUSY LOW Delay t
30
25 ns
(–40C to +85C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)
Operating Current
4
1 MSPS Throughput
AVDD
5
TBD mA
DVDD
5
TBD mA
OVDD
5
TBD µA
Power Dissipation
5
without REF 1 MSPS Throughput 112 mW
100 SPS Throughput
6
15 µW
In Power-Down Mode
7
TBD µW
Power Dissipation
5
with REF 1 MSPS Throughput 122 mW
100 SPS Throughput
6
10.015 mW
In Power-Down Mode
7
TBD µW
TEMPERATURE RANGE
8
Specified Performance T
MIN
to T
MAX
–40 +85
°C
NOTES
1
LSB means Least Significant Bit. With the 0 V to 2.5 V input range, one LSB is 38.15 µV.
2
See Definition of Specifications section. These specifications do not include the error contribution from the external reference.
3
All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale unless otherwise specified.
4
In warp mode.
5
Tested in parallel reading mode using external reference.
6
In impulse mode with external REF.
7
With all digital inputs forced to DVDD or DGND respect
ively.
8
Contact factory for extended temperature range.
9
The max should be the minimum of 5.25V and DVDD+0.3 V.
Specifications subject to change without notice.
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PRELIMINARY TECHNICAL DATA
–4–
AD7667
Table I. Serial clock timings in Master Read after Convert
DIVSCLK[1] 0011unit
DIVSCLK[0] 0101
SYNC to SCLK First Edge Delay Minimum t
18
3 171717ns
Internal SCLK Period minimum t
19
25 50 100 200 ns
Internal SCLK Period typical t
19
40 70 140 280 ns
Internal SCLK HIGH Minimum t
20
12 22 50 100 ns
Internal SCLK LOW Minimum t
21
7 214999ns
SDOUT Valid Setup Time Minimum t
22
4 181818ns
SDOUT Valid Hold Time Minimum t
23
2 4 3089ns
SCLK Last Edge to SYNC Delay Minimum t
24
3 60 140 300 ns
Busy High Width Maximum (Warp) t
24
1.5 2 3 5.25 µs
Busy High Width Maximum (Normal) t
24
1.75 2.25 3.25 5.55 µs
Busy High Width Maximum (Impulse) t
24
2 2.5 3.5 5.75 µs
REFER TO FIGURES 18 AND 20 (Slave Serial Interface Modes)
2
External SCLK Setup Time t
31
5ns
External SCLK Active Edge to SDOUT Delay t
32
318ns
SDIN Setup Time t
33
5ns
SDIN Hold Time t
34
5ns
External SCLK Period t
35
25 ns
External SCLK HIGH t
36
10 ns
External SCLK LOW t
37
10 ns
NOTES
1
In warp mode only, the maximum time between conversions is 1 ms; otherwise, there is no required maximum time.
2
In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.
3
In serial master read during convert mode. See Table I for serial master read after convert mode.
Specifications subject to change without notice.
Symbol Min Typ Max Unit
REV. PrA
PRELIMINARY TECHNICAL DATA
AD7667
–5–
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7667 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDE
Temperature
Model Range Package Description Package Option
AD7667AST –40°C to +85°C Quad Flatpack (LQFP) ST-48
AD7667ASTRL –40°C to +85°C Quad Flatpack (LQFP) ST-48
AD7667ACP –40°C to +85°C Chip Scale (LFCSP) CP-48
AD7667ACPRL –40°C to +85°C Chip Scale (LFCSP) CP-48
EVAL-AD7667CB
1
Evaluation Board
EVAL-CONTROL BRD2
2
Controller Board
NOTES
1
This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD2 for evaluation/demonstration purposes.
2
This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.
ABSOLUTE MAXIMUM RATINGS*
IN2, TEMP2,REF, REFBUFIN, INGND, REFGND to AGND
. . . . . . . . . . . . . . . . . . . . . . .AVDD + 0.3 V to AGND – 0.3 V
Ground Voltage Differences
AGND, DGND, OGND . . . . . . . . . . . . . . . . . . . . . ±0.3 V
Supply Voltages
AVDD, DVDD, OVDD . . . . . . . . . . . . . . . -0.3V to +7 V
AVDD to DVDD, AVDD to OVDD . . . . . . . . . . . . . ±7 V
DVDD to OVDD . . . . . . . . . . . . . . . . . . . . -0.3V to +7 V
Digital Inputs . . . . . . . . . . . . . . . . –0.3 V to DVDD + 3.0 V
Internal Power Dissipation
3
. . . . . . . . . . . . . . . . . . . 700 mW
Internal Power Dissipation
4
. . . . . . . . . . . . . . . . . . . . . 2.5 W
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range
(Soldering 10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
See Analog Input section.
3
Specification is for the device in free air:
48-Lead LQFP; θ
JA
= 91°C/W, θ
JC
= 30°C/W
4
Specification is for the device in free air:
48-Lead LFCSP; θ
JA
= 26°C/W
I
OH
500A
1.6mA I
OL
TO OUTPUT
PIN
1.4V
C
L
60pF*
*
IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND
SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD
C
L
OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.
Figure 1. Load Circuit for Digital Interface Timing,
SDOUT, SYNC, SCLK Outputs, C
L
= 10 pF
0.8V
2V
2V
0.8V
0.8V
2V
t
DELAY
t
DELAY
Figure 2. Voltage Reference Levels for Timing
WARNING!
ESD SENSITIVE DEVICE
REV. PrA
PRELIMINARY TECHNICAL DATA
–6–
AD7667
PIN FUNCTION DESCRIPTIONS
Pin No. Mnemonic Type Description
1 AGND P Analog Power Ground Pin
2 AVDD P Input Analog Power Pins. Nominally 5 V.
3, 40–42, NC No Connect
44
4 BYTESWAP DI Parallel Mode Selection (8/16 bit). When LOW, the LSB is output on D[7:0] and the
MSB is output on D[15:8]. When HIGH, the LSB is output on D[15:8] and the MSB
is output on D[7:0].
5 OB/2C D I Straight Binary/Binary Two’s Complement. When OB/2C is HIGH, the digital output is
straight binary; when LOW, the MSB is inverted resulting in a two’s complement output
from its internal shift register.
6 WARP DI Mode Selection. When HIGH and IMPULSE LOW, this input selects the fastest mode,
the maximum throughput is achievable, and a minimum conversion rate must be applied
in order to guarantee full specified accuracy. When LOW, full accuracy is maintained
independent of the minimum conversion rate.
7 IMPULSE DI Mode Selection. When HIGH and WARP LOW, this input selects a reduced power mode.
In this mode, the power dissipation is approximately proportional to the sampling rate.
8 SER/PAR DI Serial/Parallel Selection Input. When LOW, the parallel port is selected; when HIGH, the
serial interface mode is selected and some bits of the DATA bus are used as a serial port.
9,10 DATA[0:1] DI Bit 0 and Bit 1 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, these
outputs are in high impedance.
11,12 DATA[2:3]or DI/O When SER/PAR is LOW, these outputs are used as Bit 2 and Bit 3 of the Parallel Port
DIVSCLK[0:1] Data Output Bus. When SER/PAR is HIGH , EXT/INT is LOW, and RDC/SDIN is
LOW, which is serial master read after convert, these inputs, part of the serial port, are
used to slow down if desired the internal serial clock which clocks the data output. In
other serial moes, these pins are not used
13 DATA[4] DI/O When SER/PAR is LOW, this output is used as Bit 4 of the Parallel Port Data Output
Bus.
or EXT/INT When SER/PAR is HIGH, this input, part of the serial port, is used as a digital select input
for choosing the internal or an external data clock. With EXT/INT tied LOW, the internal
clock
is selected on SCLK output. With EXT/INT set to a logic HIGH, output data is syn
chronized
to an external clock signal connected to the SCLK input.
14 DATA[5] DI/O When SER/PAR is LOW, this output is used as Bit 5 of the Parallel Port Data Output
Bus.
or INVSYNC When SER/PAR is HIGH, this input, part of the serial port, is used to select the active
PIN CONFIGURATION
48-Lead LQFP
(ST-48)
36
35
34
33
32
31
30
29
28
27
26
25
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
48 47 46 45 44 39 38 3743 42 41 40
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
AGND
CNVST
PD
RESET
CS
RD
DGND
AGND
AVDD
NC
BYTESWAP
OB/2C
WARP
IMPULSE
NC = NO CONNECT
SER/PAR
D0
D1
D2/SCLK0
BUSY
D15
D14
D13
AD7667
D3/SCLK1
D12
D4/EXT/INT
D5/INVSYNC
D6/INVSCLK
D7/RDC/SDIN
OGND
OVDD
DVDD
DGND
D8/SDOUT
D9/SCLK
D10/SYNC
D11/RDERROR
PDBUF
PDREF
REFBUFIN
TEMPNCINNCNCNCINGND
REFGND
REF
REV. PrA
PRELIMINARY TECHNICAL DATA
AD7667
–7–
state of the SYNC signal. It is active in both master and slave mode. When LOW, SYNC
is active HIGH. When HIGH, SYNC is active LOW.
15 DATA[6] DI/O When SER/PAR is LOW, this output is used as Bit 6 of the Parallel Port Data Output
Bus.
or INVSCLK
When SER/
PAR
is HIGH, this input, part of the serial port, is used to invert the SCLK signal.
It is active in both master and slave mode.
16 DATA[7] DI/O When SER/PAR is LOW, this output is used as Bit 7 of the Parallel Port Data Output
Bus.
or RDC/SDIN When SER/PAR is HIGH, this input, part of the serial port, is used as either an external
data input or a read mode selection input depending on the state of EXT/INT.
When EXT/INT is HIGH, RDC/SDIN could be used as a data input to daisy chain the conver sion results from two or more ADCs onto a single SDOUT line. The digital data level on
SDIN is output on DATA with a delay of 16 SCLK periods after the initiation of the read
sequence.
When EXT/INT is LOW, RDC/SDIN is used to select the read mode. When RDC/SDIN
is HIGH, the data is output on SDOUT during conversion. When RDC/SDIN is LOW,
the data can be output on SDOUT only when the conversion is complete.
17 OGND P Input/Output Interface Digital Power Ground
18 OVDD P Input/Output Interface Digital Power. Nominally at the same supply than the supply of
the host interface (5 V or 3 V).
19 DVDD P Digital Power. Nominally at 5 V.
20 DGND P Digital Power Ground
21 DATA[8] DO When SER/PAR is LOW, this output is used as Bit 8 of the Parallel Port Data Output Bus.
or SDOUT When SER/PAR is HIGH, this output, part of the serial port, is used as a serial data out
put synchronized to SCLK. Conversion results are stored in an on-chip register. The
AD7667 provides the conversion result, MSB first, from its internal shift register. The
DATA format is determined by the logic level of OB/2C. In serial mode, when EXT/INT
is LOW, SDOUT is valid on both edges of SCLK.
In serial mode, when EXT/INT is HIGH:
If INVSCLK is LOW, SDOUT is updated on SCLK rising edge and valid on the next
falling edge.
If INVSCLK is HIGH, SDOUT is updated on SCLK falling edge and valid on the next rising
edge.
22 DATA[9] DI/O When SER/PAR is LOW, this output is used as the Bit 9 of the Parallel Port Data
or SCLK Output Bus.
When SER/PAR is HIGH, this pin, part of the serial port, is used as a serial data clock
input or output, dependent upon the logic state of the EXT/INT pin. The active edge
where the data SDOUT is updated depends upon the logic state of the INVSCLK pin.
23 DATA[10] DO When SER/PAR is LOW, this output is used as the Bit 10 of the Parallel Port Data Output
Bus.
or SYNC When SER/PAR is HIGH, this output, part of the serial port, is used as a digital output
frame synchronization for use with the internal data clock (EXT/INT = Logic LOW).
When a read sequence is initiated and INVSYNC is LOW, SYNC is driven HIGH and
remains HIGH while SDOUT output is valid. When a read sequence is initiated and
INVSYNC is HIGH, SYNC is driven LOW and remains LOW while SDOUT output is
valid.
24 DATA[11] DO When SER/PAR is LOW, this output is used as the Bit 11 of the Parallel Port Data Output
Bus.
or RDERROR When SER/PAR is HIGH and EXT/INT is HIGH, this output, part of the serial port,
is used as a incomplete read error flag. In slave mode, when a data read is started and
not complete when the following conversion is complete, the current data is lost and
RDERROR is pulsed high.
25–28 DATA[12:15] DO Bit 12 to Bit 15 of the Parallel Port Data output bus. These pins are always outputs regard
less of the state of SER/PAR.
29 BUS Y D O Busy Output. Transitions HIGH when a conversion is started, and remains HIGH until
the conversion is complete and the data is latched into the on-chip shift register. The fall
ing edge of BUSY could be used as a data ready clock signal.
30 DGND P Must Be Tied to Digital Ground
31 RD DI
Read Data. When CS and RD are both LOW, the interface parallel or serial output bus is
enabled.
32 CS DI Chip Select. When CS and RD are both LOW, the interface parallel or serial output bus is
enabled. CS is also used to gate the external clock.
Pin No. Mnemonic Type Description
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