Analog Devices AD7661 Datasheet
16-Bit 100 kSPS PulSAR
®
FEATURES
2.5 V internal reference: typical drift 3 ppm/°C
Guaranteed max drift 15 ppm/°C
Throughput: 100 kSPS
INL: ±2.5 LSB max (±0.0038% of full scale)
16-bit resolution with no missing codes
S/(N+D): 88 dB min @ 20 kHz
THD: –96 dB max @ 20 kHz
Analog input voltage range: 0 V to 2.5 V
Both AC and DC specifications
No pipeline delay
Parallel and serial 5 V/3 V interface
TM
®/QSPI
SPI
Single 5 V supply operation
Power dissipation
16 mW typ, 160 µW @ 1 kSPS without REF
40 mW typ with REF
48-lead LQFP and 48-lead LFCSP packages
Pin-to-pin compatible with PulSAR ADCs
APPLICATIONS
Data acquisition
Medical instruments
Digital signal processing
Spectrum analysis
Instrumentation
Battery-powered systems
Process control
GENERAL DESCRIPTION
The AD7661* is a 16-bit, 100 kSPS, charge redistribution SAR
analog-to-digital converter that operates from a single 5 V
power supply. The part contains a high speed 16-bit sampling
ADC, an internal conversion clock, internal reference, error
correction circuits, and both serial and parallel system interface ports. The AD7661 is hardware factory-calibrated and
comprehensively tested to ensure ac parameters such as signalto-noise ratio (SNR) and total harmonic distortion (THD), in
addition to the more traditional dc parameters of gain, offset,
and linearity.
The AD7661 is available in a 48-lead LQFP and a tiny 48-lead
LFCSP with operation specified from –40°C to +85°C.
*
Patent Pending.
/MICROWIRETM/DSP compatible
Unipolar ADC with Reference
AD7661
FUNCTIONAL BLOCK DIAGRAM
REFBUFIN
AGND
AVDD
INGND
PDREF
PDBUF
RESET
REF
IN
PD
Table 1. PulSAR Selection
Type/kSPS 100–250 500–570
PseudoDifferential
True Bipolar AD7663 AD7665 AD7671
True
Differential
18-Bit AD7678 AD7679 AD7674
Multichannel/
Simultaneous
PRODUCT HIGHLIGHTS
1. Fast Throughput.
The AD7661 is a 100 kSPS, charge redistribution, 16-bit
SAR ADC with internal error correction circuitry.
2. Superior INL.
The AD7661 has a maximum integral nonlinearity of
2.5 LSB with no missing 16-bit codes.
3. Internal Reference.
The AD7661 has an internal reference with a typical
temperature drift of 3 ppm/°C.
4. Single-Supply Operation.
The AD7661 operates from a single 5 V supply. Its power
dissipation decreases with throughput.
5. Serial or Parallel Interface.
Versatile parallel or 2-wire serial interface arrangement is
compatible with both 3 V and 5 V logic.
REF REFGND
AD7661
SWITCHED
CAP DAC
CLOCK
CONTROL LOGIC AND
CALIBRATION CIRCUITRY
CNVST
Figure 1. Functional Block Diagram
SERIAL
PORT
PARALLEL
INTERFACE
DGNDDVDD
OVDD
OGND
16
DATA[15:0]
BUSY
RD
CS
SER/PAR
OB/2C
BYTESWAP
800–
1000
AD7651
AD7660/AD7661
AD7650/AD7652
AD7664/AD7666
AD7653
AD7667
AD7675 AD7676 AD7677
AD7654
AD7655
03033-0-001
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved.
AD7661
TABLE OF CONTENTS
Specifications..................................................................................... 3
Timing Specifications....................................................................... 5
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Definitions of Specifications......................................................... 11
Typical Performance Characteristics ........................................... 12
Circuit Information........................................................................ 16
Converter Operation.................................................................. 16
Typical Connection Diagram ................................................... 18
Power Dissipation versus Throughput.................................... 20
Conversion Control....................................................................21
REVISION HISTORY
Revision 0: Initial Version.
Digital Interface.......................................................................... 22
Parallel Interface......................................................................... 22
Serial Interface............................................................................ 22
Master Serial Interface............................................................... 23
Slave Serial Interface .................................................................. 24
Microprocessor Interfacing....................................................... 26
Application Hints ........................................................................... 27
Bipolar and Wider Input Ranges.............................................. 27
Layout .......................................................................................... 27
Evaluating the AD7661’s Performance.................................... 27
Outline Dimensions....................................................................... 28
Ordering Guide .......................................................................... 28
Rev. 0 | Page 2 of 28
AD7661
SPECIFICATIONS
Table 2. –40°C to +85°C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted
Parameter Conditions Min Typ Max Unit
RESOLUTION 16 Bits
ANALOG INPUT
Voltage Range VIN – V
Operating Input Voltage VIN –0.1 +3 V
V
INGND
Analog Input CMRR fIN = 10 kHz 68 dB
Input Current 100 kSPS Throughput 1.1 µA
Input Impedance1
THROUGHPUT SPEED
Complete Cycle 10 µs
Throughput Rate 0 100 kSPS
DC ACCURACY
Integral Linearity Error –2.5 +2.5 LSB2
No Missing Codes 16 Bits
Differential Linearity Error –1.0 +1.5 LSB
Transition Noise 0.7 LSB
Unipolar Zero Error, T
MIN
3
to T
±5 LSB
MAX
Unipolar Zero Error Temperature Drift3 ±0.25 ppm/°C
Full-Scale Error, T
MIN
to T
3
REF = 2.5 V ±0.08 % of FSR
MAX
Full-Scale Error Temperature Drift ±0.4 ppm/°C
Power Supply Sensitivity AVDD = 5 V ± 5% ±2 LSB
AC ACCURACY
Signal-to-Noise fIN = 20 kHz 88 89.3 dB4
Spurious Free Dynamic Range fIN = 20 kHz 96 107 dB
Total Harmonic Distortion fIN = 20 kHz –107 –96 dB
Signal-to-(Noise + Distortion) fIN = 20 kHz 88 89.3 dB
–60 dB Input, fIN = 20 kHz 30 dB
–3 dB Input Bandwidth 820 kHz
SAMPLING DYNAMICS
Aperture Delay 2 ns
Aperture Jitter 5 ps rms
Transient Response Full-Scale Step 8.75 µs
REFERENCE
Internal Reference Voltage V
REF
Internal Reference Temperature Drift –40°C to +85°C ±3 ±15 ppm/°C
Output Voltage Hysteresis –40°C to +85°C 50 ppm
Long Term Drift 100 ppm/1000 Hours
Line Regulation AVDD = 5 V ± 5% ±15 ppm/V
Turn-On Settling Time C
REF
Temperature Pin
Voltage Output @ 25°C 300 mV
Temperature Sensitivity 1 mV/°C
Output Resistance 4.3 kΩ
External Reference Voltage Range 2.3 2.5 AVDD – 1.85 V
External Reference Current Drain 100 kSPS Throughput 35 µA
0 V
INGND
V
REF
–0.1 +0.5 V
@ 25°C 2.48 2.5 2.52 V
= 10 µF 5 ms
Rev. 0 | Page 3 of 28
AD7661
Parameter Conditions Min Typ Max Unit
DIGITAL INPUTS
Logic Levels
VIL –0.3 +0.8 V
VIH 2.0 DVDD + 0.3 V
IIL –1 +1 µA
IIH –1 +1 µA
DIGITAL OUTPUTS
Data Format5
Pipeline Delay6
VOL I
VOH I
POWER SUPPLIES
Specified Performance
AVDD 4.75 5 5.25 V
DVDD 4.75 5 5.25 V
OVDD 2.7 5.257 V
Operating Current 100 kSPS Throughput
AVDD8 With Reference and Buffer 6.2 mA
AVDD9 Reference and Buffer Alone 3 mA
DVDD10 1.75 mA
10
OVDD
21 µA
Power Dissipation without REF10 100 kSPS Throughput 16 25 mW
1 kSPS Throughput 160 µW
Power Dissipation with REF10 100 kSPS Throughput 40 45 mW
TEMPERATURE RANGE11
Specified Performance T
1
See Analog Input section.
2
LSB means least significant bit. With the 0 V to 2.5 V input range, 1 LSB is 38.15 µV.
3
See Definitions of Specifications section. These specifications do not include the error contribution from the external reference.
4
All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified.
5
Parallel or Serial 16-Bit.
6
Conversion results are available immediately after completed conversion.
7
The max should be the minimum of 5.25 V and DVDD + 0.3 V.
8
With REF, PDREF and PDBUF are LOW; without REF, PDREF and PDBUF are HIGH.
9
With PDREF, PDBUF LOW and PD HIGH.
10
Tested in parallel reading mode
11
Consult factory for extended temperature range.
= 1.6 mA 0.4 V
SINK
= –500 µA OVDD – 0.6 V
SOURCE
to T
MIN
–40 +85 °C
MAX
Rev. 0 | Page 4 of 28
AD7661
TIMING SPECIFICATIONS
Table 3. –40°C to +85°C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted
Parameter Symbol Min Typ Max Unit
Refer to Figure 33 and Figure 34
Convert Pulse Width t1 10 ns
Time between Conversions t2 10 µs
CNVST LOW to BUSY HIGH Delay
BUSY HIGH All Modes Except Master Serial Read after Convert t4 1.25 µs
Aperture Delay t5 2 ns
End of Conversion to BUSY LOW Delay t6 10 ns
Conversion Time t7 1.25 µs
Acquisition Time t8 8.75 µs
RESET Pulse Width t9 10 ns
Refer to Figure 35, Figure 36, and Figure 37 (Parallel Interface Modes)
CNVST LOW to DATA Valid Delay
DATA Valid to BUSY LOW Delay t11 12 ns
Bus Access Request to DATA Valid t12 45 ns
Bus Relinquish Time t13 5 15 ns
Refer to Figure 39 and Figure 40 (Master Serial Interface Modes)1
CS LOW to SYNC Valid Delay
CS LOW to Internal SCLK Valid Delay1
CS LOW to SDOUT Delay
CNVST LOW to SYNC Delay
SYNC Asserted to SCLK First Edge Delay t18 3 ns
Internal SCLK Period2 t
Internal SCLK HIGH2 t
Internal SCLK LOW2 t
SDOUT Valid Setup Time2 t
SDOUT Valid Hold Time2 t
SCLK Last Edge to SYNC Delay2 t
CS HIGH to SYNC HI-Z
CS HIGH to Internal SCLK HI-Z
CS HIGH to SDOUT HI-Z
BUSY HIGH in Master Serial Read after Convert2 t
CNVST LOW to SYNC Asserted Delay
SYNC Deasserted to BUSY LOW Delay t30 25 ns
Refer to Figure 41 and Figure 42 (Slave Serial Interface Modes)1
External SCLK Setup Time t31 5 ns
External SCLK Active Edge to SDOUT Delay t32 3 18 ns
SDIN Setup Time t33 5 ns
SDIN Hold Time t34 5 ns
External SCLK Period t35 25 ns
External SCLK HIGH t36 10 ns
External SCLK LOW t37 10 ns
1
In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.
2
In serial master read during convert mode. See Table 4 for serial master read after convert mode.
35 ns
t
3
1.25 µs
t
10
10 ns
t
14
10 ns
t
15
10 ns
t
16
525 ns
t
17
25 40 ns
19
12 ns
20
7 ns
21
4 ns
22
2 ns
23
3 ns
24
10 ns
t
25
10 ns
t
26
10 ns
t
27
See Table 4
28
1.25 µs
t
29
Rev. 0 | Page 5 of 28
AD7661
Table 4. Serial Clock Timings in Master Read after Convert
DIVSCLK[1] 0 0 1 1
DIVSCLK[0] Symbol 0 1 0 1 Unit
SYNC to SCLK First Edge Delay Minimum t
Internal SCLK Period Minimum t
Internal SCLK Period Maximum t
Internal SCLK HIGH Minimum t
Internal SCLK LOW Minimum t
SDOUT Valid Setup Time Minimum t
SDOUT Valid Hold Time Minimum t
SCLK Last Edge to SYNC Delay Minimum t
BUSY HIGH Width Maximum t
18
19
19
20
21
22
23
24
24
3 17 17 17 ns
25 50 100 200 ns
40 70 140 280 ns
12 22 50 100 ns
7 21 49 99 ns
4 18 18 18 ns
2 4 30 80 ns
3 55 130 290 ns
2 2.5 3.5 5.75 µs
Rev. 0 | Page 6 of 28
AD7661
ABSOLUTE MAXIMUM RATINGS
Table 5. AD7661 Stress Ratings1
Parameter Rating
IN2, TEMP2, REF, REFBUFIN,
INGND, REFGND to AGND
AVDD + 0.3 V to
AGND – 0.3 V
Ground Voltage Differences
AGND, DGND, OGND ±0.3 V
Supply Voltages
AVDD, DVDD, OVDD –0.3 V to +7 V
AVDD to DVDD, AVDD to OVDD ±7 V
DVDD to OVDD –0.3 V to +7 V
Digital Inputs –0.3 V to DVDD + 0.3 V
PDREF, PDBUF
Internal Power Dissipation4 700 mW
3
±20 mA
Internal Power Dissipation5 2.5 W
Junction Temperature 150°C
Storage Temperature Range –65°C to +150°C
Lead Temperature Range
300°C
(Soldering 10 sec)
1
Stresses above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional
operation of the device at these or any other conditions above those listed
in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device
reliability.
2
See Analog Input section.
3
See the Voltage Reference Input section.
4
Specification is for the device in free air:
48-Lead LQFP; θ
5
Specification is for the device in free air:
48-Lead LFCSP; θ
= 91°C/W, θJC = 30°C/W
JA
= 26°C/W.
JA
1.6mA
TO OUTPUT
PIN
C
L
60pF
*
500µA
*IN SERIAL INTERFACE MODES,THE SYNC, SCLK, AND
SDOUT TIMINGS ARE DEFINEDWITH A MAXIMUM LOAD
C
OF 10pF; OTHERWISE,THE LOAD IS 60pF MAXIMUM.
L
Figure 2. Load Circuit for Digital Interface Timing,
SDOUT, SYNC, SCLK Outputs C
0.8V
t
DELAY
2V
0.8V
Figure 3. Voltage Reference Levels for Timing
I
OL
1.4V
I
OH
03033-0-002
= 10 pF
L
2V
t
DELAY
2V
0.8V
03033-0-003
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
this product features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
Rev. 0 | Page 7 of 28
AD7661
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PDBUF
PDREF
REFBUFIN
TEMP
AVDDINAGND
AD7661
OVDD
OGND
AGNDNCINGND
DVDD
DGND
D8/SDOUT
48
47 46 45 44 39 38 3743 42 41 40
1
AGND
AVDD
NC
BYTESWAP
OB/2C
NC
NC
SER/PAR
D0
D1
D2/DIVSCLK0
D3/DIVSCLK1
NC = NO CONNECT
PIN 1
IDENTIFIER
2
3
4
5
6
7
8
9
10
11
12
13 14
D4/EXT/INT
TOP VIEW
(Not to Scale)
15 16 17 18 19 20 21 22 23 24
D6/INVSCLK
D5/INVSYNC
D7/RDC/SDIN
Figure 4. 48-Lead LQFP (ST-48) and 48-Lead LFCSP (CP-48)
Table 6. Pin Function Descriptions
Pin No. Mnemonic Type1Description
1, 36,
AGND P Analog Power Ground Pin.
41, 42
2, 44 AVDD P Input Analog Power Pin. Nominally 5 V.
3, 6,
NC No Connect.
7, 40
4 BYTESWAP DI
Parallel Mode Selection (8-/16-bit). When LOW, the LSB is output on D[7:0] and the MSB is output on
D[15:8]. When HIGH, the LSB is output on D[15:8] and the MSB is output on D[7:0].
5
OB/
2C
DI
Straight Binary/Binary Twos Complement. When OB/
when LOW, the MSB is inverted, resulting in a twos complement output from its internal shift
register.
8
SER/
PAR
DI
Serial/Parallel Selection Input. When LOW, the parallel port is selected; when HIGH, the serial
interface mode is selected and some bits of the DATA bus are used as a serial port.
9, 10 D[0:1] DO
Bit 0 and Bit 1 of the Parallel Port Data Output Bus. When SER/
impedance.
11, 12
D[2:3]or
DIVSCLK[0:1]
DI/O
When SER/
When SER/
PAR is LOW, these outputs are used as Bit 2 and Bit 3 of the parallel port data output bus.
PAR is HIGH, EXT/INT is LOW, and RDC/SDIN is LOW (serial master read after convert),
these inputs, part of the serial port, are used to slow down, if desired, the internal serial clock that
clocks the data output. In other serial modes, these pins are not used.
13
D4 or
EXT/
INT
DI/O
When SER/
When SER/
PAR is LOW, this output is used as Bit 4 of the parallel port data output bus.
PAR is HIGH, this input, part of the serial port, is used as a digital select input for choosing
the internal data clock or an external data clock. With EXT/
on the SCLK output. With EXT/
INT set to a logic HIGH, output data is synchronized to an external
clock signal connected to the SCLK input.
14
D5 or
INVSYNC
DI/O
When SER/
When SER/
PAR is LOW, this output is used as Bit 5 of the parallel port data output bus.
PAR is HIGH, this input, part of the serial port, is used to select the active state of the SYNC
signal. It is active in both master and slave modes. When LOW, SYNC is active HIGH. When HIGH,
SYNC is active LOW.
15
D6 or
INVSCLK
DI/O
When SER/
When SER/
PAR is LOW, this output is used as Bit 6 of the parallel port data output bus.
PAR is HIGH, this input, part of the serial port, is used to invert the SCLK signal. It is active
in both master and slave modes.
REFGND
REF
36
AGND
35
CNVST
34
PD
33
RESET
32
CS
31
RD
30
DGND
29
BUSY
28
D15
27
D14
26
D13
25
D12
D9/SCLK
D10/SYNC
D11/RDERROR
03033-0-004
2C is HIGH, the digital output is straight binary;
PAR is HIGH, these outputs are in high
INT tied LOW, the internal clock is selected
Rev. 0 | Page 8 of 28
AD7661
Pin No. Mnemonic Type1Description
16
17 OGND P Input/Output Interface Digital Power Ground.
18 OVDD P Input/Output Interface Digital Power. Nominally at the same supply as the host interface (5 V or 3 V).
19 DVDD P Digital Power. Nominally at 5 V.
20 DGND P Digital Power Ground.
21
22
23
24
25–28 D[12:15] DO
29 BUSY DO
30 DGND P Must Be Tied to Digital Ground.
31
32
33 RESET DI
34 PD DI
35
37 REF AI/O Reference Input Voltage. On-chip reference output voltage.
38 REFGND AI Reference Input Analog Ground.
39 INGND AI Analog Input Ground.
D7 or
RDC/SDIN
D8 or
SDOUT
D9 or
SCLK
D10 or
SYNC
D11 or
RDERROR
RD
CS
CNVST
DI/O
DO
DI/O
DO
DO
DI
DI
DI
When SER/
When SER/
read mode selection input depending on the state of EXT/
When EXT/
from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on DATA
with a delay of 16 SCLK periods after the initiation of the read sequence.
When EXT/
is output on SDOUT during conversion. When RDC/SDIN is LOW, the data can be output on SDOUT
only when the conversion is complete.
When SER/
When SER/
synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7661 provides the
conversion result, MSB first, from its internal shift register. The DATA format is determined by the
logic level of OB/
serial mode when EXT/
valid on the next falling edge; if INVSCLK is HIGH, SDOUT is updated on the SCLK falling edge and
valid on the next rising edge.
When SER/
When SER/
depending upon the logic state of the EXT/
updated depends upon the logic state of the INVSCLK pin.
When SER/
When SER/
synchronization for use with the internal data clock (EXT/
initiated and INVSYNC is LOW, SYNC is driven HIGH and remains HIGH while the SDOUT output is
valid. When a read sequence is initiated and INVSYNC is HIGH, SYNC is driven LOW and remains LOW
while the SDOUT output is valid.
When SER/
SER/
flag. In slave mode, when a data read is started and not complete when the following conversion is
complete, the current data is lost and RDERROR is pulsed HIGH.
Bit 12 to Bit 15 of the Parallel Port Data Output Bus. These pins are always outputs regardless of the
state of SER/
Busy Output. Transitions HIGH when a conversion is started and remains HIGH until the conversion is
complete and the data is latched into the on-chip shift register. The falling edge of BUSY could be
used as a data ready clock signal.
Read Data. When
Chip Select. When
is also used to gate the external clock.
Reset Input. When set to a logic HIGH, this pin resets the AD7661 and the current conversion, if any,
is aborted. If not used, this pin could be tied to DGND.
Power-Down Input. When set to a logic HIGH, power consumption is reduced and conversions are
inhibited after the current one is completed.
Start Conversion. If
on
most appropriate if low sampling jitter is desired. If
complete, the internal sample/hold is put into the hold state and a conversion is immediately
started.
PAR is LOW, this output is used as Bit 7 of the parallel port data output bus.
PAR is HIGH, this input, part of the serial port, is used as either an external data input or a
INT.
INT is HIGH, RDC/SDIN could be used as a data input to daisy-chain the conversion results
INT is LOW, RDC/SDIN is used to select the read mode. When RDC/SDIN is HIGH, the data
PAR is LOW, this output is used as Bit 8 of the parallel port data output bus.
PAR is HIGH, this output, part of the serial port, is used as a serial data output
2C. In serial mode when EXT/INT is LOW, SDOUT is valid on both edges of SCLK. In
INT is HIGH, if INVSCLK is LOW, SDOUT is updated on the SCLK rising edge and
PAR is LOW, this output is used as Bit 9 of the parallel port data or SCLK output bus.
PAR is HIGH, this pin, part of the serial port, is used as a serial data clock input or output,
INT pin. The active edge where the data SDOUT is
PAR is LOW, this output is used as Bit 10 of the parallel port data output bus.
PAR is HIGH, this output, part of the serial port, is used as a digital output frame
INT = logic LOW). When a read sequence is
PAR is LOW, this output is used as Bit 11 of the parallel port data output bus. When
PAR and EXT/INT are HIGH, this output, part of the serial port, is used as an incomplete read error
PAR.
CS and RD are both LOW, the interface parallel or serial output bus is enabled.
CS and RD are both LOW, the interface parallel or serial output bus is enabled. CS
CNVST is HIGH when the acquisition phase (t8) is complete, the next falling edge
CNVST puts the internal sample/hold into the hold state and initiates a conversion. The mode is
CNVST is LOW when the acquisition phase (t8) is
Rev. 0 | Page 9 of 28
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