Analog Devices AD7660 d Datasheet

16-Bit, 100 kSPS PulSAR

FEATURES Throughput: 100 kSPS INL: 3 LSB Max (0.0046% of Full-Scale) 16-Bit Resolution with No Missing Codes S/(N+D): 87 dB Min @ 10 kHz, 90 dB Typ @ 45 kHz THD: –96 dB Max @ 10 kHz Analog Input Voltage Range: 0 V to 2.5 V Both AC and DC Specifications No Pipeline Delay Parallel and Serial 5 V/3 V Interface

/QSPI™/MICROWIRE™/DSP Compatible

SPI Single 5 V Supply Operation 21 mW Typical Power Dissipation, 21 W @ 100 SPS Power-Down Mode: 7 W Max Package: 48-Lead Quad Flatpack (LQFP)

48-Lead Chip Scale Package (LFCSP) Pin-to-Pin Compatible with the AD7664

APPLICATIONS Data Acquisition Battery-Powered Systems PCMCIA Instrumentation Automatic Test Equipment Scanners Medical Instruments Process Control

GENERAL DESCRIPTION

The AD7660 is a 16-bit, 100 kSPS, charge redistribution SAR, analog-to-digital converter that operates from a single 5 V power supply. The part contains an internal conversion clock, error correction circuits, and both serial and parallel system interface ports.

The AD7660 is hardware factory-calibrated and is comprehensively tested to ensure ac parameters such as signal-to-noise ratio (SNR) and total harmonic distortion (THD), in addition to the more traditional dc parameters of gain, offset, and linearity.

It is fabricated using Analog Devices’ high performance,

0.6 micron CMOS process with correspondingly low cost and is available in a 48-lead LQFP and a tiny 48-lead LFCSP with operation specified from –40∞C to +85∞C.

Unipolar CMOS ADC

AD7660

FUNCTIONAL BLOCK DIAGRAM

SERIAL

PORT

PARALLEL

INTERFACE

DGNDDVDD

AVDD AGND REF REFGND

AD7660

INGND

RESET

SWITCHED

CAP DAC

CLOCK

CONTROL LOGIC AND

CALIBRATION CIRCUITRY

CNVST

Table I. PulSAR Selection

Type/kSPS 100–250 500–570 800–1000

Pseudo AD7651 AD7650/AD7652 AD7653 Differential AD7660/AD7661 AD7664/AD7666 AD7667

True Bipolar AD7663 AD7665 AD7671

True AD7675 AD7676 AD7677 Differential

18-Bit AD7678 AD7679 AD7674

Simultaneous/ AD7654 Multichannel AD7655

PRODUCT HIGHLIGHTS

1. Fast Throughput The AD7660 is a 100 kSPS, charge redistribution, 16-bit SAR ADC with internal error correction circuitry.

2. Superior INL The AD7660 has a maximum integral nonlinearity of 3 LSBs with no missing 16-bit code.

3. Single-Supply Operation The AD7660 operates from a single 5 V supply and only dissipates 21 mW typical. Its power dissipation decreases with the throughput to, for instance, only 21 mW at a 100 SPS throughput. It consumes 7 mW maximum when in power-down.

4. Serial or Parallel Interface Versatile parallel or 2-wire serial interface arrangement compatible with both 3 V or 5 V logic.

OVDD

OGND

D[15:0]

BUSY

SER/PAR

OB/2C

*Patent pending

REV. D

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD7660–SPECIFICATIONS

(–40C to +85C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)

Parameter Conditions Min Typ Max Unit

RESOLUTION 16 Bits

ANALOG INPUT

Voltage Range V Operating Input Voltage V

Analog Input CMRR f

– V

INGND

= 25 kHz 70 dB

REF

V –0.1 +3 V –0.1 +0.5 V

Input Current 100 kSPS Throughput 325 nA Input Impedance See Analog Input Section

THROUGHPUT SPEED

Complete Cycle 10 ms Throughput Rate 0 100 kSPS

DC ACCURACY

Integral Linearity Error –3 +3 LSB

Differential Linearity Error –1 +1.75 LSB No Missing Codes 16 Bits Transition Noise Full-Scale Error Unipolar Zero Error

REF = 2.5 V ± 0.045 ± 0.08 % of FSR

0.75 LSB

± 1 ± 5 LSB

Power Supply Sensitivity AVDD = 5 V ± 5% ± 3 LSB

AC ACCURACY

Signal-to-Noise fIN = 10 kHz 87 90 dB

fIN = 45 kHz 90 dB

Spurious-Free Dynamic Range f

= 10 kHz 96 dB

fIN = 45 kHz 100 dB

Total Harmonic Distortion f

= 10 kHz –96 dB

= 45 kHz –100 dB

Signal-to-(Noise+Distortion) fIN = 10 kHz 87 dB

= 45 kHz 90 dB

–60 dB Input 30 dB

–3 dB Input Bandwidth 820 kHz

SAMPLING DYNAMICS

Aperture Delay 2ns Aperture Jitter 5 ps rms Transient Response Full-Scale Step 8 ms

REFERENCE

External Reference Voltage Range 2.3 2.5 AVDD – 1.85 V External Reference Current Drain 100 kSPS Throughput 22 mA

POWER SUPPLIES

Specified Performance

AVDD 4.75 5 5.25 V DVDD 4.75 5 5.25 V OVDD 2.7 5.25 V

Operating Current 100 kSPS Throughput

AVDD 3.2 mA

DVDD

OVDD

Power Dissipation

100 kSPS Throughput 21 25 mW 100 SPS Throughput 21 mW in Power-Down Mode

5, 6

1mA 10 mA

7 mW

DIGITAL INPUTS

Logic Levels

–0.3 +0.8 V +2.0 OVDD + 0.3 V –1 +1 mA –1 +1 mA

DIGITAL OUTPUTS

Data Format Parallel or Serial 16-Bit Pipeline Delay Conversion Results Available Immediately

after Completed Conversion

= 1.6 mA 0.4 V

SINK

= –500 mA OVDD – 0.6 V

SOURCE

–2–

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AD7660

Parameter Conditions Min Typ Max Unit

TEMPERATURE RANGE

Specified Performance T

NOTES

LSB means least significant bit. With the 0 V to 2.5 V input range, one LSB is 38.15 mV.

Typical rms noise at worst-case transitions and temperatures.

See Definition of Specifications section. These specifications do not include the error contribution from the external reference.

All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale unless otherwise specified.

Tested in Parallel Reading Mode.

With all digital inputs forced to DVDD or DGND respectively.

Specifications subject to change without notice.

MIN

to T

MAX

–40 +85 ∞C

TIMING SPECIFICATIONS

Parameter

(–40C to +85C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)

Symbol Min Typ Max Unit

REFER TO FIGURES 11 AND 12

Convert Pulsewidth t Time between Conversions t CNVST LOW to BUSY HIGH Delay t BUSY HIGH All Modes Except in t

Master Serial Read after Convert Mode Aperture Delay t End of Conversion to BUSY LOW Delay t Conversion Time t Acquisition Time t RESET Pulsewidth t

REFER TO FIGURES 13, 14, AND 15 (Parallel Interface Modes)

CNVST LOW to DATA Valid Delay t DATA Valid to BUSY LOW Delay t Bus Access Request to DATA Valid t Bus Relinquish Time t

REFER TO FIGURE 16 AND 17 (Master Serial Interface Modes)

CS LOW to SYNC Valid Delay t CS LOW to Internal SCLK Valid Delay t CS LOW to SDOUT Delay t CNVST LOW to SYNC Delay t

SYNC Asserted to SCLK First Edge Delay t Internal SCLK Period t Internal SCLK HIGH (INVSCLK Low) Internal SCLK LOW (INVSCLK Low)

SDOUT Valid Setup Time t SDOUT Valid Hold Time t SCLK Last Edge to SYNC Delay t

CS HIGH to SYNC HI-Z t CS HIGH to Internal SCLK HI-Z t CS HIGH to SDOUT HI-Z t

BUSY HIGH in Master Serial Read after Convert t CNVST LOW to SYNC Asserted Delay t SYNC Deasserted to BUSY LOW Delay t

REFER TO FIGURES 18 AND 20 (Slave Serial Interface Modes)

External SCLK Setup Time t External SCLK Active Edge to SDOUT Delay t SDIN Setup Time t SDIN Hold Time t External SCLK Period t External SCLK HIGH t External SCLK LOW t

NOTES

In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C

If the polarity of SCLK is inverted, the timing references of SCLK are also inverted.

Specifications subject to change without notice.

of 10 pF; otherwise, the load is 60 pF maximum.

5ns 10 ms

15 ns 2 ms

2ns

10 ns

2 ms

8 ms 10 ns

2 ms

45 ns

40 ns

515ns

10 ns 10 ns 10 ns

500 ns 4ns 40 75 ns 30 ns

9.5 ns

4.5 ns 3ns 3

10 ns 10 ns 10 ns

3.2 ms

1.5 ms

50 ns

5ns 316ns 5ns 5ns 25 ns 10 ns 10 ns

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AD7660

ABSOLUTE MAXIMUM RATINGS

Analog Inputs

, REF, INGND, REFGND . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . AVDD + 0.3 V to AGND – 0.3 V

Ground Voltage Differences

AGND, DGND, OGND . . . . . . . . . . . . . . . . . . . . . ± 0.3 V

Supply Voltages

AVDD, DVDD, OVDD . . . . . . . . . . . . . . . . –0.3 V to +7 V

AVDD to DVDD,

AVDD to OVDD . . . . . . . . . . . . . ± 7 V

DVDD to OVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 7 V

Digital Inputs

Except the Databus D(7:4) . . . –0.3 V to DVDD + 0.3 V

Databus Inputs D(7:4) . . . . . . –0.3 V to OVDD + 0.3 V

Internal Power Dissipation Internal Power Dissipation

. . . . . . . . . . . . . . . . . . . 700 mW

. . . . . . . . . . . . . . . . . . . . . 2.5 W

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150∞C

Storage Temperature Range . . . . . . . . . . . . –65∞C to +150∞C

Lead Temperature Range

(Soldering 10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 300∞C

NOTES

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

See Analog Input section.

Specification is for device in free air: 48-Lead LQFP: qJA = 91∞C/W, qJC = 30∞C/W.

Specification is for device in free air: 48-Lead LFCSP: qJA = 26∞C/W.

AGND AVDD

DGND OB/2C

SER/PAR

D2 D3

PIN CONFIGURATION

NCNCNCNCNCINNCNCNC

47 46

45 44 39 38 3743 42 41 40

PIN 1 IDENTIFIER

13 14

D4/EXT/INT

AD7660

TOP VIEW

(Not to Scale)

15 16 17 18

OVDD

OGND

D6/INVSCLK

D5/INVSYNC

D7/RDC/SDIN

NC = NO CONNECT

19 20

DVDD

21 22

DGND

D8/SDOUT

INGND

REFGND

23 24

D9/SCLK

D10/SYNC

REF

AGND

CNVST

RESET

DGND

BUSY

D15

D14

D13

D12

D11/RDERROR

1.6mA I

TO OUTPUT

60pF

500A

*IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD

OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.

1.4V

Figure 1. Load Circuit for Digital Interface Timing

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD7660AST –40∞C to +85∞C Quad Flatpack (LQFP) ST-48 AD7660ASTRL –40∞C to +85∞C Quad Flatpack (LQFP) ST-48 AD7660ACP –40∞C to +85∞CChip Scale (LFCSP) CP-48 AD7660ACPRL –40∞C to +85∞CChip Scale (LFCSP) CP-48 EVAL-AD7660CB EVAL-CONTROL BRD2

NOTES

This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD2 for evaluation/demonstration purposes.

This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.

0.8V

DELAY

0.8V 0.8V

DELAY

2V2V

Figure 2. Voltage Reference Levels for Timings

Evaluation Board Controller Board

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7660 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

–4–

WARNING!

ESD SENSITIVE DEVICE

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AD7660

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Type Description

1 AGND P Analog Power Ground Pin 2 AVDD P Input Analog Power Pins. Nominally 5 V. 3, 6, 7, NC No Connect

40–42, 44–48

4 DGND DI Must Be Tied to Digital Ground 5OB/2C DI Straight Binary/Binary Twos Complement. When OB/2C is HIGH, the digital output is

straight binary; when LOW, the MSB is inverted resulting in a twos complement output from its internal shift register.

8 SER/PAR DI Serial/Parallel Selection Input. When LOW, the Parallel Port is selected; when HIGH, the

Serial Interface Mode is selected and some bits of the DATA bus are used as a Serial Port.

9–12 D[0:3] DO Bit 0 to Bit 3 of the Parallel Port Data Output Bus. These pins are always outputs regardless

of the state of SER/PAR.

13 D4 DI/O When SER/PAR is LOW, this output is used as the Bit 4 of the Parallel Port Data Output Bus.

or EXT/INT When SER/PAR is HIGH, this input, part of the Serial Port, is used as a digital select input

for choosing the internal or an external data clock. With EXT/INT tied LOW, the internal clock is selected on the SCLK output. With EXT/INT set to a logic HIGH, output data is synchronized to an external clock signal connected to the SCLK input.

14 D5 DI/O When SER/PAR is LOW, this output is used as the Bit 5 of the Parallel Port Data Output Bus.

or INVSYNC When SER/PAR is HIGH, this input, part of the Serial Port, is used to select the active state

of the SYNC signal. When LOW, SYNC is active HIGH. When HIGH, SYNC is active LOW.

15 D6 DI/O When SER/PAR is LOW, this output is used as the Bit 6 of the Parallel Port Data Output Bus.

or INVSCLK When SER/PAR is HIGH, this input, part of the Serial Port, is used to invert the SCLK

signal. It is active in both Master and Slave Modes.

16 D7 DI/O When SER/PAR is LOW, this output is used as the Bit 7 of the Parallel Port Data Output Bus.

or RDC/SDIN When SER/PAR is HIGH, this input, part of the Serial Port, is used as either an external data

input or a Read Mode selection input depending on the state of EXT/INT. When EXT/INT is HIGH, RDC/SDIN could be used as a data input to daisy-chain the

conversion results from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on DATA with a delay of 16 SCLK periods after the initiation of the read sequence.

When EXT/INT is LOW, RDC/SDIN is used to select the Read Mode. When RDC/SDIN is HIGH, the data is output on SDOUT during conversion. When RDC/SDIN is LOW, the

data is output on SDOUT only when the conversion is complete. 17 OGND P Input/Output Interface Digital Power Ground 18 OVDD P Input/Output Interface Digital Power. Nominally at the same supply as the supply of the host

interface (5 V or 3 V). 19 DVDD P Digital Power. Nominally at 5 V. 20 DGND P Digital Power Ground 21 D8 DO When SER/PAR is LOW, this output is used as Bit 8 of the Parallel Port Data Output Bus.

or SDOUT When SER/PAR is HIGH, this output, part of the Serial Port, is used as a serial data output

synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7660

provides the conversion result, MSB first, from its internal shift register. The DATA format

is determined by the logic level of OB/2C. In Serial Mode, when EXT/INT is LOW, SDOUT

is valid on both edges of SCLK.

In Serial Mode, when EXT/INT is HIGH:

If INVSCLK is LOW, SDOUT is updated on the SCLK rising edge and valid on the next

falling edge.

If INVSCLK is HIGH, SDOUT is updated on the SCLK falling edge and valid on the next

rising edge.

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AD7660

PIN FUNCTION DESCRIPTIONS (continued)

Pin No. Mnemonic Type Description

22 D9 DI/O When SER/PAR is LOW, this output is used as Bit 9 of the Parallel Port Data Output Bus.

or SCLK When SER/PAR is HIGH, this pin, part of the Serial Port, is used as a serial data clock input

or output, dependent upon the logic state of the EXT/INT pin. The active edge where the data SDOUT is updated depends upon the logic state of the INVSCLK pin.

23 D10 DO When SER/PAR is LOW, this output is used as Bit 10 of the Parallel Port Data Output Bus.

or SYNC When SER/PAR is HIGH, this output, part of the Serial Port, is used as a digital output

frame synchronization for use with the internal data clock (EXT/INT = Logic LOW). When a read sequence is initiated and INVSYNC is LOW, SYNC is driven HIGH and remains HIGH while SDOUT output is valid. When a read sequence is initiated and INVSYNC is HIGH, SYNC is driven LOW and remains LOW while SDOUT output is valid.

24 D11 DO When SER/PAR is LOW, this output is used as the Bit 11 of the Parallel Port Data Output Bus.

or RDERROR When SER/PAR is HIGH and EXT/INT is HIGH, this output, part of the Serial Port, is

used as an incomplete read error flag. In Slave Mode, when a data read is started and not complete when the following conversion is complete, the current data is lost and RDERROR is pulsed HIGH.

25–28 D[12:15] DO Bit 12 to Bit 15 of the Parallel Port Data Output Bus. These pins are always outputs regard-

less of the state of SER/PAR.

29 BUSY DO Busy Output. Transitions HIGH when a conversion is started and remains HIGH until the

conversion is complete and the data is latched into the on-chip shift register. The falling edge of BUSY could be used as a data-ready clock signal.

30 DGND P Must Be Tied to Digital Ground 31 RD DI Read Data. When CS and RD are both LOW, the interface parallel or serial output bus is

enabled.

32 CS DI Chip Select. When CS and RD are both LOW, the interface parallel or serial output bus is

enabled. CS is also used to gate the external clock.

33 RESET DI Reset Input. When set to a logic HIGH, reset the AD7660. Current conversion, if any, is aborted. 34 PD DI Power-Down Input. When set to a logic HIGH, power consumption is reduced and conver-

sions are inhibited after the current one is completed.

35 CNVST DI Start Conversion. If CNVST is HIGH when the acquisition phase (t

falling edge on CNVST puts the internal sample-and-hold into the hold state and initiates a conversion. This mode is the most appropriate if low sampling jitter is desired. If CNVST is LOW when the acquisition phase (t

) is complete, the internal sample-and-hold is put into the

hold state and a conversion is immediately started. 36 AGND P Must Be Tied to Analog Ground 37 REF AI Reference Input Voltage 38 REFGND AI Reference Input Analog Ground 39 INGND AI Analog Input Ground 43 IN AI Primary Analog Input with a Range of 0 V to V

NOTES AI = Analog Input DI = Digital Input DI/O = Bidirectional Digital DO = Digital Output P = Power

REF

) is complete, the next

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+ 14 hidden pages

Analog Devices AD7660 d Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

TIMING SPECIFICATIONS

PIN CONFIGURATION

ORDERING GUIDE

PIN FUNCTION DESCRIPTIONS