ANALOG DEVICES AD7656, AD7657 Service Manual

250 kSPS, 6-Channel, Simultaneous

V

A

V1V2V3V4V5V

FEATURES

6 independent ADCs True bipolar analog inputs Pin-/software-selectable ranges: ±10 V, ±5 V Fast throughput rate: 250 kSPS iCMOS process technology Low power

140 mW at 250 kSPS with 5 V supplies

Wide input bandwidth

86.5 dB SNR at 50 kHz input frequency On-chip reference and reference buffers Parallel, serial, and daisy-chain interface modes High speed serial interface

SPI-/QSPI™-/MICROWIRE™-/DSP-compatible Standby mode: 100 μW maximum 64-lead LQFP

APPLICATIONS

Power line monitoring systems Instrumentation and control systems Multi-axis positioning systems

Sampling, Bipolar 16-/14-/12-Bit ADC

AD7656/AD7657/AD7658

FUNCTIONAL BLOCK DIAGRAM

DD

REF

BUF

T/H

BUF

T/H

BUF

T/H

6

V

SS

CONVST

CLK OSC

16-/14-/12-BI T SAR

CONVST B CONVST C

CONTROL

LOGIC

AD7656/AD7657/AD7658

AGND

Figure 1.

OUTPUT

DRIVERS

OUTPUT

DRIVERS

OUTPUT

DRIVERS

OUTPUT

DRIVERS

DGND

VCCDV

CC

CS SER/PAR V

DRIVE

STBY

DOUT A

SCLK

DOUT B

DOUT C

DATA/ CONTROL LINES

RD

WR

05020-001

GENERAL DESCRIPTION

The AD7656/AD7657/AD76581 contain six 16-/14-/12-bit, fast, low power, successive approximation ADCs all in the one package that is designed on the iCMOS™ process (industrial CMOS). iCMOS is a process combining high voltage silicon with submicron CMOS and complementary bipolar technologies. It enables the development of a wide range of high performance analog ICs, capable of 33 V operation in a footprint that no previous generation of high voltage parts could achieve. Unlike analog ICs using conventional CMOS processes, iCMOS components can accept bipolar input signals while providing increased performance, which dramatically reduces power consumption and package size.

The AD7656/AD7657/AD7658 feature throughput rates up to 250 kSPS. The parts contain low noise, wide bandwidth, track-and-hold amplifiers that can handle input frequencies up to 12 MHz.

1

Protected by U.S. Patent No. 6,731,232.

The conversion process and data acquisition are controlled using CONVST signals and an internal oscillator. Three CONVST pins allow independent, simultaneous sampling of the three ADC pairs. The AD7656/AD7657/AD7658 all have a high speed parallel and serial interface, allowing the devices to interface with microprocessors or DSPs. In serial interface mode, the parts have a daisy-chain feature that allows multiple ADCs to connect to a single serial interface. The AD7656/ AD7657/AD7658 can accommodate true bipolar input signals in the ±4 × V

range and ±2 × V

REF

range. The AD7656/

REF

AD7657/AD7658 also contain an on-chip 2.5 V reference.

PRODUCT HIGHLIGHTS

1. Six 16-/14-/12-bit, 250 kSPS ADCs on board.

2. Six true bipolar, high impedance analog inputs.

3. Parallel and high speed serial interfaces.

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD7656/AD7657/AD7658

REVISION HISTORY

8/10—Rev. B to Rev. C

Changes to t Changes to V

Added Power Supply Configuration Section .............................. 29

Added Figure 36 .............................................................................. 29

V

to AVCC

DD

1/10—Rev. A to Rev. B

Changes to Unit of DC Accuracy Parameter, Table 1 .................. 3

Changes to DC Accuracy Parameter, Table 2 ............................... 5

Changes to DC Accuracy Parameter, Table 3 ............................... 7

Changes to Terminology Section.................................................. 18

Updated Outline Dimensions ....................................................... 30

Changes to Ordering Guide .......................................................... 30

Unit in Table 4 ........................................................... 9

1

to AVCC Rating in Table 5 .................................. 10

DD

4/06—Rev. 0 to Rev. A

Added AD7657/AD7658 parts ......................................... Universal

Changes to Table 1 ............................................................................. 3

Changes to Table 5 .......................................................................... 10

3/06—Revision 0: Initial Version

Rev. C | Page 2 of 32

AD7656/AD7657/AD7658

SPECIFICATIONS

AD7656

V

= 2.5 V internal/external, AVCC = 4.75 V to 5.25 V, DVCC = 4.75 V to 5.25 V, V

REF

For ±4 × V f

SAMPLE

range: VDD = 10 V to 16.5 V, VSS = −10 V to −16.5 V; For ±2 × V

REF

= 250 kSPS, TA = T

MIN

to T

, unless otherwise noted.1

MAX

REF

Table 1.

Parameter B Version1 Y Version1 Unit Test Conditions/Comments

DYNAMIC PERFORMANCE fIN = 50 kHz sine wave

Signal-to-Noise + Distortion (SINAD)2 84 84 dB min

85.5 85.5 dB typ

Signal-to-Noise Ratio (SNR)2 85 85 dB min

86.5 86.5 dB typ

Total Harmonic Distortion (THD)2 −90 −90 dB max

−92 −92 dB typ VDD/VSS = ±5 V to ±10 V

−100 −100 dB typ VDD/VSS = ±12 V to ±16.5 V

Peak Harmonic or Spurious Noise (SFDR)2 −100 −100 dB typ

Intermodulation Distortion (IMD)2 fa = 50 kHz, fb = 49 kHz

Second-Order Terms −112 −112 dB typ

Third-Order Terms −107 −107 dB typ Aperture Delay 10 10 ns max Aperture Delay Matching 4 4 ns max Aperture Jitter 35 35 ps typ Channel-to-Channel Isolation2 −100 −100 dB typ fIN on unselected channels up to 100 kHz Full Power Bandwidth 12 12 MHz typ @ −3 dB 2 2 MHz typ @ −0.1 dB

DC ACCURACY

Resolution 16 16 Bits No Missing Codes 15 14 Bits min 16 16 Bits min @ 25°C Integral Nonlinearity2 ±3 ±4.5 LSB max ±1 ±1 LSB typ Positive Full-Scale Error2 ±0.75 ±0.75 % FSR max ±0.22% FSR typical Positive Full-Scale Error Matching2 ±0.35 ±0.35 % FSR max Bipolar Zero-Scale Error2 ±0.023 ±0.023 % FSR max ±0.004% FSR typical Bipolar Zero-Scale Error Matching2 ±0.038 ±0.038 % FSR max Negative Full-Scale Error2 ±0.75 ±0.75 % FSR max ±0.22% FSR typical Negative Full-Scale Error Matching2 ±0.35 ±0.35 % FSR max

ANALOG INPUT See Table 8 for min VDD/VSS for each range

Input Voltage Ranges ±4 × V ±2 × V

±4 × V

REF

±2 × V

REF

V RNG bit/RANGE pin = 0

REF

V RNG bit/RANGE pin = 1

REF

DC Leakage Current ±1 ±1 μA max Input Capacitance3 10 10 pF typ ±4 × V 14 14 pF typ ±2 × V

REFERENCE INPUT/OUTPUT

Reference Input Voltage Range 2.5/3 2.5/3 V min/max DC Leakage Current ±1 ±1 μA max Input Capacitance3 18.5 18.5 pF typ

Reference Output Voltage 2.49/2.51 2.49/2.51 V min/max Long-Term Stability 150 150 ppm typ 1,000 hours Reference Temperature Coefficient 25 25 ppm/°C max 6 6 ppm/°C typ

= 2.7 V to 5.25 V;

DRIVE

range: VDD = 5 V to 16.5 V, VSS = −5 V to −16.5 V;

range when in track

REF

range when in track

REF

= 1

DIS

EN/

Rev. C | Page 3 of 32

AD7656/AD7657/AD7658

Parameter B Version1 Y Version1 Unit Test Conditions/Comments

LOGIC INPUTS

Input High Voltage (V Input Low Voltage (V Input Current (IIN) ±1 ±1 μA max Typically 10 nA, VIN = 0 V or V Input Capacitance (CIN)3 10 10 pF max

LOGIC OUTPUTS

Output High Voltage (VOH) V Output Low Voltage (VOL) 0.2 0.2 V max I Floating-State Leakage Current ±1 ±1 μA max Floating-State Output Capacitance3 10 10 pF max Output Coding Twos complement

CONVERSION RATE

Conversion Time 3.1 3.1 μs max Track-and-Hold Acquisition Time Throughput Rate 250 250 kSPS Parallel interface mode only

POWER REQUIREMENTS

VDD 5/15 5/15 V nom min/max For 4 × V VSS −5/−15 −5/−15 V nom min/max For 4 × V AVCC 5 5 V nom DVCC 5 5 V nom V

3/5 3/5 V nom min/max

DRIVE

I

Digital I/P

TOTAL

Normal Mode (Static) 28 28 mA max AVCC = DVCC = V

(Includes IAVCC, IVDD, IVSS, IV

Normal Mode (Operational) 26 26 mA max f

(Includes IAVCC, IVDD, IVSS, IV ISS (Operational) 0.25 0.25 mA max VSS = −16.5 V, f I

(Operational) 0.25 0.25 mA max VDD = 16.5 V, f

DD

Partial Power-Down Mode 7 7 mA max

Full Power-Down Mode (STBY Pin)

Power Dissipation

Normal Mode (Static) 143 143 mW max Normal Mode (Operational) 140 140 mW max f Partial Power-Down Mode 35 35 mW max Full Power-Down Mode (STBY Pin)

1

Temperature ranges are as follows: B version is −40°C to +85°C and Y version is −40°C to +125°C.

2

See the Terminology section.

3

Sample tested during initial release to ensure compliance.

) 0.7 × V

INH

) 0.3 × V

INL

2, 3

550 550 ns max

, IDVCC) VSS = −16.5 V

DRIVE

, IDVCC) VDD = 16.5 V, VSS = −16.5 V

DRIVE

80 80 μA max

100 100 μW max

− 0.2 V

DRIVE

0.7 × V

DRIVE

0.3 × V

DRIVE

V min

DRIVE

V max

DRIVE

− 0.2 V min I

DRIVE

= 200 μA

SOURCE

= 200 μA

SINK

range, VDD = 10 V to 16.5 V

REF

range, VDD = −10 V to −16.5 V

REF

= 0 V or V

S

DRIVE

= 250 kSPS, AVCC = DVCC = V

SAMPLE

= DVCC = V

AV

CC

V

= −16.5 V

SS

DRIVE

= 5.25 V, VDD = 16.5 V,

= 250 kSPS

= 5.25 V, VDD = 16.5 V,

SCLK on or off, AVCC = DVCC = V

= 16.5 V, VSS = −16.5 V

V

DD

= DV

= V

AV

CC

= −16.5 V

V

SS

SAMPLE

CC

= 250 kSPS

= 5.25 V, VDD = 16.5 V,

DRIVE

= 5.25 V,

DRIVE

= 5.25 V,

Rev. C | Page 4 of 32

AD7656/AD7657/AD7658

AD7657

V

= 2.5 V internal/external, AVCC = 4.75 V to 5.25 V, DVCC = 4.75 V to 5.25 V, V

REF

For ±4 × V f

SAMPLE

range: VDD = 10 V to 16.5 V, VSS = −10 V to −16.5 V; For ±2 × V

REF

= 250 kSPS, TA = T

MIN

to T

, unless otherwise noted.1

MAX

REF

Table 2.

Parameter B Version1 Y Version1 Unit Test Conditions/Comments

DYNAMIC PERFORMANCE fIN = 50 kHz sine wave

Signal-to-Noise + Distortion (SINAD)2 81.5 81.5 dB min Signal-to-Noise Ratio (SNR)2 82.5 82.5 dB min

83.5 83.5 dB typ Total Harmonic Distortion (THD)2 −90 −89 dB max

−92 −92 dB typ Peak Harmonic or Spurious Noise (SFDR)2 −100 −100 dB typ Intermodulation Distortion (IMD)2 fa = 50 kHz, fb = 49 kHz

Second-Order Terms −109 −109 dB typ

Third-Order Terms −104 −104 dB typ Aperture Delay 10 10 ns max Aperture Delay Matching 4 4 ns max Aperture Jitter 35 35 ps typ Channel-to-Channel Isolation2 −100 −100 dB typ fIN on unselected channels up to 100 kHz Full Power Bandwidth 12 12 MHz typ @ −3 dB 2 2 MHz typ @ −0.1 dB

DC ACCURACY

Resolution 14 14 Bits No Missing Codes 14 14 Bits min Integral Nonlinearity2 ±1.5 ±1.5 LSB max ±1 ±1 LSB typ Positive Full-Scale Error2 ±0.75 ±0.75 % FSR max ±0.183% FSR typical Positive Full-Scale Error Matching2 ±0.3 ±0.3 % FSR max Bipolar Zero-Scale Error2 ±0.0305 ±0.0305 % FSR max ±0.015 % FSR typical Bipolar Zero-Scale Error Matching2 ±0.0427 ±0.0427 % FSR max Negative Full-Scale Error2 ±0.75 ±0.75 % FSR max ±0.183% FSR typical Negative Full-Scale Error Matching2 ±0.3 ±0.3 % FSR max

ANALOG INPUT See Tabl e 8 for min VDD/VSS for each range

Input Voltage Ranges ±4 × V ±2 × V

±4 × V

REF

±2 × V

REF

V RNG bit/RANGE pin = 0

REF

V RNG bit/RANGE pin = 1

REF

DC Leakage Current ±1 ±1 μA max Input Capacitance3 10 10 pF typ ±4 × V 14 14 pF typ ±2 × V

REFERENCE INPUT/OUTPUT

Reference Input Voltage Range 2.5/3 2.5/3 V min/max DC Leakage Current ±1 ±1 μA max Input Capacitance3 18.5 18.5 pF typ

Reference Output Voltage 2.49/2.51 2.49/2.51 V min/max Long-Term Stability 150 150 ppm typ 1,000 hours Reference Temperature Coefficient 25 25 ppm/°C max 6 6 ppm/°C typ

LOGIC INPUTS

Input High Voltage (V Input Low Voltage (V

) 0.7 × V

INH

) 0.3 × V

INL

0.7 × V

DRIVE

0.3 × V

DRIVE

V min

DRIVE

V max

DRIVE

Input Current (IIN) ±1 ±1 μA max Typically 10 nA, VIN = 0 V or V Input Capacitance (CIN)3 10 10 pF max

= 2.7 V to 5.25 V;

DRIVE

range: VDD = 5 V to 16.5 V, VSS = −5 V to −16.5 V;

range when in track

REF

range when in track

REF

= 1

DIS

EN/

DRIVE

Rev. C | Page 5 of 32

AD7656/AD7657/AD7658

Parameter B Version1 Y Version1 Unit Test Conditions/Comments

LOGIC OUTPUTS

Output High Voltage (VOH) V Output Low Voltage (VOL) 0.2 0.2 V max I Floating-State Leakage Current ±1 ±1 μA max Floating-State Output Capacitance3 10 10 pF max Output Coding Twos complement

CONVERSION RATE

Conversion Time 3.1 3.1 μs max Track-and-Hold Acquisition Time

2, 3

550 550 ns max

Throughput Rate 250 250 kSPS Parallel interface mode only

POWER REQUIREMENTS

VDD 5/15 5/15 V nom min/max For 4 × V VSS −5/−15 −5/−15 V nom min/max For 4 × V AVCC 5 5 V nom DVCC 5 5 V nom V

3/5 3/5 V nom min/max

DRIVE

I

Digital I/PS = 0 V or V

TOTAL

Normal Mode (Static) 28 28 mA max AVCC = DVCC = V

(Includes IAVCC, IVDD, IVSS, IV

, IDVCC) VSS = −16.5 V

DRIVE

Normal Mode (Operational) 26 26 mA max f

(Includes IAVCC, IVDD, IVSS, IV

, IDVCC) VDD = 16.5 V, VSS = −16.5 V

DRIVE

ISS (Operational) 0.25 0.25 mA max VSS = −16.5 V, f I

(Operational) 0.25 0.25 mA max VDD = 16.5 V, f

DD

Partial Power-Down Mode 7 7 mA max

Full Power-Down Mode (STBY Pin)

Power Dissipation

Normal Mode (Static) 143 143 mW max Normal Mode (Operational) 140 140 mW max f Partial Power-Down Mode 35 35 mW max Full Power-Down Mode (STBY Pin)

1

Temperature ranges are as follows: B version is −40°C to +85°C and Y version is −40°C to +125°C.

2

See the Terminology section.

3

Sample tested during initial release to ensure compliance.

− 0.2 V

DRIVE

− 0.2 V min I

DRIVE

80 80 μA max

100 100 μW max

= 200 μA

SOURCE

= 200 μA

SINK

range, VDD = 10 V to 16.5 V

REF

range, VDD = −10 V to −16.5 V

REF

DRIVE

= 5.25 V, VDD = 16.5 V,

DRIVE

= 250 kSPS, AVCC = DVCC = V

SAMPLE

= 250 kSPS

SAMPLE

= 250 kSPS

SAMPLE

= DVCC = V

AV

CC

= −16.5 V

V

SS

= 5.25 V, VDD = 16.5 V,

DRIVE

SCLK on or off, AVCC = DVCC = V

= 16.5 V, VSS = −16.5 V

V

DD

= DV

= V

AV

CC

V

= −16.5 V

SS

SAMPLE

CC

= 250 kSPS

= 5.25 V, VDD = 16.5 V,

DRIVE

= 5.25 V,

DRIVE

= 5.25 V,

Rev. C | Page 6 of 32

AD7656/AD7657/AD7658

AD7658

V

= 2.5 V internal/external, AVCC = 4.75 V to 5.25 V, DVCC = 4.75 V to 5.25 V, V

REF

For ±4 × V f

SAMPLE

range: VDD = 10 V to 16.5 V, VSS = −10 V to −16.5 V; For ±2 × V

REF

= 250 kSPS, TA = T

MIN

to T

, unless otherwise noted.1

MAX

REF

Table 3.

Parameter B Version1 Y Version1 Unit Test Conditions/Comments

DYNAMIC PERFORMANCE fIN = 50 kHz sine wave

Signal-to-Noise + Distortion (SINAD)2 73 73 dB min

73.5 73.5 dB typ Total Harmonic Distortion (THD)2 −88 −88 dB max

−92 −92 dB typ Peak Harmonic or Spurious Noise (SFDR)2 −97 −97 dB typ Intermodulation Distortion (IMD)2 fa = 50 kHz, fb = 49 kHz

Second-Order Terms −106 −106 dB typ

Third-Order Terms −101 −101 dB typ Aperture Delay 10 10 ns max Aperture Delay Matching 4 4 ns max Aperture Jitter 35 35 ps typ Channel-to-Channel Isolation2 −100 −100 dB typ fIN on unselected channels up to 100 kHz Full Power Bandwidth 12 12 MHz typ @ −3 dB 2 2 MHz typ @ −0.1 dB

DC ACCURACY

Resolution 12 12 Bits No Missing Codes 12 12 Bits min Differential Nonlinearity ±0.7 ±0.7 LSB max Integral Nonlinearity2 ±1 ±1 LSB max Positive Full-Scale Error2 ±0.75 ±0.75 % FSR max ±0.244% FSR typical Positive Full-Scale Error Matching2 ±0.366 ±0.366 % FSR max Bipolar Zero-Scale Error2 ±3 ±3 LSB max ±0.0488% FSR typical Bipolar Zero-Scale Error Matching2 ±3 ±3 LSB max Negative Full-Scale Error2 ±0.75 ±0.75 % FSR max ±0.244% FSR typical Negative Full-Scale Error Matching2 ±0.366 ±0.366 % FSR max

ANALOG INPUT See Table 8 for min VDD/VSS for each range

Input Voltage Ranges ±4 × V ±2 × V

±4 × V

REF

±2 × V

REF

V RNG bit/RANGE pin = 0

REF

V RNG bit/RANGE pin = 1

REF

DC Leakage Current ±1 ±1 μA max Input Capacitance3 10 10 pF typ ±4 × V 14 14 pF typ ±2 × V

REFERENCE INPUT/OUTPUT

Reference Input Voltage Range 2.5/3 2.5/3 V min/max DC Leakage Current ±1 ±1 μA max Input Capacitance3 18.5 18.5 pF typ

Reference Output Voltage 2.49/2.51 2.49/2.51 V min/max Long-Term Stability 150 150 ppm typ 1,000 hours Reference Temperature Coefficient 25 25 ppm/°C max 6 6 ppm/°C typ

LOGIC INPUTS

Input High Voltage (V Input Low Voltage (V

) 0.7 × V

INH

) 0.3 × V

INL

0.7 × V

DRIVE

0.3 × V

DRIVE

V min

DRIVE

V max

DRIVE

Input Current (IIN) ±1 ±1 μA max Typically 10 nA, VIN = 0 V or V Input Capacitance (CIN)3 10 10 pF max

= 2.7 V to 5.25 V;

DRIVE

range: VDD = 5 V to 16.5 V, VSS = −5 V to −16.5 V;

range when in track

REF

range when in track

REF

= 1

DIS

EN/

DRIVE

Rev. C | Page 7 of 32

AD7656/AD7657/AD7658

Parameter B Version1 Y Version1 Unit Test Conditions/Comments

LOGIC OUTPUTS

Output High Voltage (VOH) V Output Low Voltage (VOL) 0.2 0.2 V max I Floating-State Leakage Current ±1 ±1 μA max Floating-State Output Capacitance3 10 10 pF max Output Coding Twos complement

CONVERSION RATE

Conversion Time 3.1 3.1 μs max Track-and-Hold Acquisition Time

2, 3

550 550 ns max

Throughput Rate 250 250 kSPS Parallel interface mode only

POWER REQUIREMENTS

VDD 5/15 5/15 V nom min/max For 4 × V VSS −5/−15 −5/−15 V nom min/max For 4 × V AVCC 5 5 V nom DVCC 5 5 V nom V

3/5 3/5 V nom min/max

DRIVE

I

Digital I/PS = 0 V or V

TOTAL

Normal Mode (Static) 28 28 mA max AVCC = DVCC = V

(Includes IAVCC, IVDD, IVSS, IV

, IDVCC) VSS = −16.5 V

DRIVE

Normal Mode (Operational) 26 26 mA max f

(Includes IAVCC, IVDD, IVSS, IV

, IDVCC) VDD = 16.5 V, VSS = −16.5 V

DRIVE

ISS (Operational) 0.25 0.25 mA max VSS = −16.5 V, f I

(Operational) 0.25 0.25 mA max VDD = 16.5 V, f

DD

Partial Power-Down Mode 7 7 mA max

Full Power-Down Mode (STBY Pin)

Power Dissipation

Normal Mode (Static) 143 143 mW max Normal Mode (Operational) 140 140 mW max f Partial Power-Down Mode 35 35 mW max Full Power-Down Mode (STBY Pin)

1

Temperature ranges are as follows: B version is −40°C to +85°C and Y version is −40°C to +125°C

2

See the Terminology section.

3

Sample tested during initial release to ensure compliance.

− 0.2 V

DRIVE

− 0.2 V min I

DRIVE

80 80 μA max

100 100 μW max

= 200 μA

SOURCE

= 200 μA

SINK

range, VDD = 10 V to 16.5 V

REF

range, VDD = −10 V to −16.5 V

REF

DRIVE

= 5.25 V, VDD = 16.5 V,

DRIVE

= 250 kSPS, AVCC = DVCC = V

SAMPLE

= 250 kSPS

SAMPLE

= 250 kSPS

SAMPLE

= DVCC = V

AV

CC

= −16.5 V

V

SS

= 5.25 V, VDD = 16.5 V,

DRIVE

SCLK on or off, AVCC = DVCC = V

= 16.5 V, VSS = −16.5 V

V

DD

= DVCC = V

AV

CC

V

= −16.5 V

SS

SAMPLE

= 250 kSPS

= 5.25 V, VDD = 16.5 V,

DRIVE

= 5.25 V,

DRIVE

= 5.25 V,

Rev. C | Page 8 of 32

AD7656/AD7657/AD7658

TIMING SPECIFICATIONS

AVCC/DVCC = 4.75 V to 5.25 V, VDD = 5 V to 16.5 V, VSS = −5 V to −16.5 V, V T

= T

MIN

to T

A

, unless otherwise noted.1

MAX

Table 4.

Parameter

< 4.75 V V

DRIVE

Limit at T

DRIVE

MIN, TMAX

= 4.75 V to 5.25 V

Unit Description V

PARALLEL MODE

t

3 3 μs typ Conversion time, internal clock

CONVER T

t

150 150 ns min

QUIET

t

550 550 ns min Acquisition time

ACQ

t10 25 25 ns min Minimum CONVST low pulse t1 60 60 ns max CONVST high to BUSY high t

2 2 ms max

WAKE -UP

25 25 μs max Partial power-down mode

PARALLEL WRITE OPERATION

t11 15 15 ns min t12 0 0 ns min t13 5 5 ns min t14 5 5 ns min t15 5 5 ns min

PARALLEL READ OPERATION

t

2

0 0 ns min t3 0 0 ns min t4 0 0 ns min t5 45 36 ns min t6 45 36 ns max t7 10 10 ns min t8 12 12 ns max t9 6 6 ns min Minimum time between reads

SERIAL INTERFACE

f

18 18 MHz max Frequency of serial read clock

SCLK

t16 12 12 ns max

2

t

22 22 ns max

17

t18 0.4 t t19 0.4 t

0.4 t

SCLK

0.4 t

SCLK

ns min SCLK low pulse width

SCLK

ns min SCLK high pulse width

SCLK

t20 10 10 ns min SCLK to data valid hold time after SCLK falling edge t21 18 18 ns max

1

Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.

2

A buffer is used on the data output pins for this measurement.

= 2.7 V to 5.25 V, V

DRIVE

= 2.5 V internal/external,

REF

Minimum quiet time required between bus relinquish and start of next conversion

rising edge to CONVST rising edge

STBY

pulse width

WR

to WR setup time

CS

to WR hold time

CS Data setup time before WR Data hold after WR

BUSY to RD

to RD setup time

CS

to RD hold time

CS

pulse width

RD

delay

Data access time after RD Data hold time after RD Bus relinquish time after RD

Delay from CS

until SDATA three-state disabled

rising edge

falling edge

rising edge

Data access time after SCLK rising edge/CS

rising edge to SDATA high impedance

CS

falling edge

200µA I

TO OUT P U T

C

L

25pF

200µA I

Figure 2. Load Circuit for Digital Output Timing Specification

Rev. C | Page 9 of 32

OL

1.6V

OH

05020-002

AD7656/AD7657/AD7658

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 5.

Parameter Rating

VDD to AGND, DGND −0.3 V to +16.5 V VSS to AGND, DGND +0.3 V to −16.5 V VDD to AVCC AVCC − 0.3 V to 16.5 V AVCC to AGND, DGND −0.3 V to +7 V DVCC to AVCC −0.3 V to AV

+ 0.3 V

CC

DVCC to DGND, AGND −0.3 V to +7 V AGND to DGND −0.3 V to +0.3 V V

to DGND −0.3 V to DVCC + 0.3 V

DRIVE

Analog Input Voltage to AGND1 V Digital Input Voltage to DGND −0.3 V to V Digital Output Voltage to GND −0.3 V to V

− 0.3 V to VDD + 0.3 V

SS

+ 0.3 V

DRIVE

+ 0.3 V

DRIVE

REFIN to AGND −0.3 V to AVCC + 0.3 V Input Current to Any Pin Except

Supplies

2

±10 mA

Operating Temperature Range

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. These specifications apply to a four-layer board.

Table 6. Thermal Resistance

Package Type θJA θ

64-Lead LQFP 45 11 °C/W

B Version −40°C to +85°C Y Version −40°C to +125°C

ESD CAUTION

Storage Temperature Range −65°C to +150°C Junction Temperature 150°C Pb/SN Temperature, Soldering

Reflow (10 sec to 30 sec) 240(+0)°C

Pb-Free Temperature, Soldering Reflow 260(+0)°C

1

If the analog inputs are being driven from alternative VDD and VSS supply

circuitry, a 240 Ω series resistor should be placed on the analog inputs.

2

Transient currents of up to 100 mA do not cause SCR latch-up.

Unit

JC

Rev. C | Page 10 of 32

ANALOG DEVICES AD7656, AD7657 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

AD7656

AD7657

AD7658

TIMING SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION