Analog Devices AD7655 a Datasheet

Low Cost, 4-Channel, 16-Bit

FEATURES

4-channel, 16-bit resolution ADC 2 track-and-hold amplifiers Throughput:

1 MSPS (Normal mode)

888 kSPS (Impulse mode) Analog input voltage range: 0 V to 5 V No pipeline delay Parallel and serial 5 V/3 V interface SPI®/QSPI™/MICROWIRE™/DSP-compatible Single 5 V supply operation Power dissipation:

120 mW typical

2.6 mW @ 10 kSPS

Package: 48-lead quad flatpack (LQFP)

or 48-lead frame chip scale package (LFCSP) Pin-to-pin compatible with the AD7654 Low cost

APPLICATIONS

AC motor control 3-phase power control 4-channel data acquisition Uninterrupted power supplies Communications

GENERAL DESCRIPTION

The AD76551 is a low cost, simultaneous sampling, dualchannel, 16-bit, charge redistribution SAR, analog-to-digital converter that operates from a single 5 V power supply. It contains two low noise, wide bandwidth, track-and-hold amplifiers that allow simultaneous sampling, a high speed 16-bit sampling ADC, an internal conversion clock, error correction circuits, and both serial and parallel system interface ports. Each track-and-hold has a multiplexer in front to provide a 4-channel input ADC. The A0 multiplexer control input allows the choice of simultaneously sampling input pairs INA1/INB1 (A0 = High) or INA2/INB2 (A0 = Low). The part features a very high sampling rate mode (Normal) and, for low power applications, a reduced power mode (Impulse) where the power is scaled with the throughput. Operation is specified from −40°C to +85°C.

1 MSPS PulSAR

®

ADC

AD7655

FUNCTIONAL BLOCK DIAGRAM

AVDD AGND REFxREFGND

TRACK/HOLD

INA1 INAN INA2

A0

INB1 INBN INB2

PD

RESET

×2

MUX

CONTROL LOGIC AND

CALIBRATION CIRCUITRY

AD7655

IMPULSE

SWITCHED

CAP DAC

CLOCK

CNVST

Figure 1.

Table 1. PulSAR® Selection

Type / kSPS 100 - 250 500 - 570

Pseudo Differential

AD7660/61

AD7650/52

AD7664/66 True Bipolar AD7663 AD7665 AD7671 True

Differential

AD7675 AD7676 AD7677 AD7621

18 Bit AD7678 AD7679 AD7674 AD7641 Multichannel/

Simultaneous

AD7654 AD7655

PRODUCT HIGHLIGHTS

1. Multichannel ADC.

The AD7655 features 4-channel inputs with two sampleand-hold circuits that allow simultaneous sampling.

2. Fast throughput.

The AD7655 is a 1 MSPS, charge redistribution, 16-bit SAR ADC with internal error correction circuitry.

3. Single-supply operation.

The AD7655 operates from a single 5 V supply. In Impulse mode, its power dissipation decreases with throughput.

4. Serial or parallel interface.

Versatile parallel or 2-wire serial interface arrangement is compatible with both 3 V and 5 V logic.

1

Patent pending.

DGNDDVDD

SERIAL

PORT

PARALLEL

INTERFACE

16

800 1000

AD7653 AD7667

OVDD OGND D[15:0] SER/PAR EOC BUSY CS RD A/B BYTESWAP

>1000

03536-001

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

www.analog.com

AD7655

SPECIFICATIONS

−40°C to +85°C, V

Table 2.

Parameter Conditions Min Typ Max Unit

RESOLUTION 16 Bits ANALOG INPUT

Voltage Range V Common-Mode Input Voltage V Analog Input CMRR fIN = 100 kHz 55 dB Input Current 500 kSPS throughput 45 µA Input Impedance1

THROUGHPUT SPEED

Complete Cycle (2 Channels) In Normal mode 2 µs Throughput Rate In Normal mode 0 1 MSPS Complete Cycle (2 Channels) In Impulse mode 2.25 µs Throughput Rate In Impulse mode 0 888 kSPS

DC ACCURACY

Integral Linearity Error −6 +6 LSB2 No Missing Codes 15 Bits Transition Noise 0.8 LSB Full-Scale Error3 T Full-Scale Error Drift3 ±2 ppm/°C Unipolar Zero Error3 T Unipolar Zero Error Drift3 ±0.8 ppm/°C Power Supply Sensitivity AVDD = 5 V ±5% ±0.8 LSB

AC ACCURACY

Signal-to-Noise fIN = 100 kHz 86 dB4 Spurious-Free Dynamic Range fIN = 100 kHz 98 dB Total Harmonic Distortion fIN = 100 kHz −96 dB Signal-to-(Noise + Distortion) fIN = 100 kHz 86 dB f Channel-to-Channel Isolation fIN = 100 kHz −92 dB

−3 dB Input Bandwidth 10 MHz

SAMPLING DYNAMICS

Aperture Delay5 2 ns Aperture Delay Matching5 30 ps Aperture Jitter5 5 ps rms Transient Response Full-scale step 250 ns

REFERENCE

External Reference Voltage Range 2.3 2.5 AVDD/2 V External Reference Current Drain 500 kSPS throughput 180 µA

DIGITAL INPUTS

Logic Levels

VIL −0.3 +0.8 V VIH +2.0 OVDD + 0.3 V IIL −1 +1 µA IIH −1 +1 µA

= 2.5 V, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.

REF

– V

INx

INxN

MIN

IN

0 2 V

INxN

−0.1 +0.5 V

to T

±0.25 ±0.5 % of FSR

MAX

to T

±0.25 % of FSR

MAX

= 100 kHz, −60 dB Input 30 dB

V

REF

Rev. A | Page 3 of 28

AD7655

Parameter Conditions Min Typ Max Unit

DIGITAL OUTPUTS

Data Format6

Pipeline Delay7

VOL I VOH I

POWER SUPPLIES

Specified Performance

AVDD 4.75 5 5.25 V

DVDD

OVDD 2.7 5.258 V

Operating Current9 1 MSPS throughput

AVDD 15.5 mA DVDD 8.5 mA

OVDD 100 µA Power Dissipation 1 MSPS throughput9 120 135 mW 20 kSPS throughput10 2.6 mW 888 kSPS throughput10 114 125 mW

TEMPERATURE RANGE11

Specified Performance T

1

See Analog Inputs section.

2

LSB means least significant bit. Within the 0 V to 5 V input range, one LSB is 76.294 V.

3

See Definition of Specifications section. These specifications do not include the error contribution from the external reference.

4

All specifications in dB are referred to as full-scale input FS; tested with an input signal at 0.5 dB below full scale unless otherwise specified.

5

Sample tested during initial release.

6

Parallel or serial 16-bit.

7

Conversion results are available immediately after completed conversion.

8

The maximum should be the minimum of 5.25 V and DVDD + 0.3 V.

9

In Normal mode; tested in parallel reading mode.

10

In Impulse mode; tested in parallel reading mode.

11

Consult sales for extended temperature range.

= 1.6 mA 0.4 V

SINK

= −500 µA OVDD − 0.2 V

SOURCE

4.75 5 5.25 V

to T

MIN

−40 +85 °C

MAX

Rev. A | Page 4 of 28

AD7655

TIMING SPECIFICATIONS

−40°C to +85°C, V

Table 3.

Parameter Symbol Min Typ Max Unit

Refer to Figure 21 and Figure 22

Convert Pulse Width t1 5 ns Time between Conversions

(Normal Mode/Impulse Mode) t2 2/2.25 µs

CNVST

Low to BUSY High Delay

BUSY High All Modes Except in Master Serial Read after Convert Mode

(Normal Mode/Impulse Mode) t4 1.75/2 µs Aperture Delay t5 2 ns End of Conversions to BUSY Low Delay t6 10 ns Conversion Time

(Normal Mode/Impulse Mode) t7 1.75/2 µs Acquisition Time t8 250 ns RESET Pulse Width t9 10 ns CNVST Low to High Delay

EOC High for Channel A Conversion

(Normal Mode/Impulse Mode) t EOC Low after Channel A Conversion EOC High for Channel B Conversion Channel Selection Setup Time t Channel Selection Hold Time t

Refer to Figure 23 to Figure 27 (Parallel Interface Modes)

CNVST

Low to DATA Valid Delay DATA Valid to BUSY Low Delay t Bus Access Request to DATA Valid t18 40 ns Bus Relinquish Time t A/B Low to Data Valid Delay

Refer to and (Master Serial Interface Modes)

CS Low to SYNC Valid Delay CS Low to Internal SCLK Valid Delay1 CS Low to SDOUT Delay CNVST

Low to SYNC Delay (Read during Convert)

(Normal Mode/Impulse Mode) t SYNC Asserted to SCLK First Edge Delay t25 3 ns Internal SCK Period2 t Internal SCLK High2 t Internal SCLK Low2 t SDOUT Valid Setup Time2 t SDOUT Valid Hold Time2 t SCLK Last Edge to SYNC Delay2 t CS

High to SYNC HI-Z CS

High to Internal SCLK HI-Z CS

High to SDOUT HI-Z BUSY High in Master Serial Read after Convert2 t CNVST

Low to SYNC Asserted Delay

(Normal Mode/Impulse Mode) t SYNC Deasserted to BUSY Low Delay t

= 2.5 V, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.

REF

32 ns

t

3

t

30 ns

10

1/1.25 µs

11

t

45 ns

12

t

0.75 µs

13

250 ns

14

30 ns

15

1.75/2 µs

t

16

14 ns

17

5 15 ns

19

t

40 ns

20

t

10 ns

21

t

10 ns

22

t

10 ns

23

250/500 ns

24

23 40 ns

26

12 ns

27

7 ns

28

4 ns

29

2 ns

30

1 ns

31

10 ns

t

32

t

10 ns

33

10 ns

t

34

See Table 4

35

0.75/1 µs

36

25 ns

37

Rev. A | Page 5 of 28

AD7655

Parameter Symbol Min Typ Max Unit

Refer to Figure 31 and Figure 32 (Slave Serial Interface Modes)

External SCLK Setup Time t38 5 ns External SCLK Active Edge to SDOUT Delay t39 3 18 ns SDIN Setup Time t40 5 ns SDIN Hold Time t41 5 ns External SCLK Period t42 25 ns External SCLK High t43 10 ns External SCLK Low t44 10 ns

1

In serial interface modes, the SYNC, SCLK, and ADOUT timings are defined with a maximum load CL of 10 pF; otherwise CL is 60 pF maximum.

2

In serial master read during convert mode. See for serial master read after convert mode. Table 4

Table 4. Serial Clock Timings in Master Read after Convert

DIVSCLK[1]

DIVSCLK[0] Symbol 0 1 0 1 Unit

SYNC to SCLK First Edge Delay Minimum

Internal SCLK Period Minimum t26 25 50 100 200 ns Internal SCLK Period Typical t26 40 70 140 280 ns Internal SCLK High Minimum t27 12 22 50 100 ns Internal SCLK Low Minimum t28 7 21 49 99 ns SDOUT Valid Setup Time Minimum t29 4 18 18 18 ns SDOUT Valid Hold Time Minimum t30 2 4 30 80 ns SCLK Last Edge to SYNC Delay Minimum t31 1 3 30 80 ns Busy High Width Maximum (Normal) t35 3.25 4.25 6.25 10.75 µs Busy High Width Maximum (Impulse) t35 3.5 4.5 6.5 11 µs

0 0 1 1

3 17 17 17 ns

t

25

Rev. A | Page 6 of 28

AD7655

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Values

Analog Input INAx1, INBx1, REFx, INxN, REFGND

AVDD +0.3 V to AGND −0.3 V

Ground Voltage Differences

AGND, DGND, OGND ±0.3 V

Supply Voltages

AVDD, DVDD, OVDD –0.3 V to +7 V AVDD to DVDD, AVDD to OVDD ±7 V DVDD to OVDD –0.3 V to +7 V

Digital Inputs –0.3 V to DVDD + 0.3 V Internal Power Dissipation2 700 mW Internal Power Dissipation3 2.5 W Junction Temperature 150°C Storage Temperature Range –65°C to +150°C Lead Temperature Range

(Soldering 10 sec) 300°C

1

See Analog Inputs section.

2

Specification is for device in free air:

48-lead LQFP: θ

3

Specification is for device in free air: 48-lead LFCSP: θJA = 26°C/W.

= 91°C/W, θJC = 30°C/W.

JA

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

I

1.6mA

TO OUTPUT

C

L

60pF*

500µA

*IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD C

OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.

L

OL

1.4V

I

OH

03536-002

Figure 2. Load Circuit for Digital Interface Timing.

SDOUT, SYNC, SCLK Outputs, CL = 10 pF

0.8V

t

DELAY

2V

0.8V

Figure 3. Voltage Reference Levels for Timing

2V

t

DELAY

2V

0.8V

03536-003

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. A | Page 7 of 28

AD7655

D

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AGND47AGND46INA145INAN44INA243REFA42REFB41INB240INBN39INB138REFGN

48

1

AGND

AVDD

A0

BYTESWAP

A/B

DGND IMPULSE SER/PAR

D0

D1 D2/DIVSCLK[0] D3/DIVSCLK[1]

10

11 12

2 3 4 5 6

7 8 9

PIN 1

13

14

D4/EXT/INT

D5/INVSYNC

AD7655

TOP VIEW

(Not to Scale)

15

16

17

D6/INVSCLK

D7/RDC/SDIN

18

OVDD

OGND

19

DVDD

Figure 4. 48-Lead LQFP (ST-48) and 48-Lead LFCSP (CP-48)

Table 6. Pin Function Descriptions

Pin No. Mnemonic Type1 Description

1, 47, 48 AGND P Analog Power Ground Pin. 2 AVDD P Input Analog Power Pin. Nominally 5 V. 3 A0 DI

Multiplexer Select. When LOW, the analog inputs INA1 and INB1 are sampled simultaneously, then converted. When HIGH, the analog inputs INA2 and INB2 are sampled simultaneously, then converted.

4 BYTESWAP DI

Parallel Mode Selection (8 bit, 16 bit). When LOW, the LSB is output on D[7:0] and the MSB is output on D[15:8]. When HIGH, the LSB is output on D[15:8] and the MSB is output on D[7:0].

5

A/

B

DI

Data Channel Selection. In parallel mode, when LOW, the data from Channel B is read. When HIGH, the data from Channel A is read. In serial mode, when HIGH, Channel A is output first followed by Channel

B. When LOW, Channel B is output first followed by Channel A. 6, 20 DGND P Digital Power Ground. 7 IMPULSE DI

Mode Selection. When HIGH, this input selects a reduced power mode. In this mode, the power

dissipation is approximately proportional to the sampling rate. 8

SER/

PAR

DI

Serial/Parallel Selection Input. When LOW, the parallel port is selected; when HIGH, the serial interface

mode is selected and some bits of the DATA bus are used as a serial port. 9, 10 D[0:1] DO

Bit 0 and Bit 1 of the Parallel Port Data Output Bus. When SER/

impedance. 11, 12 D[2:3] or DI/O

DIVSCLK[0:1]

When SER/

PAR is LOW, these outputs are used as Bit 2 and Bit 3 of the Parallel Port Data Output Bus. PAR is HIGH, EXT/INT is LOW, and RDC/SDIN is LOW, which is the serial master read after

convert mode; these inputs, part of the serial port, are used to slow down if desired the internal serial

clock that clocks the data output. In the other serial modes, these inputs are not used. 13 D[4] DI/O

or EXT/

INT

When SER/

When SER/PAR is HIGH, this input, part of the serial port, is used as a digital select input for choosing

PAR is LOW, this output is used as Bit 4 of the Parallel Port Data Output Bus.

the internal or an external data clock, called respectively, master and slave mode. With EXT/

LOW, the internal clock is selected on SCLK output. With EXT/

synchronized to an external clock signal connected to the SCLK input. 14 D[5] DI/O

or INVSYNC

When SER/

PAR is LOW, this output is used as Bit 5 of the Parallel Port Data Output Bus.

PAR is HIGH, this input, part of the serial port, is used to select the active state of the SYNC

signal in Master modes. When LOW, SYNC is active HIGH. When HIGH, SYNC is active LOW.

20

DGND

21

22

D8/SDOUT

D9/SCLK

REF

37

36

DVDD

35

CNVST

34

PD

33

RESET

32

CS

31

RD

30

EOC

29

BUSY

28

D15

27

D14

26

D13

25

D12

23

24

D10/SYNC

D11/RDERROR

03536-004

PAR is HIGH, these outputs are in high

INT tied

INT set to a logic HIGH, output data is

Rev. A | Page 8 of 28

AD7655

Pin No. Mnemonic Type1 Description

15 D[6] DI/O or INVSCLK

16 D[7] DI/O or RDC/SDIN

17 OGND P Input/Output Interface Digital Power Ground. 18 OVDD P

19, 36 DVDD P Digital Power. Nominally at 5 V. 21 D[8] DO

or SDOUT

If INVSCLK is LOW, SDOUT is updated on the SCLK rising edge and valid on the next falling edge. If INVSCLK is HIGH, SDOUT is updated on the SCLK falling edge and valid on the next rising edge. 22 D[9] DI/O

or SCLK

23 D[10] DO or SYNC

24 D[11] DO

or RDERROR

25 to 28 D[12:15] DO

29 BUSY DO

30 31 32

33 RESET DI

34 PD DI

EOC RD CS

DO End of Convert Output. Goes LOW at each channel conversion. DI DI

When SER/ When SER/

both Master and Slave modes. When SER/ When SER/

read mode selection input, depending on the state of EXT/ When EXT/

from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on SDOUT with a delay of 32 SCLK periods after the initiation of the read sequence.

When EXT/ previous data is output on SDOUT during conversion. When RDC/SDIN is LOW, the data can be output on SDOUT only when the conversion is complete.

Input/Output Interface Digital Power. Nominally at the same supply as the supply of the host interface (5 V or 3 V).

When SER/ When SER/

to SCLK. Conversion results are stored in a 32-bit on-chip register. The AD7655 provides the two conversion results, MSB first, from its internal shift register. The order of channel outputs is controlled by A/B. In serial mode, when EXT/INT is LOW, SDOUT is valid on both edges of SCLK.

In Serial Mode, when EXT/

When SER/

When SER/ dependent upon the logic state of the EXT/ depends on the logic state of the INVSCLK pin.

When SER/ When SER/

synchronization for use with the internal data clock (EXT/ When a read sequence is initiated and INVSYNC is LOW, SYNC is driven HIGH and frames SDOUT. After

the first channel is output, SYNC is pulsed LOW. When a read sequence is initiated and INVSYNC is HIGH, SYNC is driven LOW and remains LOW while SDOUT output is valid. After the first channel is output, SYNC is pulsed HIGH.

When SER/

When SER/ incomplete read error flag. In Slave mode, when a data read is started and not complete when the

following conversion is complete, the current data is lost and RDERROR is pulsed HIGH. Bit 12 to Bit 15 of the Parallel Port Data Output Bus. When SER/

impedance. Busy Output. Transitions HIGH when a conversion is started and remains HIGH until the two

conversions are complete and the data is latched into the on-chip shift register. The falling edge of BUSY can be used as a data ready clock signal.

Read Data. When Chip Select. When

also used to gate the external serial clock. Reset Input. When set to a logic HIGH, reset the AD7655. Current conversion if any is aborted. If not

used, this pin could be tied to DGND. Power-Down Input. When set to a logic HIGH, power consumption is reduced and conversions are

inhibited after the current one is completed.

PAR is LOW, this output is used as Bit 6 of the Parallel Port Data Output Bus. PAR is HIGH, this input, part of the serial port, is used to invert the SCLK signal. It is active in

PAR is LOW, this output is used as Bit 7 of the Parallel Port Data Output Bus. PAR is HIGH, this input, part of the serial port, is used as either an external data input or a

INT.

INT is HIGH, RDC/SDIN can be used as a data input to daisy-chain the conversion results

INT is LOW, RDC/SDIN is used to select the read mode. When RDC/SDIN is HIGH, the

PAR is LOW, this output is used as Bit 8 of the Parallel Port Data Output Bus. PAR is HIGH, this output, part of the serial port, is used as a serial data output synchronized

INT is HIGH:

PAR is LOW, this output is used as Bit 9 of the Parallel Port Data Output Bus. PAR

is HIGH, this pin, part of the serial port, is used as a serial data clock input or output,

INT pin. The active edge where the data SDOUT is updated

PAR is LOW, this output is used as Bit 10 of the Parallel Port Data Output Bus. PAR is HIGH, this output, part of the serial port, is used as a digital output frame

INT = Logic LOW).

PAR is LOW, this output is used as Bit 11 of the Parallel Port Data Output Bus.

PAR is HIGH and EXT/INT is HIGH, this output, part of the serial port, is used as an

PAR is HIGH, these outputs are in high

CS and RD are both LOW, the interface parallel or serial output bus is enabled.

CS and RD are both LOW, the interface parallel or serial output bus is enabled. CS is

Rev. A | Page 9 of 28

Analog Devices AD7655 a Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

SPECIFICATIONS

TIMING SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS