ANALOG DEVICES AD7654 Service Manual
16-Bit, 500 kSPS PulSAR® Dual,
V
A
VDDA
FEATURES
Dual, 16-bit, 2-channel simultaneous sampling ADC
16-bit resolution with no missing codes
Throughput:
500 kSPS (normal mode)
444 kSPS (impulse mode)
INL: ±3.5 LSB max (±0.0053% of full scale)
SNR: 89 dB typ @ 100 kHz
THD: −100 dB @ +100 kHz
Analog input voltage range: 0 V to 5 V
No pipeline delay
Parallel and serial 5 V/3 V interface
SPI®/QSPI™/MICROWIRE™/DSP compatible
Single 5 V supply operation
Power dissipation:
120 mW typical
2.6 mW @ 10 kSPS
Packages:
48-lead low profile quad flat package (LQFP)
48-lead lead frame chip scale package (LFCSP)
Low cost
APPLICATIONS
AC motor control
3-phase power control
4-channel data acquisition
Uninterrupted power supplies
Communications
2-Channel, Simultaneous Sampling ADC
AD7654
FUNCTIONAL BLOCK DIAGRAM
DD
D
SERIAL
PORT
PARALLEL
INTERFACE
DGND
OVDD
OGND
16
D[15:0]
SER/PAR
EOC
BUSY
CS
RD
A/B
BYTESWAP
AD7667
AD7623
GND REFxREFGND
TRACK/HOLD
INA1
INAN
INA2
A0
INB1
INBN
INB2
PD
RESET
×2
MUX
MUX
MUX
CONTROL LOGI C AND
CALIBRATION CIRCUITRY
AD7654
IMPULSE
SWITCHED
CAP DAC
CLOCK
CNVST
Figure 1.
Table 1. PulSAR Selection
Type/kSPS 100 to 250 500 to 570 800 to 1000 >1000
Pseudo
Differential
True Bipolar AD7663 AD7665 AD7671
True Differential AD7675 AD7676 AD7677 AD7621
18-Bit AD7678 AD7679 AD7674 AD7641
Multichannel/
Simultaneous
AD7660/
AD7661
AD7653
AD7654 AD7655
AD7650/
AD7652
AD7664/
AD7666
03057-001
GENERAL DESCRIPTION
The AD7654 is a low cost, simultaneous sampling, dualchannel, 16-bit, charge redistribution SAR, analog-to-digital
converter that operates from a single 5 V power supply. It
contains two low noise, wide bandwidth, track-and-hold
amplifiers that allow simultaneous sampling, a high speed
16-bit sampling ADC, an internal conversion clock, error
correction circuits, and both serial and parallel system interface
ports. Each track-and-hold has a multiplexer in front to provide
a 4-channel input ADC. The A0 multiplexer control input
allows the choice of simultaneously sampling input pairs
INA1/INB1 (A0 = low) or INA2/INB2 (A0 = high). The part
features a very high sampling rate mode (normal) and, for low
power applications, a reduced power mode (impulse) where the
power is scaled with the throughput. Operation is specified
from −40°C to +85°C.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
PRODUCT HIGHLIGHTS
1. Simultaneous Sampling.
The AD7654 features two sample-and-hold circuits that
allow simultaneous sampling. It provides inputs for four
channels.
2. Fast Throughput.
The AD7654 is a 500 kSPS, charge redistribution, 16-bit
SAR ADC with internal error correction circuitry.
3. Superior INL and No Missing Codes.
The AD7654 has a maximum integral nonlinearity of
3.5 LSB with no missing 16-bit codes.
4. Single-Supply Operation.
The AD7654 operates from a single 5 V supply. In impulse
mode, its power dissipation decreases with throughput.
5. Serial or Parallel Interface.
Versatile parallel or 2-wire serial interface arrangement is
compatible with both 3 V and 5 V logic.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.
AD7654
TABLE OF CONTENTS
Features.............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram ..............................................................1
General Description......................................................................... 1
Product Highlights........................................................................... 1
Specifications..................................................................................... 3
Timing Specifications ..................................................................5
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Terminology.................................................................................... 11
Typical Performance Characteristics........................................... 12
Application Information................................................................ 14
Circuit Information.................................................................... 14
Modes of Operation................................................................... 14
Driver Amplifier Choice ........................................................... 16
Voltage Reference Input ............................................................ 17
Power Supply............................................................................... 17
Power Dissipation....................................................................... 17
Conversion Control................................................................... 18
Digital Interface.......................................................................... 18
Parallel Interface......................................................................... 18
Serial Interface............................................................................ 20
Master Serial Interface............................................................... 20
Slave Serial Interface.................................................................. 22
Microprocessor Interfacing....................................................... 24
SPI Interface (ADSP-219x) ....................................................... 24
Application Hints ...........................................................................25
Layout .......................................................................................... 25
Evaluating the AD7654 Performance...................................... 25
Transfer Functions......................................................................14
Typical Connection Diagram ...................................................16
Analog Inputs..............................................................................16
Input Channel Multiplexer........................................................ 16
REVISION HISTORY
11/05—Rev. A to Rev. B
Changes to General Description .................................................... 1
Changes to Timing Specifications.................................................. 5
Changes to Figure 16...................................................................... 13
Changes to Figure 18...................................................................... 15
Added Table 8..................................................................................17
Changes to Figure 24...................................................................... 19
Changes to Figure 29...................................................................... 21
Updated Outline Dimensions....................................................... 26
Changes to Ordering Guide.......................................................... 26
Outline Dimensions....................................................................... 26
Ordering Guide .......................................................................... 27
11/04—Rev. 0 to Rev. A
Changes to Figure 7........................................................................ 12
Changes to Figure 18...................................................................... 15
Changes to Figure 19...................................................................... 16
Changes to Voltage Reference Input Section.............................. 17
Changes to Conversion Control Section..................................... 18
Changes to Digital Interface Section ........................................... 18
Updated Outline Dimensions...................................................... 25
11/02—Revision 0: Initial Version
Rev. B | Page 2 of 28
AD7654
SPECIFICATIONS
AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V; all specifications T
Table 2.
Parameter Conditions Min Typ Max Unit
RESOLUTION 16 Bits
ANALOG INPUT
Voltage Range V
Common-Mode Input Voltage V
– V
INx
INxN
0 2 V
INxN
−0.1 +0.5 V
Analog Input CMRR fIN = 100 kHz 55 dB
Input Current 500 kSPS throughput 45 µA
Input Impedance
1
THROUGHPUT SPEED
Complete Cycle In normal mode 2 µs
Throughput Rate In normal mode 0 500 kSPS
Complete Cycle In impulse mode 2.25 µs
Throughput Rate In impulse mode 0 444 kSPS
DC ACCURACY
Integral Linearity Error2 −3.5 +3.5 LSB3
No Missing Codes 16 Bits
Transition Noise 0.7 LSB
Full-Scale Error
4
T
to T
MIN
±0.25 ±0.5 % of FSR
MAX
Full-Scale Error Drift4 ±2 ppm/°C
Unipolar Zero Error
Unipolar Zero Error Drift
4
4
T
to T
MIN
±0.25 % of FSR
MAX
±0.8 ppm/°C
Power Supply Sensitivity AVDD = 5 V ±5% 0.8 LSB
AC ACCURACY
Signal-to-Noise fIN = 20 kHz 88 90 dB5
f
= 100 kHz 89 dB
IN
Spurious-Free Dynamic Range fIN = 100 kHz 105 dB
Total Harmonic Distortion fIN = 100 kHz −100 dB
Signal-to-Noise and Distortion fIN = 20 kHz 87.5 90 dB
f
f
= 100 kHz 88.5 dB
IN
= 100 kHz, −60 dB Input 30 dB
IN
Channel-to-Channel Isolation fIN = 100 kHz −92 dB
−3 dB Input Bandwidth 10 MHz
SAMPLING DYNAMICS
Aperture Delay 2 ns
Aperture Delay Matching 30 ps
Aperture Jitter 5 ps rms
Transient Response Full-scale step 250 ns
REFERENCE
External Reference Voltage Range 2.3 2.5 AVDD/2 V
External Reference Current Drain 500 kSPS throughput 180 µA
DIGITAL INPUTS
Logic Levels
VIL −0.3 +0.8 V
VIH +2.0 DVDD + 0.3 V
IIL −1 +1 µA
IIH −1 +1 µA
Rev. B | Page 3 of 28
MIN
to T
, unless otherwise noted.
MAX
V
REF
AD7654
Parameter Conditions Min Typ Max Unit
DIGITAL OUTPUTS
Data Format6
Pipeline Delay7
VOL I
VOH I
POWER SUPPLIES
Specified Performance
AVDD 4.75 5 5.25 V
DVDD 4.75 5 5.25 V
OVDD 2.7 5.258 V
Operating Current9 500 kSPS throughput
AVDD 15.5 mA
DVDD 8.5 mA
OVDD 100 µA
Power Dissipation 500 kSPS throughput9 120 135 mW
10 kSPS throughput10 2.6 mW
444 kSPS throughput10 114 125 mW
TEMPERATURE RANGE11
Specified Performance T
1
See the Analog Inputs section.
2
Linearity is tested using endpoints, not best fit.
3
LSB means least significant bit. Within the 0 V to 5 V input range, one LSB is 76.294 V.
4
See the Terminology section. These specifications do not include the error contribution from the external reference.
5
All specifications in dB are referred to as full-scale input, FS; tested with an input signal at 0.5 dB below full scale unless otherwise specified.
6
Parallel or serial 16-bit.
7
Conversion results are available immediately after completed conversion.
8
The maximum should be the minimum of 5.25 V and DVDD + 0.3 V.
9
In normal mode; tested in parallel reading mode.
10
In impulse mode; tested in parallel reading mode.
11
Consult sales for extended temperature range.
= 1.6 mA 0.4 V
SINK
= −500 µA OVDD − 0.2 V
SOURCE
to T
MIN
−40 +85 °C
MAX
Rev. B | Page 4 of 28
AD7654
TIMING SPECIFICATIONS
AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V; all specifications T
Table 3.
Parameter Symbol Min Typ Max Unit
CONVERSION AND RESET (See Figure 22 and Figure 23)
Convert Pulse Width t1 5 ns
Time Between Conversions
(Normal Mode/Impulse Mode) t2 2/2.25 µs
CNVST Low to BUSY High Delay
BUSY High All Modes Except in Master Serial Read After Convert Mode
(Normal Mode/Impulse Mode) t4 1.75/2 µs
Aperture Delay t5 2 ns
End of Conversions to BUSY Low Delay t6 10 ns
Conversion Time
(Normal Mode/Impulse Mode) t7 1.75/2 µs
Acquisition Time t8 250 ns
RESET Pulse Width t9 10 ns
CNVST Low to EOC High Delay
EOC High for Channel A Conversion
(Normal Mode/Impulse Mode) t11 1/1.25 µs
EOC Low after Channel A Conversion
EOC High for Channel B Conversion
Channel Selection Setup Time t
Channel Selection Hold Time t15 30 ns
PARALLEL INTERFACE MODES (See Figure 24 to Figure 28)
CNVST Low to DATA Valid Delay
DATA Valid to BUSY Low Delay t17 14 ns
Bus Access Request to DATA Valid t18 40 ns
Bus Relinquish Time t19 5 15 ns
A/B Low to Data Valid Delay
MASTER SERIAL INTERFACE MODES (see Figure 29 and Figure 30)
CS Low to SYNC Valid Delay
CS Low to Internal SCLK Valid Delay1
CS Low to SDOUT Delay
CNVST Low to SYNC Delay (Read During Convert)
(Normal Mode/Impulse Mode) t24 250/500 ns
SYNC Asserted to SCLK First Edge Delay t25 3 ns
Internal SCK Period
Internal SCLK High
2
2
Internal SCLK Low2 t28 7 ns
SDOUT Valid Setup Time
SDOUT Valid Hold Time
SCLK Last Edge to SYNC Delay
2
2
2
CS High to SYNC HI-Z
CS High to Internal SCLK HI-Z
CS High to SDOUT HI-Z
BUSY High in Master Serial Read After Convert2 t35 See Tabl e 4
CNVST Low to SYNC Asserted Delay
(Normal Mode/Impulse Mode) t36 0.75/1 µs
SYNC Deasserted to BUSY Low Delay t37 25 ns
Rev. B | Page 5 of 28
MIN
to T
, unless otherwise noted.
MAX
t
32 ns
3
t
30 ns
10
t
45 ns
12
t
0.75 µs
13
250 ns
14
t
1.75/2 µs
16
t
40 ns
20
t
10 ns
21
t
10 ns
22
t
10 ns
23
t26 23 40 ns
t27 12 ns
t29 4 ns
t30 2 ns
t31 1 ns
t
10 ns
32
t
10 ns
33
t
10 ns
34
AD7654
Parameter Symbol Min Typ Max Unit
SLAVE SERIAL INTERFACE MODES (see Figure 32 and Figure 33)
External SCLK Setup Time t38 5 ns
External SCLK Active Edge to SDOUT Delay t39 3 18 ns
SDIN Setup Time t40 5 ns
SDIN Hold Time t41 5 ns
External SCLK Period t42 25 ns
External SCLK High t43 10 ns
External SCLK Low t44 10 ns
1
In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise CL is 60 pF maximum.
2
In serial master read during convert mode. See Table 4 for serial master read after convert mode.
Table 4. Serial Clock Timings in Master Read After Convert
DIVSCLK[1]
DIVSCLK[0] Symbol 0 1 0 1 Unit
SYNC to SCLK First Edge Delay Minimum
Internal SCLK Period Minimum t26 25 50 100 200 ns
Internal SCLK Period Typical t26 40 70 140 280 ns
Internal SCLK High Minimum t27 12 22 50 100 ns
Internal SCLK Low Minimum t28 7 21 49 99 ns
SDOUT Valid Setup Time Minimum t29 4 18 18 18 ns
SDOUT Valid Hold Time Minimum t30 2 4 30 80 ns
SCLK Last Edge to SYNC Delay Minimum t31 1 3 30 80 ns
Busy High Width Maximum (Normal) t35 3.25 4.25 6.25 10.75 µs
Busy High Width Maximum (Impulse) t35 3.5 4.5 6.5 11 µs
0 0 1 1
3 17 17 17 ns
t
25
Rev. B | Page 6 of 28
AD7654
*
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Values
Analog Inputs
INAx1, INBx1, REFx, INxN,
REFGND
AVDD + 0.3 V to
AGND − 0.3 V
Ground Voltage Differences
AGND, DGND, OGND ±0.3 V
Supply Voltages
AVDD, DVDD, OVDD −0.3 V to +7 V
AVDD to DVDD, AVDD to OVDD ±7 V
DVDD to OVDD −0.3 V to +7 V
Digital Inputs −0.3 V to DVDD + 0.3 V
Internal Power Dissipation
Internal Power Dissipation
2
3
700 mW
2.5 W
Junction Temperature 150°C
Storage Temperature Range −65°C to +150°C
Lead Temperature Range
(Soldering 10 sec) 300°C
1
See Analog Inputs section.
2
Specification is for device in free air:
48-lead LQFP: θJA = 91°C/W, θJC = 30°C/W.
3
Specification is for device in free air: 48-lead LFCSP; θJA = 26°C/W.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
I
1.6mA
TO OUTPUT
PIN
C
L
60pF*
500µA
IN SERIAL I NTERFACE MODES, THE SYNC, SCLK, AND
SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LO AD
OF 10pF; OTHERWI SE, THE LOAD IS 60pF MAXIMUM.
C
L
OL
1.4V
I
OH
03057-002
Figure 2. Load Circuit for Digital Interface Timing
(SDOUT, SYNC, SCLK Outputs, C
= 10 pF)
L
0.8V
t
DELAY
2V
0.8V
Figure 3. Voltage Reference Levels for Timing
2V
t
DELAY
2V
0.8V
03057-003
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. B | Page 7 of 28
AD7654
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AGND47AGND46INA145INAN44INA243REFA42REFB41INB240INBN39INB138REFGND37REF
48
1
AGND
AVD D
A0
BYTESWAP
A/B
DGND
IMPULSE
SER/PAR
D0
D1
D2/DIVSCLK[0]
D3/DIVSCLK[1]
Figure 4. 48-Lead LQFP (ST-48) and 48-Lead LFCSP (CP-48)
Table 6. Pin Function Descriptions
Pin No. Mnemonic Type1 Description
1, 47, 48 AGND P Analog Power Ground Pin.
2 AVDD P Input Analog Power Pin. Nominally 5 V.
3 A0 DI
Multiplexer Select. When LOW, the analog inputs INA1 and INB1 are sampled simultaneously, then
converted. When HIGH, the analog inputs INA2 and INB2 are sampled simultaneously, then converted.
4 BYTESWAP DI
Parallel Mode Selection (8 bit, 16 bit). When LOW, the LSB is output on D[7:0] and the MSB is output on
D[15:8]. When HIGH, the LSB is output on D[15:8] and the MSB is output on D[7:0].
5
A/
B
DI
Data Channel Selection. In parallel mode, when LOW, the data from Channel B is read. When HIGH, the
data from Channel A is read. In serial mode, when HIGH, Channel A is output first followed by Channel
B. When LOW, Channel B is output first followed by Channel A.
6, 20 DGND P Digital Power Ground.
7 IMPULSE DI
Mode Selection. When HIGH, this input selects a reduced power mode. In this mode, the power
dissipation is approximately proportional to the sampling rate.
8
SER/
PA R
DI
Serial/Parallel Selection Input. When LOW, the parallel port is selected; when HIGH, the serial interface
mode is selected and some bits of the DATA bus are used as a serial port.
9, 10 D[0:1] DO
Bit 0 and Bit 1 of the Parallel Port Data Output Bus. When SER/
impedance.
11, 12 D[2:3] or DI/O
DIVSCLK[0:1]
When SER/
When SER/
PA R is LOW, these outputs are used as Bit 2 and Bit 3 of the parallel port data output bus.
PA R is HIGH, EXT/INT is LOW, and RDC/SDIN is LOW, which is the serial master read after
convert mode, these inputs, part of the serial port, are used to slow down if desired the internal serial
clock that clocks the data output. In the other serial modes, these inputs are not used.
13 D[4] DI/O
or EXT/
INT
When SER/
When SER/PA Ris HIGH, this input, part of the serial port, is used as a digital select input for choosing
PA Ris LOW, this output is used as Bit 4 of the parallel port data output bus.
the internal or an external data clock, called respectively, master and slave mode. With EXT/
LOW, the internal clock is selected on SCLK output. With EXT/
synchronized to an external clock signal connected to the SCLK input.
14 D[5] DI/O
or INVSYNC
When SER/
When SER/
PA R is LOW, this output is used as Bit 5 of the parallel port data output bus.
PA R is HIGH, this input, part of the serial port, is used to select the active state of the SYNC
signal in Master modes. When LOW, SYNC is active HIGH. When HIGH, SYNC is active LOW.
PIN 1
2
3
4
5
6
7
8
9
10
11
12
13
14
D4/EXT/INT
15
D5/INVSYNC
(Not to Scale)
16
17
D6/INVSCLK
D7/RDC/SDIN
AD7654
TOP VIEW
18
19
OVDD
OGND
20
21
22
DVDD
DGND
D8/SDOUT
36
DVDD
35
CNVST
34
PD
33
RESET
32
CS
31
RD
30
EOC
29
BUSY
28
D15
27
D14
26
D13
25
D12
23
24
D9/SCLK
D10/SYNC
D11/RDERROR
03057-004
PA R is HIGH, these outputs are in high
INT tied
INT set to a logic HIGH, output data is
Rev. B | Page 8 of 28
AD7654
Pin No. Mnemonic Type1 Description
15 D[6] DI/O
or INVSCLK
16 D[7] DI/O
or RDC/SDIN
17 OGND P Input/Output Interface Digital Power Ground.
18 OVDD P
19, 36 DVDD P Digital Power. Nominally at 5 V.
21 D[8] DO
or SDOUT
If INVSCLK is LOW, SDOUT is updated on the SCLK rising edge and valid on the next falling edge.
If INVSCLK is HIGH, SDOUT is updated on the SCLK falling edge and valid on the next rising edge.
22 D[9] DI/O
or SCLK
23 D[10] DO
or SYNC
24 D[11] DO
or RDERROR
25 to 28 D[12:15] DO
29 BUSY DO
30
31
32
33 RESET DI
34 PD DI
EOC
RD
CS
DO End of Convert Output. Goes LOW at each channel conversion.
DI
DI
When SER/
When SER/
both master and slave modes.
When SER/
When SER/
read mode selection input, depending on the state of EXT/INT.
When EXT/
from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on SDOUT
with a delay of 32 SCLK periods after the initiation of the read sequence.
When EXT/
previous data is output on SDOUT during conversion. When RDC/SDIN is LOW, the data can be output
on SDOUT only when the conversion is complete.
Input/Output Interface Digital Power. Nominally at the same supply as the supply of the host interface
(5 V or 3 V).
When SER/
When SER/
to SCLK. Conversion results are stored in a 32-bit on-chip register. The AD7654 provides the two
conversion results, MSB first, from its internal shift register. The order of channel outputs is controlled
by A/B. In serial mode, when EXT/INT is LOW, SDOUT is valid on both edges of SCLK.
In Serial Mode, when EXT/
When SER/
When SER/
dependent upon the logic state of the EXT/
depends on the logic state of the INVSCLK pin.
When SER/
When SER/
synchronization for use with the internal data clock (EXT/INT = Logic LOW).
When a read sequence is initiated and INVSYNC is LOW, SYNC is driven HIGH and frames SDOUT. After
the first channel is output, SYNC is pulsed LOW. When a read sequence is initiated and INVSYNC is
HIGH, SYNC is driven LOW and remains LOW while SDOUT output is valid. After the first channel is
output, SYNC is pulsed HIGH.
When SER/
When SER/
incomplete read error flag. In Slave mode, when a data read is started and not complete when the
following conversion is complete, the current data is lost and RDERROR is pulsed HIGH.
Bit 12 to Bit 15 of the parallel port data output bus. When SER/
impedance.
Busy Output. Transitions HIGH when a conversion is started and remains HIGH until the two
conversions are complete and the data is latched into the on-chip shift register. The falling edge of
BUSY can be used as a data ready clock signal.
Read Data. When CS and RD are both LOW, the interface parallel or serial output bus is enabled.
Chip Select. When CS and RD are both LOW, the interface parallel or serial output bus is enabled. CS is
also used to gate the external serial clock.
Reset Input. When set to a logic HIGH, reset the AD7654. Current conversion if any is aborted. If not
used, this pin could be tied to DGND.
Power-Down Input. When set to a logic HIGH, power consumption is reduced and conversions are
inhibited after the current one is completed.
PA R is LOW, this output is used as Bit 6 of the parallel port data output bus.
PA R is HIGH, this input, part of the serial port, is used to invert the SCLK signal. It is active in
PA R is LOW, this output is used as Bit 7 of the parallel port data output bus.
PA R is HIGH, this input, part of the serial port, is used as either an external data input or a
INT is HIGH, RDC/SDIN can be used as a data input to daisy-chain the conversion results
INT is LOW, RDC/SDIN is used to select the read mode. When RDC/SDIN is HIGH, the
PA R is LOW, this output is used as Bit 8 of the Parallel port data output bus.
PA R is HIGH, this output, part of the serial port, is used as a serial data output synchronized
INT is HIGH:
PA R is LOW, this output is used as Bit 9 of the Parallel Port Data Output Bus.
PA R is HIGH, this pin, part of the serial port, is used as a serial data clock input or output,
INT pin. The active edge where the data SDOUT is updated
PA R is LOW, this output is used as Bit 10 of the parallel port data output bus.
PA R is HIGH, this output, part of the serial port, is used as a digital output frame
PA R is LOW, this output is used as Bit 11 of the parallel port data output bus.
PA R is HIGH and EXT/INT is HIGH, this output, part of the serial port, is used as an
PA R is HIGH, these outputs are in high
Rev. B | Page 9 of 28
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