Analog Devices AD7652 Datasheet
16-Bit 500 kSPS PulSAR
TM
FEATURES
Throughput: 500 kSPS
16-bit resolution
Analog input voltage range: 0 V to 2.5 V
No pipeline delay
Parallel and serial 5 V/3 V interface
®/QSPI
TM
/MICROWIRETM/DSP compatible
SPI
Single 5 V supply operation
Power dissipation
65 mW typ, 130 µW @ 1 kSPS without REF
80 mW typ with REF
48-lead LQFP and 48-lead LFCSP packages
Pin-to-pin compatible with PulSAR ADCs
APPLICATIONS
Data acquisition
Instrumentation
Digital signal processing
Spectrum analysis
Medical instruments
Battery-powered systems
Process control
GENERAL DESCRIPTION
The AD7652* is a 16-bit, 500 kSPS, charge redistribution SAR
analog-to-digital converter that operates from a single 5 V
power supply. The part contains a high speed 16-bit sampling
ADC, an internal conversion clock, internal reference, error
correction circuits, and both serial and parallel system interface
ports.
The AD7652 is fabricated using Analog Devices’ high performance, 0.6 micron CMOS process, with correspondingly low cost,
and is available in a 48-lead LQFP and a tiny 48-lead LFCSP
with operation specified from –40°C to +85°C.
*
Patent Pending.
Unipolar ADC with Reference
AD7652
FUNCTIONAL BLOCK DIAGRAM
REFBUFIN
AGND
AVDD
INGND
PDREF
PDBUF
RESET
REF
IN
PD
Table 1. PulSAR Selection
Type/kSPS 100–250 500–570
PseudoDifferential
True Bipolar AD7663 AD7665 AD7671
True
Differential
18-Bit AD7678 AD7679 AD7674
Multichannel/
Simultaneous
PRODUCT HIGHLIGHTS
1. Fast Throughput.
The AD7652 is a 500 kSPS, charge redistribution, 16-bit
SAR ADC with internal error correction circuitry.
2. Internal Reference.
The AD7652 has an internal reference with a typical
temperature drift of 7 ppm/°C.
3. Single-Supply Operation.
The AD7652 operates from a single 5 V supply. Its power
dissipation decreases with throughput.
REF REFGND
AD7652
SWITCHED
CAP DAC
CLOCK
CONTROL LOGIC AND
CALIBRATION CIRCUITRY
CNVST
Figure 1. Functional Block Diagram
AD7651
AD7660/AD7661
AD7650/AD7652
AD7664/AD7666
SERIAL
PORT
PARALLEL
INTERFACE
DGNDDVDD
16
AD7675 AD7676 AD7677
AD7654
AD7655
OVDD
OGND
DATA[15:0]
BUSY
RD
CS
SER/PAR
OB/2C
BYTESWAP
02965-0-001
800–
1000
AD7653
AD7667
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
4. Serial or Parallel Interface.
Versatile parallel or 2-wire serial interface arrangement is
compatible with both 3 V and 5 V logic.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved.
AD7652
TABLE OF CONTENTS
Specifications..................................................................................... 3
Timing Specifications....................................................................... 5
Absolute Maximum Ratings............................................................ 7
Pin Configuration and Function Descriptions............................. 8
Definitions of Specifications ......................................................... 11
Typical Performance Characteristics ........................................... 12
Circuit Information........................................................................ 15
Converter Operation.................................................................. 15
Typical Connection Diagram.................................................... 17
Power Dissipation versus Throughput .................................... 19
Conversion Control.................................................................... 19
Digital Interface.......................................................................... 20
REVISION HISTORY
Revision 0, Initial Version.
Parallel Interface......................................................................... 20
Serial Interface............................................................................ 20
Master Serial Interface............................................................... 21
Slave Serial Interface.................................................................. 22
Microprocessor Interfacing....................................................... 24
Application Hints............................................................................ 25
Bipolar and Wider Input Ranges.............................................. 25
Layout .......................................................................................... 25
Evaluating the AD7652’s Performance.................................... 25
Outline Dimensions....................................................................... 26
Ordering Guide........................................................................... 26
Rev. 0 | Page 2 of 28
AD7652
SPECIFICATIONS
Table 2. –40°C to +85°C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted
Parameter Conditions Min Typ Max Unit
RESOLUTION 16 Bits
ANALOG INPUT
Voltage Range VIN – V
Operating Input Voltage VIN –0.1 +3 V
0 V
INGND
V
REF
V
–0.1 +0.5 V
INGND
Analog Input CMRR fIN = 10 kHz 65 dB
Input Current 500 kSPS Throughput 6.1 µA
Input Impedance1
THROUGHPUT SPEED
Complete Cycle 2 µs
Throughput Rate 0 500 kSPS
DC ACCURACY
Integral Linearity Error –6 +6 LSB2
No Missing Codes 15 Bits
Differential Linearity Error –2 +3 LSB
Transition Noise 0.7 LSB
Unipolar Zero Error, T
MIN
to T
3
±5 LSB
MAX
Unipolar Zero Error Temperature Drift3 ±0.24 ppm/°C
Full-Scale Error, T
MIN
to T
3
REF = 2.5 V ±0.12 % of FSR
MAX
Full-Scale Error Temperature Drift ±0.5 ppm/°C
Power Supply Sensitivity AVDD = 5 V ± 5% ±2 LSB
AC ACCURACY
Signal-to-Noise fIN = 100 kHz 86 dB4
Spurious Free Dynamic Range fIN = 100 kHz 98 dB
Total Harmonic Distortion fIN = 45 kHz –98 dB
f
= 100 kHz –96 dB
IN
Signal-to-(Noise + Distortion) fIN = 100 kHz 86 dB
–60 dB Input, fIN = 100 kHz 30 dB
–3 dB Input Bandwidth 12 MHz
SAMPLING DYNAMICS
Aperture Delay 2 ns
Aperture Jitter 5 ps rms
Transient Response Full-Scale Step 750 ns
REFERENCE
Internal Reference Voltage V
@ 25°C 2.48 2.5 2.52 V
REF
Internal Reference Temperature Drift –40°C to +85°C ±7 ppm/°C
Line Regulation
Turn-On Settling Time C
AVDD = 5 V ± 5%
= 10 µF 5 ms
REF
±24 ppm/V
Temperature Pin
Voltage Output @ 25°C 300 mV
Temperature Sensitivity 1 mV/°C
Output Resistance 4.3 kΩ
External Reference Voltage Range 2.3 2.5 AVDD – 1.85 V
External Reference Current Drain 500 kSPS Throughput 110 µA
Rev. 0 | Page 3 of 28
AD7652
Parameter Conditions Min Typ Max Unit
DIGITAL INPUTS
Logic Levels
VIL –0.3 +0.8 V
VIH 2.0 DVDD + 0.3 V
IIL –1 +1 µA
IIH –1 +1 µA
DIGITAL OUTPUTS
Data Format5
Pipeline Delay6
VOL I
VOH I
POWER SUPPLIES
Specified Performance
AVDD 4.75 5 5.25 V
DVDD 4.75 5 5.25 V
OVDD 2.7 5.257 V
Operating Current 500 kSPS Throughput
AVDD8 With Reference and Buffer 12.2 mA
AVDD9 Reference and Buffer Alone 3 mA
DVDD10 3.8 mA
10
OVDD
102 µA
Power Dissipation without REF10 500 kSPS Throughput 65 75 mW
1 kSPS Throughput 130 µW
Power Dissipation with REF10 500 kSPS Throughput 80 90 mW
TEMPERATURE RANGE11
Specified Performance T
1
See section. Analog Input
2
LSB means least significant bit. With the 0 V to 2.5 V input range, 1 LSB is 38.15 µV.
3
See section. These specifications do not include the error contribution from the external reference. Definitions of Specifications
4
All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified.
5
Parallel or Serial 16-Bit.
6
Conversion results are available immediately after completed conversion.
7
The max should be the minimum of 5.25 V and DVDD + 0.3 V.
8
With REF, PDREF and PDBUF are LOW; without REF, PDREF and PDBUF are HIGH.
9
With PDREF, PDBUF LOW and PD HIGH.
10
Tested in Parallel Reading Mode
11
Consult factory for extended temperature range.
= 1.6 mA 0.4 V
SINK
= –500 µA OVDD – 0.6 V
SOURCE
to T
MIN
–40 +85 °C
MAX
Rev. 0 | Page 4 of 28
TIMING SPECIFICATIONS
Table 3. –40°C to +85°C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted
Parameter
Refer to Figure 26 and Figure 27
Convert Pulsewidth
Time between Conversions
CNVST
LOW to BUSY HIGH Delay
BUSY HIGH All Modes Except Master Serial Read after Convert
Aperture Delay
End of Conversion to BUSY LOW Delay
Conversion Time
Acquisition Time
RESET Pulsewidth
Refer to Figure 28, Figure 29, and (Parallel Interface Modes)
CNVST
LOW to DATA Valid Delay
Figure 30
DATA Valid to BUSY LOW Delay
Bus Access Request to DATA Valid
Bus Relinquish Time
Refer to Figure 32 and Figure 33 (Master Serial Interface Modes)1
CS
LOW to SYNC Valid Delay
CS
LOW to Internal SCLK Valid Delay1
CS
LOW to SDOUT Delay
CNVST
LOW to SYNC Delay
SYNC Asserted to SCLK First Edge Delay
Internal SCLK Period2
Internal SCLK HIGH2
Internal SCLK LOW2
SDOUT Valid Setup Time2
SDOUT Valid Hold Time2
SCLK Last Edge to SYNC Delay2
CS
HIGH to SYNC HI-Z
CS
HIGH to Internal SCLK HI-Z
CS
HIGH to SDOUT HI-Z
BUSY HIGH in Master Serial Read after Convert2
CNVST
LOW to SYNC Asserted Delay
SYNC Deasserted to BUSY LOW Delay
Refer to and (Slave Serial Interface Modes)1
Figure 34 Figure 35
External SCLK Setup Time
External SCLK Active Edge to SDOUT Delay
SDIN Setup Time
SDIN Hold Time
External SCLK Period
External SCLK HIGH
External SCLK LOW
1
In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.
2
In Serial Master Read during Convert Mode. See Table 4 for serial master read after convert mode.
Symbol
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
t
12
t
13
t
14
t
15
t
16
t
17
t
18
t
19
t
20
t
21
t
22
t
23
t
24
t
25
t
26
t
27
t
28
t
29
t
30
t
31
t
32
t
33
t
34
t
35
t
36
t
37
Min Typ Max Unit
10 ns
2 µs
35 ns
1.25 µs
2 ns
10 ns
1.25 µs
750 ns
10 ns
1.25 µs
12 ns
45 ns
5 15 ns
10 ns
10 ns
10 ns
525 ns
3 ns
25 40 ns
12 ns
7 ns
4 ns
2 ns
3 ns
10 ns
10 ns
10 ns
See Table 4
1.25 µs
25 ns
5 ns
3 18 ns
5 ns
5 ns
25 ns
10 ns
10 ns
AD7652
Rev. 0 | Page 5 of 28
AD7652
Table 4. Serial Clock Timings in Master Read after Convert
DIVSCLK[1] 0 0 1 1
DIVSCLK[0] Symbol 0 1 0 1 Unit
SYNC to SCLK First Edge Delay Minimum t18 3 17 17 17 ns
Internal SCLK Period Minimum t19 25 50 100 200 ns
Internal SCLK Period Maximum t19 40 70 140 280 ns
Internal SCLK HIGH Minimum t20 12 22 50 100 ns
Internal SCLK LOW Minimum t21 7 21 49 99 ns
SDOUT Valid Setup Time Minimum t22 4 18 18 18 ns
SDOUT Valid Hold Time Minimum t23 2 4 30 80 ns
SCLK Last Edge to SYNC Delay Minimum t24 3 55 130 290 ns
BUSY HIGH Width Maximum t24 2 2.5 3.5 5.75 µs
Rev. 0 | Page 6 of 28
ABSOLUTE MAXIMUM RATINGS
Table 5. AD7652 Stress Ratings1
IN2, TEMP2, REF, REFBUFIN,
INGND, REFGND to AGND
Ground Voltage Differences
AGND, DGND, OGND ±0.3 V
Supply Voltages
AVDD, DVDD, OVDD –0.3 V to +7 V
AVDD to DVDD, AVDD to OVDD ±7 V
DVDD to OVDD –0.3 V to +7 V
Digital Inputs –0.3 V to DVDD + 0.3 V
PDREF, PDBUF
3
Internal Power Dissipation4 700 mW
Internal Power Dissipation5 2.5 W
Junction Temperature 150°C
Storage Temperature Range –65°C to +150°C
Lead Temperature Range
(Soldering 10 sec)
1
Stresses above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional
operation of the device at these or any other conditions above those listed
in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect
device reliability.
2
See Analog Input section.
3
See Voltage Reference Input Section.
4
Specification is for the device in free air:
48-Lead LQFP; θJA = 91°C/W, θJC = 30°C/W
5
Specification is for the device in free air:
48-Lead LFCSP; θJA = 26°C/W.
AVDD + 0.3 V to
AGND – 0.3 V
±20 mA
300°C
1.6mA
TO OUTPUT
PIN
C
L
60pF*
500µA
* IN SERIAL INTERFACE MODES,THE SYNC, SCLK, AND
SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD
OF 10pF; OTHERWISE,THE LOAD IS 60pF MAXIMUM.
C
L
I
OL
1.4V
I
OH
02964-0-006
Figure 2. Load Circuit for Digital Interface Timing,
SDOUT, SYNC, SCLK Outputs C
0.8V
t
DELAY
2V
0.8V
L
2V
= 10 pF
t
DELAY
2V
0.8V
02965-0-007
Figure 3. Voltage Reference Levels for Timing
AD7652
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 7 of 28
AD7652
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PDBUF
PDREF
REFBUFIN
TEMP
AVDDINAGND
AGNDNCINGND
REFGND
D8/SDOUT
D9/SCLK
D10/SYNC
REF
D11/RDERROR
36
35
34
33
32
31
30
29
28
27
26
25
02965-0-002
AGND
CNVST
PD
RESET
CS
RD
DGND
BUSY
D15
D14
D13
D12
is HIGH, these outputs are in high
tied LOW, the internal clock is selected
48
47 46 45 44 39 38 3743 42 41 40
1
AGND
AVDD
NC
BYTESWAP
OB/2C
NC
NC
SER/PAR
D0
D1
D2/DIVSCLK0
D3/DIVSCLK1
NC = NO CONNECT
PIN 1
IDENTIFIER
2
3
4
5
6
7
8
9
10
11
12
13 14
D4/EXT/INT
AD7652
TOP VIEW
(Not to Scale)
15 16 17 18 19 20 21 22 23 24
DVDD
OVDD
DGND
OGND
D6/INVSCLK
D5/INVSYNC
D7/RDC/SDIN
Figure 4. 48-Lead LQFP (ST-48) and 48-Lead LFCSP (CP-48)
Table 6. Pin Function Descriptions
Pin No. Mnemonic Type1 Description
1, 36,
AGND P Analog Power Ground Pin.
41, 42
2, 44 AVDD P Input Analog Power Pin. Nominally 5 V.
3, 6,
NC No Connect.
7, 40
4 BYTESWAP DI Parallel Mode Selection (8-/16-bit). When LOW, the LSB is output on D[7:0] and the MSB is output on
D[15:8]. When HIGH, the LSB is output on D[15:8] and the MSB is output on D[7:0].
5
OB/2C
DI
Straight Binary/Binary Twos Complement. When OB/2C is HIGH, the digital output is straight binary;
when LOW, the MSB is inverted, resulting in a twos complement output from its internal shift register.
8
SER/PAR
DI Serial/Parallel Selection Input. When LOW, the parallel port is selected; when HIGH, the serial interface
mode is selected and some bits of the DATA bus are used as a serial port.
9, 10 D[0:1] DO
Bit 0 and Bit 1 of the Parallel Port Data Output Bus. When SER/PAR
impedance.
11, 12 D[2:3]or
DIVSCLK[0:1]
DI/O
When SER/PAR
When SER/PAR
is LOW, these outputs are used as Bit 2 and Bit 3 of the parallel port data output bus.
is HIGH, EXT/INT is LOW, and RDC/SDIN is LOW (serial master read after convert), these
inputs, part of the serial port, are used to slow down, if desired, the internal serial clock that clocks the
data output. In other serial modes, these pins are not used.
13 D4 or
INT
EXT/
DI/O
When SER/PAR is LOW, this output is used as Bit 4 of the parallel port data output bus.
When SER/PAR
is HIGH, this input, part of the serial port, is used as a digital select input for choosing
the internal data clock or an external data clock. With EXT/INT
on the SCLK output. With EXT/INT
set to a logic HIGH, output data is synchronized to an external clock
signal connected to the SCLK input.
14 D5 or
INVSYNC
DI/O
When SER/PAR
When SER/PAR
is LOW, this output is used as Bit 5 of the parallel port data output bus.
is HIGH, this input, part of the serial port, is used to select the active state of the SYNC
signal. It is active in both master and slave modes. When LOW, SYNC is active HIGH. When HIGH, SYNC
is active LOW.
15 D6 or
INVSCLK
DI/O
When SER/PAR
When SER/PAR
is LOW, this output is used as Bit 6 of the parallel port data output bus.
is HIGH, this input, part of the serial port, is used to invert the SCLK signal. It is active in
both master and slave modes.
Rev. 0 | Page 8 of 28
Pin No. Mnemonic Type1 Description
16 D7 or
RDC/SDIN
17 OGND P Input/Output Interface Digital Power Ground.
18 OVDD P Input/Output Interface Digital Power. Nominally at the same supply as the host interface (5 V or 3 V).
19 DVDD P Digital Power. Nominally at 5 V.
20 DGND P Digital Power Ground.
21 D8 or
SDOUT
22 D9 or
SCLK
23 D10 or
SYNC
24 D11 or
RDERROR
25–28 D[12:15] DO Bit 12 to Bit 15 of the Parallel Port Data Output Bus. These pins are always outputs regardless of the
29 BUSY DO Busy Output. Transitions HIGH when a conversion is started and remains HIGH until the conversion is
30 DGND P Must Be Tied to Digital Ground.
31
32
33 RESET DI Reset Input. When set to a logic HIGH, this pin resets the AD7652 and the current conversion, if any, is
34 PD DI Power-Down Input. When set to a logic HIGH, power consumption is reduced and conversions are
35
37 REF AI/O Reference Input Voltage. On-chip reference output voltage.
38 REFGND AI Reference Input Analog Ground.
39 INGND AI Analog Input Ground.
43 IN AI Primary Analog Input with a Range of 0 V to 2.5 V.
RD
CS
CNVST
DI/O
DO
DI/O
DO
DO
DI
DI
DI
When SER/PAR
When SER/PAR
read mode selection input depending on the state of EXT/INT
When EXT/INT
from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on DATA
with a delay of 16 SCLK periods after the initiation of the read sequence.
When EXT/INT is LOW, RDC/SDIN is used to select the read mode. When RDC/SDIN is HIGH, the data is
output on SDOUT during conversion. When RDC/SDIN is LOW, the data can be output on SDOUT only
when the conversion is complete.
When SER/PAR
When SER/PAR
to SCLK. Conversion results are stored in an on-chip register. The AD7652 provides the conversion
result, MSB first, from its internal shift register. The DATA format is determined by the logic level of
OB/2C
. In serial mode when EXT/INT is LOW, SDOUT is valid on both edges of SCLK. In serial mode
when EXT/INT
next falling edge; if INVSCLK is HIGH, SDOUT is updated on the SCLK falling edge and valid on the next
rising edge.
When SER/PAR
When SER/PAR
depending upon the logic state of the EXT/INT
depends upon the logic state of the INVSCLK pin.
When SER/PAR
When SER/PAR
synchronization for use with the internal data clock (EXT/INT
initiated and INVSYNC is LOW, SYNC is driven HIGH and remains HIGH while the SDOUT output is
valid. When a read sequence is initiated and INVSYNC is HIGH, SYNC is driven LOW and remains LOW
while the SDOUT output is valid.
When SER/PAR
SER/PAR
flag. In slave mode, when a data read is started and not complete when the following conversion is
complete, the current data is lost and RDERROR is pulsed HIGH.
state of SER/PAR.
complete and the data is latched into the on-chip shift register. The falling edge of BUSY could be
used as a data ready clock signal.
Read Data. When CS and RD are both LOW, the interface parallel or serial output bus is enabled.
Chip Select. When CS and RD are both LOW, the interface parallel or serial output bus is enabled. CS is
also used to gate the external clock.
aborted. If not used, this pin could be tied to DGND.
inhibited after the current one is completed.
Start Conversion. If CNVST is HIGH when the acquisition phase (t8) is complete, the next falling edge
on CNVST
most appropriate if low sampling jitter is desired. If CNVST
complete, the internal sample/hold is put into the hold state and a conversion is immediately started.
is LOW, this output is used as Bit 7 of the parallel port data output bus.
is HIGH, this input, part of the serial port, is used as either an external data input or a
.
is HIGH, RDC/SDIN could be used as a data input to daisy-chain the conversion results
is LOW, this output is used as Bit 8 of the parallel port data output bus.
is HIGH, this output, part of the serial port, is used as a serial data output synchronized
is HIGH, if INVSCLK is LOW, SDOUT is updated on the SCLK rising edge and valid on the
is LOW, this output is used as Bit 9 of the parallel port data or SCLK output bus.
is HIGH, this pin, part of the serial port, is used as a serial data clock input or output,
pin. The active edge where the data SDOUT is updated
is LOW, this output is used as Bit 10 of the parallel port data output bus.
is HIGH, this output, part of the serial port, is used as a digital output frame
= logic LOW). When a read sequence is
is LOW, this output is used as Bit 11 of the parallel port data output bus. When
and EXT/INT are HIGH, this output, part of the serial port, is used as an incomplete read error
puts the internal sample/hold into the hold state and initiates a conversion. The mode is
is LOW when the acquisition phase (t8) is
AD7652
Rev. 0 | Page 9 of 28
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