Analog Devices AD7650 Datasheet

16-Bit, 570 kSPS

a

FEATURES
Throughput

570 kSPS (Warp Mode)

500 kSPS (Normal Mode)
16 Bits Resolution
Analog Input Voltage Range: 0 V to 2.5 V
No Pipeline Delay
Parallel and Serial 5 V/3 V Interface

SPI™/QSPI™/MICROWIRE™/DSP
Single 5 V Supply Operation
Power Dissipation

77 mW Typical @ 444 kSPS (Impulse Mode)

21 ␮W @ 100 SPS
Power-Down Mode: 7 ␮W Max
Package: 48-Lead Quad Flat Pack (LQFP) or 48-Lead

Frame Chip-Scale Pack (LFCSP)
Pin-to-Pin Compatible with PulSAR ADCs

APPLICATIONS
Data Acquisition
Instrumentation
Digital Signal Processing
Spectrum Analysis
Medical Instruments
Battery-Powered Systems
Process Control

Compatible

FUNCTIONAL BLOCK DIAGRAM

AVDD AGND REF REFGND

IN+

IN–

PD

RESET

CALIBRATION CIRCUITRY

Low Cost CMOS ADC

AD7650

SWITCHED

CAP DAC

CLOCK

CONTROL LOGIC AND

CNVSTWARP IMPULSE

AD7650

DGNDDVDD

SERIAL

PORT

PARALLEL

INTERFACE

16

*

OVDD

OGND

SER/PAR

BUSY

DATA[15:0]

CS

RD

OB/2C

GENERAL DESCRIPTION

The AD7650 is a 16-bit, 570 kSPS, charge redistribution SAR,
analog-to-digital converter that operates from a single 5 V power
supply. The part contains a high-speed 16-bit sampling ADC,
an internal conversion clock, error correction circuits, and both
serial and parallel system interface ports.

It features a very high sampling rate mode (Warp) and, for
asynchronous conversion rate applications, a fast mode (Normal)
and, for low power applications, a reduced power mode (Impulse)
where the power is scaled with the throughput.

It is fabricated using Analog Devices’ high-performance,

0.6 micron CMOS process and is available in a 48-lead LQFP
or in a tiny 48-lead Chip Scale package with operation specified
from –40°C to +85°C.

*Patent pending.
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

PRODUCT HIGHLIGHTS

1. Fast Throughput
The AD7650 is a 570 kSPS, charge redistribution, 16-bit
SAR ADC.

2. Single-Supply Operation
The AD7650 operates from a single 5 V supply. In impulse
mode, its power dissipation decreases with the throughput from
77 mW at 444 kSPS throughput to, for instance, only 21 µW
at a 100 SPS throughput. It consumes 7 µW maximum when
in power-down.

3. Serial or Parallel Interface
Versatile parallel or 2-wire serial interface arrangement com­patible with both 3 V or 5 V logic.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © Analog Devices, Inc., 2002

AD7650–SPECIFICATIONS

(–40ⴗC to +85ⴗC, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)

Parameter Condition Min Typ Max Unit

RESOLUTION 16 Bits

ANALOG INPUT

Voltage Range V
Operating Input Voltage V

Analog Input CMRR f

– V

IN+

IN–

IN+

V

IN–

= 10 kHz 62 dB

IN

0V

REF

V
–0.1 +3 V
–0.1 +0.5 V

Input Current 570 kSPS Throughput 7 µA
Input Impedance See Analog Input Section

THROUGHPUT SPEED

Complete Cycle In Warp Mode 1.75 µs
Throughput Rate In Warp Mode 1 570 kSPS
Time Between Conversions In Warp Mode 1 ms
Complete Cycle In Normal Mode 2 µs
Throughput Rate In Normal Mode 0 500 kSPS
Complete Cycle In Impulse Mode 2.25 µs
Throughput Rate In Impulse Mode 0 444 kSPS

DC ACCURACY

Integral Linearity Error –6 +6 LSB
No Missing Codes 15 Bits
Transition Noise 0.7 LSB
Full-Scale Error
Unipolar Zero Error

2

2

REF = 2.5 V ± 0.12 % of FSR

± 5 ± 25 LSB

Power Supply Sensitivity AVDD = 5 V ± 5% ± 3 LSB

AC ACCURACY

Signal-to-Noise f

= 100 kHz 86 dB

IN

4

Spurious Free Dynamic Range fIN = 100 kHz 98 dB
Total Harmonic Distortion f

Signal-to-(Noise + Distortion) f

= 45 kHz –98 dB

IN

f

= 100 kHz –96 dB

IN

= 100 kHz 86 dB

IN

–60 dB Input, f

= 100 kHz 30 dB

IN

–3 dB Input Bandwidth 18 MHz

SAMPLING DYNAMICS

Aperture Delay 2 ns
Aperture Jitter 5 ps rms
Transient Response Full-Scale Step 250 ns

REFERENCE

External Reference Voltage Range
External Reference Current Drain

570 kSPS Throughput 115 µA

2.3 2.5 AVDD – 1.85 V

DIGITAL INPUTS

Logic Levels

V

IL

V

IH

I

IL

I

IH

–0.3 +0.8 V

2.0 OVDD + 0.3 V
–1 +1 µA
–1 +1 µA

DIGITAL OUTPUTS
Data Format Parallel or Serial 16-Bit

Pipeline Delay Conversion Results Available

Immediately after Completed Conversion

I

V

OL

V

OH

= 1.6 mA 0.4 V

SINK

I

= –500 µA OVDD – 0.6 V

SOURCE

POWER SUPPLIES

Specified Performance

AVDD 4.75 5 5.25 V
DVDD 4.75 5 5.25 V
OVDD 2.7 5.25 V

1

3

REV. 0

–2–

AD7650

AD7650

Parameter Condition Min Typ Max Unit

POWER SUPPLIES (continued)

Operating Current

AVDD 15.5 mA

6

DVDD

6

OVDD

Power Dissipation

TEMPERATURE RANGE

Specified Performance T

NOTES

1

LSB means Least Significant Bit. With the 0 V to 2.5 V input range, one LSB is 38.15 µV.

2

See Definition of Specifications section. These specifications do not include the error contribution from the external reference.

3

Tested in warp mode.

4

All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale unless otherwise specified.

5

In warp mode.

6

Tested in parallel reading mode.

7

In impulse mode.

8

With all digital inputs forced to OVDD or OGND respectively.

9

Contact factory for extended temperature range.

Specifications subject to change without notice.

5

570 kSPS Throughput

4.2 mA

6

570 kSPS Throughput
444 kSPS Throughput
100 SPS Throughput
In Power-Down Mode

9

to T

MIN

MAX

5

7

7

8

–40 +85 °C

100 µA

115 mW
77 mW
21 µW

7 µW

TIMING SPECIFICATIONS

(–40ⴗC to +85ⴗC, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)

Parameter Symbol Min Typ Max Unit

REFER TO FIGURES 8 AND 9

Convert Pulsewidth t
Time Between Conversions t

1

2

5ns

1.75/2/2.25 Note 1 µs

(Warp Mode/Normal Mode/Impulse Mode)

CNVST LOW to BUSY HIGH Delay t
BUSY HIGH All Modes Except in t

3

4

30 ns

1.5/1.75/2 µs
Master Serial Read After Convert Mode
(Warp Mode/Normal Mode/Impulse Mode)

Aperture Delay t
End of Conversion to BUSY LOW Delay t
Conversion Time t

5

6

7

10 ns

2ns

1.5/1.75/2 µs
(Warp Mode/Normal Mode/Impulse Mode)

Acquisition Time t
RESET Pulsewidth t

8

9

250 ns
10 ns

REFER TO FIGURES 10, 11 AND 12

(Parallel Interface Modes)
CNVST LOW to DATA Valid Delay t

10

1.5/1.75/2 µs
(Warp Mode/Normal Mode/Impulse Mode)

DATA Valid to BUSY LOW Delay t
Bus Access Request to DATA Valid t
Bus Relinquish Time t

REFER TO FIGURES 13 AND 14

(Master Serial Interface Modes)

CS LOW to SYNC Valid Delay t
CS LOW to Internal SCLK Valid Delay

2

2

CS LOW to SDOUT Delay t
CNVST LOW to SYNC Delay t

11

12

13

14

t

15

16

17

45 ns

40 ns

515ns

10 ns
10 ns
10 ns

25/275/525 ns

(Warp Mode/Normal Mode/Impulse Mode)

SYNC Asserted to SCLK First Edge Delay t
Internal SCLK Period t
Internal SCLK HIGH (INVSCLK Low)
Internal SCLK LOW (INVSCLK Low)

3

3

SDOUT Valid Setup Time t
SDOUT Valid Hold Time t

REV. 0

REV. 0

18

19

t

20

t

21

22

23

–3–

–3–

4ns
40 75 ns
30 ns

9.5 ns

4.5 ns
3ns

AD7650

TIMING SPECIFICATIONS

(continued)

Parameter Symbol Min Typ Max Unit

REFER TO FIGURES 13 AND 14 (continued)

SCLK Last Edge to SYNC Delay t

CS HIGH to SYNC HI-Z t
CS HIGH to Internal SCLK HI-Z t
CS HIGH to SDOUT HI-Z t

BUSY HIGH in Master Serial Read After Convert t

24

25

26

27

28

3

10 ns
10 ns
10 ns

2.75/3/3.25 µs

(Warp Mode/Normal Mode/Impulse Mode)

CNVST LOW to SYNC Asserted Delay t

29

1/1.25/1.5 µs

(Warp Mode/Normal Mode/Impulse Mode)

SYNC Deasserted to BUSY LOW Delay t

REFER TO FIGURES 15 AND 16

(Slave Serial Interface Modes)

2

External SCLK Setup Time t
External SCLK Active Edge to SDOUT Delay t
SDIN Setup Time t
SDIN Hold Time t
External SCLK Period t
External SCLK HIGH t
External SCLK LOW t

NOTES

1

In warp mode only, the maximum time between conversions is 1 ms; otherwise, there is no required maximum time.

2

In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C

3

If the polarity of SCLK is inverted, the timing references of SCLK are also inverted.

Specifications subject to change without notice.

30

31

32

33

34

35

36

37

5ns
316ns
5ns
5ns
25 ns
10 ns
10 ns

of 10 pF; otherwise, the load is 60 pF maximum.

L

50 ns

1.6mA

TO OUTPUT

PIN

*IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND
SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD

OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.

C

L

60pF*

C

L

500␮A

I

OL

1.4V

I

OH

Figure 1. Load Circuit for Digital Interface Timing,
SDOUT, SYNC, SCLK Outputs, C

= 10 pF

L

2V

0.8V

t

DELAY

2V

0.8V

t

DELAY

2V

0.8V

Figure 2. Voltage Reference Levels for Timing

–4–

REV. 0

AD7650

ABSOLUTE MAXIMUM RATINGS

Analog Inputs

2

IN+

, REF, IN–, REFGND . . . . . . . . . . . . AVDD + 0.3 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . to AGND – 0.3 V

Ground Voltage Differences

AGND, DGND, OGND . . . . . . . . . . . . . . . . . . . . ± 0.3 V

Supply Voltages

AVDD, DVDD, OVDD . . . . . . . . . . . . . . . . . . . . . . . 7 V

AVDD to DVDD,

AVDD to OVDD . . . . . . . . . . . . . ± 7 V

DVDD to OVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . ±7 V

Digital Inputs

Except the Data Bus D(7:4) . . . . –0.3 V to DVDD + 0.3 V

Data Bus Inputs D(7:4) . . . . . . . –0.3 V to OVDD + 0.3 V

Internal Power Dissipation

3

. . . . . . . . . . . . . . . . . . . 700 mW

1

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C

Storage Temperature Range . . . . . . . . . . . –65°C to +150°C

Lead Temperature Range

(Soldering 10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

2

See Analog Input section.

3

Specification is for device in free air:

48-Lead LQFP: θJA = 91°C/W, θJC = 30°C/W.
48-Lead LFCSP: θJC = 26°C/W.

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD7650AST –40°C to +85°C Quad Flatpack (LQFP) ST-48
AD7650ASTRL –40°C to +85°C Quad Flatpack (LQFP) ST-48
AD7650ACP
AD7650ACPRL
EVAL-AD7650CB
EVAL-CONTROL BRD2

NOTES

1

Future Product. Contact Factory for availability.

2

This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD2 for evaluation/demonstration purposes.

3

This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designator.

1

1

2

3

–40°C to +85°C Quad Flatpack (LFCSP) CP-48
–40°C to +85°C Quad Flatpack (LFCSP) CP-48

1

1

Evaluation Board
Controller Board

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7650 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

REV. 0

–5–

AD7650

PIN CONFIGURATION

48-Lead LQFP and 48-Lead LFSCP

(ST-48 and CP-48)

AGND

AV DD

NC

DGND

OB/2C
WARP

IMPULSE
SER/PAR

D0

D1

D2

D3

NC = NO CONNECT

48

1

2

3

4

5

6

7

8

9

10

11

12

13 14

NCNCNCNCNC

46

47

PIN 1
IDENTIFIER

15 16 17 18

D4/EXT/INT

D5/INVSYNC

IN+NCNCNCIN–

45 44 39 38 3743 42 41 40

AD7650

TOP VIEW

(Not to Scale)

19 20

DVD D

OVD D

OGND

D6/INVSCLK

D7/RDC/SDIN

21 22

DGND

D8/SDOUT

REFGND

23 24

D9/SCLK

D10/SYNC

REF

D11/RDERROR

36

35

34

33

32

31

30

29

28

27

26

25

AGND

CNVST

PD

RESET

CS
RD

DGND

BUSY

D15

D14

D13

D12

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Type Description

1 AGND P Analog Power Ground Pin

2 AVDD P Input Analog Power Pins. Nominally 5 V.

3, 40–42, NC No Connect
44–48

4 DGND DI Must be tied to the ground where DVDD is referred.

5 OB/2C DI Straight Binary/Binary Two’s Complement. When OB/2C is HIGH, the digital output is

straight binary; when LOW, the MSB is inverted resulting in a two’s complement output from
its internal shift register.

6 WARP DI Mode Selection. When HIGH and IMPULSE LOW, this input selects the fastest mode, the

maximum throughput is achievable, and a minimum conversion rate must be applied in order
to guarantee full specified accuracy. When LOW, full accuracy is maintained independent of
the minimum conversion rate.

7 IMPULSE DI Mode Selection. When HIGH and WARP LOW, this input selects a reduced power mode.

In this mode, the power dissipation is approximately proportional to the sampling rate.

8 SER/PAR DI Serial/Parallel Selection Input. When LOW, the parallel port is selected; when HIGH, the

serial interface mode is selected and some bits of the DATA bus are used as a serial port.

9–12 DATA[0:3] DO Bit 0 to Bit 3 of the Parallel Port Data Output Bus. These pins are always outputs, regardless

of the state of SER/PAR.

13 DATA[4] DI/O When SER/PAR is LOW, this output is used as Bit 4 of the Parallel Port Data Output Bus.

or EXT/INT When SER/PAR is HIGH, this input, part of the serial port, is used as a digital select input for

choosing the internal or an external data clock. With EXT/INT tied LOW, the internal clock
is selected on SCLK output. With EXT/INT set to a logic HIGH, output data is synchronized
to an external clock signal connected to the SCLK input.

14 DATA[5] DI/O When SER/PAR is LOW, this output is used as Bit 5 of the Parallel Port Data Output Bus.

or INVSYNC When SER/PAR is HIGH, this input, part of the serial port, is used to select the active state of

the SYNC signal. It is active in both master and slave mode. When LOW, SYNC is active
HIGH. When HIGH, SYNC is active LOW.

15 DATA[6] DI/O When SER/PAR is LOW, this output is used as Bit 6 of the Parallel Port Data Output Bus.

or INVSCLK When SER/PAR is HIGH, this input, part of the serial port, is used to invert the SCLK signal.

It is active in both master and slave mode.

–6–

REV. 0