ANALOG DEVICES AD7643 Service Manual

www.BDTIC.com/ADI

18-Bit, 1.25 MSPS PulSAR® ADC

FEATURES

Throughput: 1.25 MSPS INL: ±1.5 LSB typical, ±3 LSB maximum (±11 ppm of full scale) 18-bit resolution with no missing codes Dynamic range: 95 dB typical SINAD: 93.5 dB typical @ 20 kHz (V THD: −113 dB typical @ 20 kHz (V

2.048 V internal reference: typical drift 8 ppm/°C; TEMP output Differential input range: ±V

REF

No pipeline delay (SAR architecture) Parallel (18-, 16-, or 8-bit bus) and serial 5 V/3.3 V/2.5 V interface SPI®/QSPI™/MICROWIRE™/DSP compatible Single 2.5 V supply operation Power dissipation

65 mW typical @ 1.25 MSPS with internal REF

2 μW in power-down mode Pb-free, 48-lead LQFP and 48-lead LFCSP_VQ Pin compatible with the AD7641 and other PulSAR ADC’s

APPLICATIONS

Medical instruments High speed data acquisition/high dynamic data acquisition Digital signal processing Spectrum analysis Instrumentation Communications AT E

GENERAL DESCRIPTION

The AD7643 is an 18-bit, 1.25 MSPS, charge redistribution SAR, fully differential, analog-to-digital converter (ADC) that operates from a single 2.5 V power supply. The part contains a high speed, 18-bit sampling ADC, an internal conversion clock, an internal reference (and buffer), error correction circuits, and both serial and parallel system interface ports. The part has no latency and can be used in asynchronous rate applications. The AD7643 is hardware factory calibrated and tested to ensure ac parameters, such as signal-to-noise ratio (SNR), in addition to the more traditional dc parameters of gain, offset, and linearity. The AD7643 is only available in Pb-free packages with operation specified from −40°C to +85°C.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

REF

(V

up to 2.5 V)

REF

= 2.5 V)

AD7643

FUNCTIONAL BLOCK DIAGRAM

TEMP

REFBUFIN

AGND

AVD D

PDREF

PDBUF

RESET

IN+

IN–

PD

REF

CONTROL L OGI C AND

CALIBRATIO N CIRCUITRY

Table 1. PulSAR 48-Lead Selection

Type/kSPS

Pseudo Differential

True Bipolar

True Differential

18-Bit Multichannel/

Simultaneous AD7654 AD7655

PRODUCT HIGHLIGHTS

1. Fast Throughput.

The AD7643 is a 1.25 MSPS, charge redistribution,

it SAR ADC.

18-b

2. Su

perior Linearity.

The AD7643 has no missing 18-bit code.

3. Inter

4. S

5. S

nal Reference. The AD7643 has a 2.048 V internal reference with a typical drift of ±8 ppm/°C and an on-chip TEMP sensor.

ingle-Supply Operation.

The AD7643 operates from a 2.5 V single supply.

erial or Parallel Interface. Versatile parallel (18-, 16-, or 8-bit bus) or 2-wire serial interface arrangement compatible with 2.5 V, 3.3 V, or 5 V logic.

REF REFGND

AD7643

REF AMP

SWITCHED

CAP DAC

CNVST

100 to 250

AD7651, AD7660, AD7661

CLOCK

Figure 1.

500 to 570

AD7650, AD7652, AD7664,

SERIAL

PARALLEL

INTERFACE

650 to 1000 >1000

AD7653, AD7667

AD7666

AD7610, AD7663

AD7665

AD7612, AD7671

AD7675 AD7676 AD7677

AD7631, AD7678

AD7679

AD7634, AD7674

PORT

DGNDDVDD

18

OVDD

OGND

D[17:0]

MODE0

MODE1

BUSY

RD

CS

D0/OB/2C

AD7621,

AD7622,

AD7623 AD7641,

AD7643

06024-001

AD7643

www.BDTIC.com/ADI

REVISION HISTORY

4/06—Revision 0: Initial Version

Ordering Guide .......................................................................... 28

Rev. 0 | Page 2 of 28

AD7643

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SPECIFICATIONS

AVDD = DVDD = 2.5 V; OVDD = 2.3 V to 3.6 V; V

Table 2.

Parameter Conditions Min Typ Max Unit

RESOLUTION 18 Bits ANALOG INPUT

Voltage Range V Operating Input Voltage V

IN+

Analog Input CMRR fIN = 100 kHz 58 dB Input Current 1.25 MSPS throughput 2.5 μA Input Impedance

2

THROUGHPUT SPEED

Complete Cycle 800 ns Throughput Rate 1.25 MSPS

DC ACCURACY

Integral Linearity Error

3

−3 ±1.5 +3 LSB No Missing Codes 18 Bits Differential Linearity Error −1 +1.25 LSB Transition Noise V V Zero Error, T

MIN

to T

MAX

5

REF

−16 +16 LSB Zero Error Temperature Drift ±1 ppm/°C Gain Error, T

MIN

to T

MAX

5

−22 +22 LSB Gain Error Temperature Drift ±1 ppm/°C Power Supply Sensitivity AVDD = 2.5 V ± 5% ±16 LSB

AC ACCURACY

Dynamic Range V

REF

Signal-to-Noise fIN = 1 kHz, V f f f

= 20 kHz, V

IN

= 20 kHz, V

IN

= 100 kHz, V

IN

Spurious-Free Dynamic Range fIN = 1 kHz, V f f f

= 20 kHz, V

IN

= 20 kHz, V

IN

= 100 kHz, V

IN

Total Harmonic Distortion fIN = 1 kHz, V f f f

= 20 kHz, V

IN

= 20 kHz, V

IN

= 100 kHz, V

IN

Signal-to-(Noise + Distortion) fIN = 1 kHz, V f f f

= 20 kHz, V

IN

= 20 kHz, V

IN

= 100 kHz, V

IN

−3 dB Input Bandwidth 50 MHz

SAMPLING DYNAMICS

Aperture Delay 1 ns Aperture Jitter 5 ps rms Transient Response Full-scale step 250 ns

INTERNAL REFERENCE PDREF = PDBUF = low

Output Voltage REF @ 25°C 2.038 2.048 2.058 V Temperature Drift −40°C to +85°C ±8 ppm/°C Line Regulation AVDD = 2.5 V ± 5% ±15 ppm/V

= 2.5 V; all specifications T

REF

− V

IN−

, V

to AGND −0.1 AVDD

IN−

MIN

−V

to T

, unless otherwise noted.

MAX

REF

+V

REF

1

V

= 2.5 V 1.7 LSB = 2.048 V 2.0 LSB

= 2.5 V 95 dB

= 2.5 V 93.5 dB

REF

= 2.5 V 93.5 dB

REF

= 2.048 V 92 dB

REF

= 2.5 V 93 dB

REF

= 2.5 V 118 dB

REF

= 2.5 V 114 dB

REF

= 2.048 V 111 dB

REF

= 2.5 V 108 dB

REF

= 2.5 V −114 dB

REF

= 2.5 V −113 dB

REF

= 2.048 V −109 dB

REF

= 2.5 V −105 dB

REF

= 2.5 V 93.5 dB

REF

= 2.5 V 93.5 dB

REF

= 2.048 V 91.8 dB

REF

= 2.5 V 92.5 dB

REF

4

6

Rev. 0 | Page 3 of 28

AD7643

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Parameter Conditions Min Typ Max Unit

Turn-On Settling Time C REFBUFIN Output Voltage REFBUFIN @ 25°C 1.19 V REFBUFIN Output Resistance 6.33 kΩ

EXTERNAL REFERENCE PDREF = PDBUF = high

Voltage Range REF 1.8 2.5 AVDD + 0.1 V Current Drain 1.25 MSPS throughput 100 μA

REFERENCE BUFFER PDREF = high, PDBUF = low

REFBUFIN Input Voltage Range REF = 2.048 V typical 1.05 1.2 1.30 V REFBUFIN Input Current REFBUFIN = 1.2 V 1 nA

TEMPERATURE PIN

Voltage Output @ 25°C 278 mV Temperature Sensitivity 1 mV/°C Output Resistance 4.7 kΩ

DIGITAL INPUTS

Logic Levels

V

IL

V

IH

I

IL

I

IH

DIGITAL OUTPUTS

Data Format Pipeline Delay

V

OL

V

OH

7

8

POWER SUPPLIES

Specified Performance

AVDD 2.37 2.5 2.63 V DVDD 2.37 2.5 2.63 V OVDD 2.30

Operating Current

11

AVD D

10

DVDD 1.5 mA

12

OVDD

Power Dissipation

10, 11

With Internal Reference 1.25 MSPS throughput 65 80 mW With External Reference 1.25 MSPS throughput 60 75 mW

In Power-Down Mode

TEMPERATURE RANGE

12

13

Specified Performance T

1

When using an external reference. With the internal reference, the input range is −0.1 V to V

2

See Analog Inputs section.

3

Linearity is tested using endpoints, not best fit.

4

LSB means least significant bit. With the ±2.048 V input range, 1 LSB is 15.63 μV.

5

See Voltage Reference Input section. These specifications do not include the error contribution from the external reference.

6

All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified.

7

Parallel or serial 18-bit.

8

Conversion results are available immediately after completed conversion.

9

See the Absolute Maximum Ratings section.

10

Tested in parallel reading mode.

11

With internal reference, PDREF and PDBUF are low; with external reference, PDREF and PDBUF are high.

12

With all digital inputs forced to OVDD.

13

Consult sales for extended temperature range.

= 10 μF 5 ms

REF

−0.3 +0.6 V

1.7 5.25 V

−1 +1 μA

I

= 500 μA 0.4 V

SINK

I

= −500 μA OVDD − 0.3 V

SOURCE

9

3.6 V

1.25 MSPS throughput With internal reference 24 mA

0.5 mA

PD = high 2 μW

MIN

to T

MAX

−40 +85 °C

.

REF

Rev. 0 | Page 4 of 28

AD7643

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TIMING SPECIFICATIONS

AVDD = DVDD = 2.5 V; OVDD = 2.3 V to 3.6 V; V

Table 3.

Parameter Symbol Min Typ Max Unit

CONVERSION AND RESET (Refer to Figure 30 and Figure 31)

Convert Pulse Width t Time Between Conversions t CNVST

Low to BUSY High Delay BUSY High All Modes (Except Master Serial Read After Convert) t Aperture Delay t End of Conversion to BUSY Low Delay t Conversion Time t Acquisition Time t RESET Pulse Width t RESET Low to BUSY High Delay BUSY High Time from RESET Low

2

PARALLEL INTERFACE MODES (Refer to Figure 32 to Figure 35 )

CNVST

Low to Data Valid Delay Data Valid to BUSY Low Delay t Bus Access Request to Data Valid t Bus Relinquish Time t

MASTER SERIAL INTERFACE MODES3 (Refer to Figure 36 and Figure 37)

CS

Low to SYNC Valid Delay

CS

Low to Internal SCLK Valid Delay

CS

Low to SDOUT Delay

CNVST

Low to SYNC Delay

3

SYNC Asserted to SCLK First Edge Delay t Internal SCLK Period Internal SCLK High Internal SCLK Low SDOUT Valid Setup Time SDOUT Valid Hold Time SCLK Last Edge to SYNC Delay CS

High to SYNC Hi-Z

CS

High to Internal SCLK Hi-Z

CS

High to SDOUT Hi-Z

4

BUSY High in Master Serial Read After Convert CNVST

Low to SYNC Asserted Delay SYNC Deasserted to BUSY Low Delay t

SLAVE SERIAL INTERFACE MODES (Refer to Figure 39 and Figure 40)

External SCLK Set-Up Time t External SCLK Active Edge to SDOUT Delay t SDIN Set-Up Time t SDIN Hold Time t External SCLK Period t External SCLK High t External SCLK Low t

1

See the Conversion Control section.

2

See the Digital Interface section and the RESET section.

3

In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.

4

In serial master read during convert mode. See Table 4 for serial master read after convert mode timing specifications.

= 2.5 V; all specifications T

REF

4

MIN

to T

, unless otherwise noted.

MAX

1

2

t

3

4

5

6

7

8

9

t

38

t

39

t

10

11

12

13

t

14

t

15

t

16

t

17

18

t

19

t

20

t

21

t

22

t

23

t

24

t

25

t

26

t

27

t

28

t

29

30

31

32

33

34

35

36

37

15 70 800 ns 23 ns

550 ns 1 ns 10 ns 550 ns 250 ns 15 ns 10 ns 500 ns

550 ns 2 ns

20 ns 2 15 ns

10 ns 10 ns 10 ns 135 ns 2 ns

8 20 ns 2 ns 2 ns 1 ns 0 ns 0 ns 10 ns

10 ns 10 ns See Table 4 ns

508 ns 13 ns

5 ns 1 8 ns 5 ns 5 ns

12.5 ns 5 ns 5 ns

1

ns

Rev. 0 | Page 5 of 28

AD7643

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Table 4. Serial Clock Timings in Master Read After Convert Mode

DIVSCLK[1] 0 0 1 1 DIVSCLK[0] Symbol 0 1 0 1 Unit

SYNC to SCLK First Edge Delay Minimum t Internal SCLK Period Minimum t Internal SCLK Period Maximum t Internal SCLK High Minimum t Internal SCLK Low Minimum t SDOUT Valid Setup Time Minimum t SDOUT Valid Hold Time Minimum t SCLK Last Edge to SYNC Delay Minimum t BUSY High Width Maximum t

18

19

20

21

22

23

24

28

1 3 3 3 ns 8 16 32 64 ns 20 40 70 135 ns 2 8 16 32 ns 2 8 16 32 ns 1 5 5 5 ns 0 0.5 10 30 ns 0 0.5 9 26 ns

0.84 1.14 1.72 2.88 μs

500µA I

OL

TO OUTPUT

C

L

50pF

500µA I

NOTE IN SERIAL INT ERFACE MODES, THE S YNC, SCLK, AND SDOUT TI MING ARE DEFINED WIT H A MAXIMUM LOAD

OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.

C

L

Figure 2. Load Circuit for Di

SDOUT, SYNC, and SCLK Outputs, C

1.4V

OH

gital Interface Timing,

= 10 pF

L

0.8V

t

DELAY

2V

0.8V

6024-002

Figure 3. Voltage Reference Levels for Timing

2V

t

DELAY

2V

0.8V

6024-003

Rev. 0 | Page 6 of 28

AD7643

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ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Rating

Analog Inputs/Outputs

IN+1, IN−, REF, REFBUFIN, TEMP,

INGND, REFGND to AGND

Ground Voltage Differences

AGND, DGND, OGND ±0.3 V

Supply Voltages

AVDD, DVDD −0.3 V to +2.7 V OVDD −0.3 V to +3.8 V AVDD to DVDD ±2.8 V AVDD, DVDD to OVDD −3.8 V to +2.8 V

Digital Inputs −0.3 V to +5.5 V PDREF, PDBUF Internal Power Dissipation Internal Power Dissipation Junction Temperature 125°C Storage Temperature Range –65°C to +125°C

1

See Analog Inputs section.

2

See Voltage Reference Input section.

3

Specification is for the device in free air:

48-Lead LQFP; θJA = 91°C/W, θJC = 30°C/W.

4

Specification is for the device in free air:

48-Lead LFCSP; θJA = 26°C/W.

2

3

4

AVDD + 0.3 V to AGND − 0.3 V

±20 mA 700 mW

2.5 W

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. 0 | Page 7 of 28

AD7643

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PDBUF

PDREF

REFBUFIN

TEMP

AVD D

IN+

AGND

AGNDNCIN–

REFGND

48 47 46 45 44 39 38 3743 42 41 40

1

AGND

AVD D

MODE0

MODE1

D0/OB/ 2C

DGND

D1/A0

D2/A1

D3

D4/DIVSCLK[0] D5/DIVSCLK[1]

NC = NO CONNECT

PIN 1 IDENTIFIER

2

3

4

5

6

7

8

9

10

11

12

13 14 15 16 17 18 19 20 21 22 23 24

D6/EXT/INT

D8/INVSCLK

D7/INVSYNC

AD7643

TOP VIEW

(Not to Scale)

DVDD

OVDD

OGND

D9/RDC/SDIN

DGND

Figure 4. Pin Configuration

Table 6. Pin Function Descriptions

Pin No.

1, 36,

Mnemonic Type

AGND P Analog Power Ground Pin.

1

Description

41, 42 2, 44 AVDD P Input Analog Power Pins. Nominally 2.5 V. 3, 4 MODE[0:1] DI

Data Output Interface Mode Selection.

Interface MODE# MODE1 MODE0

0 0 0 1 0 1 2 1 0 3 1 1 5

D0/OB/2C

DI/O

When MODE[1:0] = 0 (18-bit interface mode), this pin is Bit 0 of the parallel port data output bus and the data coding is straight binary. In all other modes, this pin allows the choice of straight

2C

binary/twos complement. When OB/

is high, the digital output is straight binary; when low,

the MSB is inverted resulting in a twos complement output from its internal shift register. 6, 7 DGND P Connect to Digital Ground. 8 D1/A0 DI/O

When MODE[1:0] = 0, this pin is Bit 1 of the parallel port data output bus. In all other modes, this

input pin controls the form in which data is output as shown in Tabl e 7. 9 D2/A1 DI/O When MODE[1:0] = 0, this pin is Bit 2 of the par

When MODE[1:0] = 1 or 2, this input pin controls the form in which data is output as shown in Table 7. 10 D3 DO

When MODE[1:0] = 0, 1, or 2, this output is used as Bit 3 of the parallel port data output bus.

This pin is always an output, regardless of the interface mode. 11, 12 D[4:5] DI/O or DIVSCLK[0:1]

When MODE[1:0] = 0, 1, or 2, these pins are Bit 4 and Bit 5 of the parallel port data output bus.

When MODE[1:0] = 3 (serial mode), serial clock division selection. When using serial master read

after convert mode (EXT/INT

= low, RDC/SDIN = low), these inputs can be used to slow down the

internally generated serial clock that clocks the data output. In other serial modes, these pins are

high impedance outputs. 13 D6 DI/O When MODE[1:0] = 0, 1, or 2, this output is used as Bit 6 of the parallel port data output bus.

or EXT/INT

When MODE[1:0] = 3 (serial mode), serial clock source select. This input is used to select the

ternally generated (master) or external (slave) serial data clock.

in

When EXT/INT

= low, master mode. The internal serial clock is selected on SCLK output. = high, slave mode. The output data is synchronized to an external clock signal,

gated by CS, connected to the SCLK input.

REF

36

AGND

CNVST

35

PD

34

33

RESET

32

CS

31

RD

30

DGND

29

BUSY

28

D17

27

D16

26

D15

25

D14

D11/SCLK

D12/SYNC

D10/SDOUT

D13/RDERROR

06024-004

allel port data output bus.

Description

18-bit interface 16-bit interface 8-bit (byte) interface Serial interface

Rev. 0 | Page 8 of 28

AD7643

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Pin No. Mnemonic Type

14 D7 DI/O When MODE[1:0] = 0, 1, or 2, this output is used as Bit 7 of the parallel port data output bus. or INVSYNC

15 D8 DI/O When MODE[1:0] = 0, 1, or 2, this output is used as Bit 8 of the parallel port data output bus. or INVSCLK

16 D9 DI/O When MODE[1:0] = 0, 1, or 2, this output is used as bit 9 of the parallel port data output bus. or RDC

or SDIN

17 OGND P Input/Output Interface Digital Power Ground. 18 OVDD P

19 DVDD P Digital Power. Nominally at 2.5 V. 20 DGND P Digital Power Ground. 21 D10 DO When MODE[1:0] = 0, 1, or 2, this output is used as Bit 10 of the parallel port data output bus. or SDOUT

22 D11 DI/O When MODE[1:0] = 0, 1, or 2, this output is used as Bit 11 of the parallel port data output bus. or SCLK

23 D12 DO When MODE[1:0] = 0, 1, or 2, this output is used as Bit 12 of the parallel port data output bus. or SYNC

24 D13 DO When MODE[1:0] = 0, 1, or 2, this output is used as Bit 13 of the parallel port data output bus. or RDERROR

25 to 28

29 BUSY DO

30 DGND P Digital Power Ground.

D[14:17] DO

1

Description

When MODE[1:0] = 3 (serial mode), invert sync selec input is used to select the active state of the SYNC signal. When INVSYNC = low, SYNC is active high.

When INVSYNC = high, SYNC is active low.

When MODE[1:0] = 3 (serial mode), invert SCLK select. I invert the SCLK signal.

When MODE[1:0] = 3 (serial mode), read during c (EXT/INT

When RDC = high, the previous conversion result is output on SDOUT during conversion and the per

When RDC = low (read after convert), the current result can be output on SDOUT only when the c

When MODE[1:0] = 3 (serial mode), serial data in. SDIN could be used as a data input to daisy-chain the conversion results from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on SDOUT with a delay of 18 SCLK periods after the initiation of the read sequence.

Input/Output Interface Digital Power. Nominally at the same supply as the supply of the host in

When MODE[1:0] = 3 (serial mode), serial da data output synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7643 provides the conversion result, MSB first, from its internal shift register. The data format is determined by the logic level of OB/2C

In master mode, EXT/INT In slave mode, EXT/INT

When MODE[1:0] = 3 (serial mode), serial clock. In all serial modes, this pin is used as the serial da where the data SDOUT is updated depends on the logic state of the INVSCLK pin.

When MODE[1:0] = 3 (serial mode), frame synchr this output is used as a digital output frame synchronization for use with the internal data clock.

When a read sequence is initiated and INVSYNC = low, SYNC is driven high and remains high while SDOUT output is valid.

When a read sequence is initiated and INVSYNC = high, SYNC is driven low and remains low while SDOUT output is valid.

When MODE[1:0] = 3 (serial mode), read error. In serial slave mode (EXT/INT is used as an incomplete read error flag. If a data read is started and not completed when the

current conversion is complete, the current data is lost and RDERROR is pulsed high. Bit 14 to Bit 17 of the Parallel Port Data Output Bus.

the interface mode. Busy Output. Transitions high when a conversion is started and remains high until the conversion

is c used as a data-ready clock signal.

= low), RDC is used to select the read mode.

iod of SCLK changes (see the Master Serial Interface section).

onversion is complete.

terface (2.5 V or 3 V).

ta output. In serial mode, this pin is used as the serial

.

= low. SDOUT is valid on both edges of SCLK.

= high: When INVSCLK = low, SDOUT is updated on SCLK rising ed When INVSCLK = high, SDOUT is updated on SCLK falling ed

ta clock input or output, depending upon the logic state of the EXT/INT

omplete and the data is latched into the on-chip shift register. The falling edge of BUSY can be

t. In serial master mode (EXT/INT

n all serial modes, this input is used to

onvert. When using serial master mode

When using serial slave mode (EXT/INT

ge and valid on the next falling edge.

ge and valid on the next rising edge.

pin. The active edge

onization. In serial master mode (EXT/INT

= high), this output

These pins are always outputs, regardless of

= low), this

= high),

= low),

Rev. 0 | Page 9 of 28

ANALOG DEVICES AD7643 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

TIMING SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS