Analog Devices AD7641 pre Datasheet

18-Bit, 2 MSPS SAR ADC

Preliminary Technical Data

FEATURES

18-bit resolution with no missing codes

2.5V internal low drift refernce
Throughput:

2 MSPS (Warp mode)

1.5 MSPS (Normal mode)
INL: ±2 LSB typical
S/(N+D): 93 dB typical @ 100 kHz ( V
THD: −100 dB typical @ 100 kHz
Differential input range: ±V

REF

(V
No pipeline delay ( SAR architecture )
Parallel (18-, 16-, or 8-bit bus)
Serial 5 V/3.3 V/2.5 V interface
SPI®/QSPI™/MICROWIRE™/DSP compatible
On-board low drift reference with buffer and

temperature sensor
Single 2.5 V supply operation
Power dissipation: 100 mW typical @ 2 MSPS
Power-down mode
48-LQFP and LFCSP packages
Speed upgrade of the AD7674
Pin-to-pin compatible with the AD7621

APPLICATIONS

Medical instruments
High dynamic data acquisition
Instrumentation
Spectrum analysis
ATE

GENERAL DESCRIPTION

The AD7641 is a 18-bit, 2 MSPS, charge redistribution SAR,
fully differential analog-to-digital converter that operates from
a single 2.5 V power supply. The part contains a high-speed 18­bit sampling ADC, an internal conversion clock, an internal
reference buffer, error correction circuits, and both serial and
parallel system interface ports. It features a very high sampling
rate mode (Warp) and a fast mode (Normal) for asynchronous
conversion rate applications. The AD7641 is hardware factory
calibrated and comprehensively tested to ensure ac parameters
such as signal-to-noise ratio (SNR) and total harmonic
distortion (THD) in addition to the more traditional dc
parameters of gain, offset and linearity. Operation is specified
from −40°C to +85°C.

Rev. Pr E

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Anal og Devices. Trademarks and
registered trademarks are the property of their respective owners.

= 2.5 V )

REF

up to 2.5 V)

REF

AD7641

FUNCTIONAL BLOCK DIAGRAM

REF

SWITCHED

CAP DAC

REFGND

AD7641

CLOCK

CNVST

Figure 1.

AD7650/52
AD7664/66

SERIAL

PORT

PARALLEL

INTERFACE

kSPS

800 to
1000 >1000

AD7653
AD7667

AD7655

TEMP

AGND

AVDD

REFBUFIN

IN+

PDREF

PDBUF

RESET

IN-

PD

REF

CONTROL LOGIC AND

CALIBRATION CIRCUITRY

WARP IMPULSE

Table 1. PulSAR Selection

Type

Pseudo
Differential

True Bipolar AD7663 AD7665 AD7671
True Differential AD7675 AD7676 AD7677 AD7621
18 Bit AD7678 AD7679 AD7674 AD7641
Multichannel/

Simultaneous

100 to 250 500 to 570

AD7651
AD7660/61

AD7654

PRODUCT HIGHLIGHTS

1. High resolution and Fast Throughput.

The AD7641 is a 2 MSPS, charge redistribution, 18-bit
SAR ADC (no latency).

2. Superior INL.

The AD7641 has a maximum integral nonlinearity of
2 LSB with no missing 18-bit codes.

3. Single-Supply Operation.

Operates from a single 2.5 V supply. Also features a
power-down mode.

4. Serial or Parallel Interface.

Versatile parallel (18-, 16-, or 8-bit bus) or 2-wire
serial interface arrangement compatible with either

2.5 V, 3.3 V, or 5 V logic.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

DGNDDVDD

OVDD

OGND

18

D[17:0]

BUSY

RD

CS

MODE0

MODE1

AD7641 Preliminary Technical Data

TABLE OF CONTENTS

Specifications..................................................................................... 3

Temperature Sensor................................................................... 15

Timing Specifications....................................................................... 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configurations and Function Descriptions........................... 7

Terminology ....................................................................................10

Circuit Information........................................................................ 11

Converter Operation...................................................................... 12

Modes of Operation................................................................... 12

Transfer Functions......................................................................12

Typical Connection Diagram........................................................ 14

Analog Inputs..............................................................................14

Driver Amplifier Choice............................................................ 14

Single to Differential Driver...................................................... 15

Voltage Reference ....................................................................... 15

Power Supply............................................................................... 16

Conversion Control ................................................................... 16

Interfaces.......................................................................................... 17

Digital Interface.......................................................................... 17

Parallel Interface......................................................................... 17

Serial Interface............................................................................ 18

Master Serial Interface............................................................... 18

Slave Serial Interface.................................................................. 18

Microprocessor Interfacing....................................................... 21

Application Hints ........................................................................... 22

Layout .......................................................................................... 22

Evaluating the AD7641 Performance ...................................... 22

Outline Dimensions....................................................................... 23

Ordering Guide .......................................................................... 24

Rev. Pr E | Page 2 of 24

Preliminary Technical Data AD7641

SPECIFICATIONS

Table 2. −40°C to +85°C, V

Parameter Conditions Min Typ Max Unit

RESOLUTION 18 Bits
ANALOG INPUT

Voltage Range V
Operating Input Voltage V
Analog Input CMRR fIN = 100 kHz 60 dB
Input Current 2 MSPS Throughput TBD µA
Input Impedance1 See Analog Inputs Section

THROUGHPUT SPEED

Complete Cycle In Warp Mode 500 ns
Throughput Rate In Warp Mode 0.001 2 MSPS
Time Between Conversions In Warp Mode 1 ms
Complete Cycle In Normal Mode 667 ns

Throughput Rate In Normal Mode 0 1.5 MSPS
DC ACCURACY
Integral Linearity Error –3 ± 2 +3 LSB2
Differential Linearity Error –1 LSB
No Missing Codes 18 Bits
Transition Noise V
Gain Error, T

MIN

to T

MAX

Gain Error Temperature Drift ±0.5 ppm/°C
Zero Error, T

MIN

to T

MAX

Zero Error Temperature Drift ±1.6 ppm/°C
Power Supply Sensitivity AVDD = 2.5V ± 5% ±5 LSB
AC ACCURACY
Signal-to-Noise f
V
V
Spurious Free Dynamic Range fIN= 100 kHz 100 dB
Total Harmonic Distortion fIN= 100 kHz –100 dB
Signal-to-(Noise+Distortion) fIN= 100 kHz, 93 dB
f

-3 dB Input Bandwidth 50 MHz
SAMPLING DYNAMICS
Aperture Delay 1 ns
Aperture Jitter 5 ps rms
Transient Response Full-Scale Step 160 ns
Overvoltage recovery 160 ns
REFERENCE
External Reference Voltage Range REF TBD 2.048 AVDD V
REF Current Drain 2 MSPS Throughput TBD µA
REF Voltage with reference buffer REFBUFIN=1.2V 2 2.048 2.1 V
Reference Buffer Input Voltage REFBUFIN TBD 1.2 TBD V

REFBUFIN Input Current –1 + 1 µA
INTERNAL REFERENCE
Internal Reference Voltage @ 25°C 1.197 1.2 1.203 V
Internal Reference Temp Drift – 40°C to +85°C 3 ppm/°C
REFBUFIN Line Regulation AVDD = 2.5V ± 5% ±15 ppm/V
REFBUFIN Output Resistance kΩ
Turn-on Settling Time 5 ms
Long-term Stability 1,000 Hours 100 ppm/1000hours

= AVDD, AVDD = DVDD = OVDD = 2.5 V, unless otherwise noted.

REF

– V

IN+

IN

to AGND

IN+, VIN

= AVDD 56 µV

3

±TBD % of FSR

REF

–V

+V

REF

REF

V

-0.1 AVDD V

3 ±TBD ±TBD LSB

= 100 kHz,

IN

=AVDD 93 dB4

REF

=2.048V 91.3 dB

REF

= 100 kHz, -60 dB Input 33 dB

IN

Rev. Pr E | Page 3 of 24

AD7641 Preliminary Technical Data

Parameter Conditions Min Typ Max Unit

Hysterisis 50 ppm
Temperature Pin Voltage Output @ 25°C 300 mV
Temperature Sensitivity 1 mV/°C
TEMP pin Output Resistance 4 kΩ
DIGITAL INPUTS
Logic Levels
VIL –0.3 +0.6 V
VIH +1.7 5.25 V
IIL –1 +1 µA
IIH –1 +1 µA
DIGITAL OUTPUTS
Data Format5
Pipeline Delay6
VOL I
VOH I
POWER SUPPLIES
Specified Performance
AVDD 2.37 2.5 2.63 V
DVDD 2.37 2.5 2.63 V
OVDD 2.3 3.6 V
Operating Current7 2 MSPS Throughput
AVDD 15 mA
DVDD8 4.5 mA
OVDD 130 µA
Power Dissipation7 PDBUF = HIGH @ 2 MSPS 100 mW
PDBUF = LOW @ 2 MSPS 108 mW

In Power-down mode PD = HIGH TBD µW
TEMPERATURE RANGE9
Specified Performance T

1

See analog Input section

2

LSB means Least Significant Bit. With the ±2.5 V input range, one LSB is 19.07 µV.

3

See Definition of Specifications section. These specifications do not include the error contribution from the external reference.

4

All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale unless otherwise specified.

5

Parallel or serial 18 bit..

6

Conversion results are available immediately after completed conversion.

7

In Warp mode.

8

Tested in parallel reading mode.

9

Contact factory for extended temperature range.

= 500 µA 0.4 V

SINK

= -500 µA OVDD – 0.3 V

SOURCE

to T

MIN

-40 +85 °C

MAX

Rev. Pr E | Page 4 of 24

Preliminary Technical Data AD7641

TIMING SPECIFICATIONS

Table 3. –40°C to +85°C, AVDD = DVDD = 2.5 V, OVDD = 2.3 V to 3.6 V, unless otherwise noted.

Parameter Symbol Min Typ Max Unit

Refer to Figure 13 and Figure 14
Convert Pulse Width t1 5 ns

500/667 Note 1 ns

t

Time Between Conversions (Warp Mode/Normal Mode)1

CNVST

LOW to BUSY HIGH Delay

BUSY HIGH All Modes Except in Master Serial Read After
Convert (Warp Mode/Normal Mode)

Aperture Delay t5 1 ns
End of Conversion to BUSY LOW Delay t6 10 ns
Conversion Time (Warp Mode/Normal Mode) t7 340/465 ns
Acquisition Time (Warp Mode/Normal Mode) t8 70/100 ns
RESET Pulsewidth t9 10 ns
Refer to Figure 15, Figure 16, and Figure 17 (Parallel Interface Modes)

CNVST

LOW to Data Valid Delay

(Warp Mode/Normal Mode)
Data Valid to BUSY LOW Delay t11 20 ns
Bus Access Request to Data Valid t12 40 ns
Bus Relinquish Time t13 2 15 ns
Refer to Figure 19 and Figure 20 (Master Serial Interface Modes) 2

CS LOW to SYNC Valid Delay
CS LOW to Internal SCLK Valid Delay
CS LOW to SDOUT Delay

CNVST

LOW to SYNC Delay

(Warp Mode/Normal Mode)
SYNC Asserted to SCLK First Edge Delay 3 t
Internal SCLK Period 3 t
Internal SCLK HIGH 3 t
Internal SCLK LOW 3 t
SDOUT Valid Setup Time t22 TBD ns
SDOUT Valid Hold Time t23 TBD ns
SCLK Last Edge to SYNC Delay 3 t

CS HIGH to SYNC HI-Z
CS HIGH to Internal SCLK HI-Z
CS HIGH to SDOUT HI-Z

BUSY HIGH in Master Serial Read after Convert3 t

CNVST

LOW to SYNC Asserted Delay

(Warp Mode/Normal Mode)
SYNC Deasserted to BUSY LOW Delay t30 TBD ns
Refer to Figure 21 and Figure 22 (Slave Serial Interface Modes)
External SCLK Setup Time t31 5 ns
External SCLK Active Edge to SDOUT Delay t32 2 7 ns
SDIN Setup Time t33 TBD ns
SDIN Hold Time t34 TBD ns
External SCLK Period t35 12.5 ns
External SCLK HIGH t36 5 ns
External SCLK LOW t37 5 ns

1

In warp mode only, the maximum time between conversions is 1ms; otherwise, there is no required maximum time.

2

In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.

3

In serial master read during convert mode.

2

t3

340/465 ns

t

4

30 ns

t10 340/465 ns

t14 TBD ns
t15 TBD ns
t16 TBD ns
t17 TBD

TBD ns

18

TBD TBD ns

19

TBD ns

20

TBD ns

21

TBD ns

24

t

TBD ns

25

t26 TBD ns
t

TBD ns

27

TBD ns

28

t29 TBD ns

Rev. Pr E | Page 5 of 24

AD7641 Preliminary Technical Data

ABSOLUTE MAXIMUM RATINGS

Table 4. AD7641 Stress Ratings1

Parameter Rating

Analog Inputs

IN+2, IN-2, REF, REFBUFIN,

AVDD + 0.3 V to AGND – 0.3 V

REFGND to AGND

Ground Voltage Differences

AGND, DGND, OGND ±0.3 V

Supply Voltages

AVDD, DVDD –0.3 V to +2.7 V
OVDD –0.3 V to +3.8 V

Digital Inputs –0.3 V to 5.5V
Internal Power Dissipation3 700 mW
Internal Power Dissipation4 2.5 W
Junction Temperature 150°C
Storage Temperature Range –65°C to +150°C
Lead Temperature Range

300°C

(Soldering 10 sec)

1

Stresses above those listed under Absolute Maximum Ratings may cause

permanent damage to the device. This is a stress rating only; functional
operation of the device at these or any other conditions above those
indicated in the operational section of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect device reliability

2

See Analog Inputs section.

3

Specification is for device in free air: 48-Lead LQFP: θJA = 91°C/W,

θJC = 30°C/W.

4

Specification is for device in free air: 48-Lead LFCSP: θJA = 26°C/W.

500␮A

TO OUTPUT

PIN

C

L

50pF*

500␮A

IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND

*

SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD
C

OF 10pF; OTHERWISE, THE LOAD IS 50pF MAXIMUM.

L

Figure 2. Load Circuit for Digital Interface Timing

SDOUT, SYNC, SCLK Outputs, C

0.8V

t

DELAY

2V

0.8V

Figure 3. Voltage Reference Levels for Timing

I

OL

1.4V

I

OH

=10 pF

L

2V

t

DELAY

2V

0.8V

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. Pr E | Page 6 of 24

Preliminary Technical Data AD7641

T

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

PDBUF

PDREF

REFBUFIN

TEMP

AVDD

IN+

AGND

AGNDNCIN-

REFGND

D11/SCLK

D10/SDOUT

REF

36

35

34

33

32

31

30

29

28

27

26

25

D12/SYNC

D13/RDERROR

AGND

CNVS

PD

RESET
CS

RD

DGND

BUSY

D17

D16

D15

D14

48

47 46 45 44 39 38 3743 42 41 40

1

AGND

AVDD

MODE0
MODE1

D0/OB/2C

WARP

NC

D1/A0

D2/A1

D4/DIVSCLK[0]
D5/DIVSCLK[1]

NC = NO CONNECT

PIN 1

2

IDENTIFIER

3

4

5

6

7

8

9

10

D3

11

12

13 14

D6/EXT/INT

(Not to Scale)

15 16 17 18

D8/INVSCLK

D7/INVSYNC

D9/RDC/SDIN

AD7641

TOP VIEW

19 20

OVDD

OGND

DVDD

Figure 4. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Type1 Description

1, 36, 41,

AGND P Analog power ground pin.

42
2, 44 AVDD P Input analog power pins. Nominally 2.5 V
7, 40 NC No Connect
3 MODE0 DI Data Output Interface mode Selection.
4 MODE1 DI Data Output Interface mode Selection:

Interface MODE # MODE0 MODE1 Description
0 0 0 18-bit Interface
1 0 1 16-bit Interface
2 1 0 Byte Interface
3 1 1 Serial Interface

5

D0/OB/

2C

DI/O

When MODE=0 (18-bit interface mode), this pin is Bit 0 of the parallel port data output bus and the
data coding is straight binary. In all other modes, this pin allows choice of Straight Binary/Binary

2C

Two’s Complement. When OB/

is HIGH, the digital output is straight binary; when LOW, the MSB is

inverted resulting in a two’s complement output from its internal shift register.

6 WARP DI

Conversion mode selection. When HIGH, this input selects the fastest mode, the maximum
throughput is achievable, and a minimum conversion rate must be applied in order to guarantee full
specified accuracy. When LOW, full accuracy is maintained independent of the minimum conversion
rate.

8 D1/A0 DI/O

When MODE=0 (18-bit interface mode), this pin is Bit 1 of the parallel port data output bus. In all other
modes, this input pin controls the form in which data is output as shown in Table 6.

9 D2/A1 DI/O

When MODE=0 or MODE=1 (18-bit or 16-bit interface mode), this pin is Bit 2 of the parallel port data
output bus. In all other modes, this input pin controls the form in which data is output as shown in
Table 6.

10 D3 DO

In all modes except MODE=3, this output is used as Bit 3 of the Parallel Port Data Output Bus. This pin
is always an output regardless of the interface mode.

11, 12

D[4:5] or
DIVSCLK[0:
1]

DI/O In all modes except MODE=3, these pins are Bit 4 and Bit 5 of the Parallel Port Data Output Bus.

In MODE=3 (serial mode), when EXT/

INT

convert, these inputs, part of the serial port, are used to slow down if desired the internal serial clock
clocks the data output. In other serial modes, these pins are not used.

21 22 23 24

DGND

is LOW, and RDC/SDIN is LOW, which serial master read after

Rev. Pr E | Page 7 of 24

AD7641 Preliminary Technical Data

Pin No. Mnemonic Type1 Description

13

14

15

16

17 OGND P Input/Output Interface Digital Power Ground.
18 OVDD P

19 DVDD P Digital Power. Nominally at 2.5 V.
20 DGND P Digital Power Ground.
21

22

23

24

25-28 D[14:17] DO

29 BUSY DO

30 DGND P Must be tied to digital ground.
31

32

D6 or

INT

EXT/

D7or
INVSYNC

D8 or
INVSCLK

D9 or
RDC/SDIN

D10 or
SDOUT

D11 or
SCLK

D12 or
SYNC

D13 or
RDERROR

RD
CS

DI/O In all modes except MODE=3, this output is used as Bit 6 of the Parallel Port Data Ouput Bus.

DI/O In all modes except MODE=3, this output is used as Bit 7 of the Parallel Port Data Output Bus.

DI/O In all modes except MODE=3, this output is used as Bit 8 of the Parallel Port Data Output Bus.

DI/O In all modes except MODE=3, this output is used as Bit 9 of the Parallel Port Data Output Bus.

DO In all modes except MODE=3, this output is used as Bit 10 of the Parallel Port Data Output Bus.

DI/O In all modes except MODE=3, this putput is used as the Bit 11 of the Parallel Port Data Output Bus.

DO In all modes except MODE=3, this output is used as the Bit 12 of the Parallel Port Data Output Bus.

DO In all modes except MODE=3, this output is used as the Bit 12 of the Parallel Port Data Output Bus.

DI
DI

When MODE=3 (serial mode), this input, part of the serial port, is used as a digital select input for
choosing the internal or an external data clock. With EXT/

INT

on SCLK output. With EXT/
signal connected to the SCLK input.

When MODE=3 (serial mode), this input, part of the serial port, is used to select the active state of the
SYNC signal. When LOW, SYNC is active HIGH. When HIGH, SYNC is active LOW.

When MODE=3 (serial mode), this input, part of the serial port, is used to invert the SCLK signal. It is
active in both master and slave mode.

When MODE=3 (serial mode), this input, part of the serial port, is used as either an external data input
or a read mode selection input depending on the state of EXT/

INT

When EXT/
from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on SDOUT
with a delay of 18 SCLK periods after the initiation of the read sequence.

When EXT/
output on SDOUT during conversion. When RDC/SDIN is LOW, the data can be output SDOUT only
when the conversion is complete.

Input/Output Interface Digital Power. Nominally at the same supply than the supply of the host
interface (2.5 V or 3 V).

When MODE=3 (serial mode), this output, part of the serial port, is used as a serial data output
synchronized to SCLK. Conversion results are stored in an on-chip shift register. The AD7641 provides
the conversion result, MSB first, from its internal shift register. The data format is determined by the

logical level of OB/
In serial mode, when EXT/
In serial mode, when EXT/

If INVSCLK is LOW, SDOUT is updated SCLK rising edge and valid on the next falling edge.
If INVSCLK is HIGH, SDOUT is updated on SCLK falling edge and valid on the next rising edge.

When MODE=3 (serial mode), this pin, part of the serial port, is used as a serial data clock input or
output, dependent upon the logic state of the EXT/
updated depends upon the logic state of the INVSCLK pin.

When MODE=3 (serial mode), this output, part of the serial port, is used as a digital output frame
synchronization for use with the internal data clock (EXT/
initiated and INVSYNC is LOW, SYNC is driven HIGH and remains HIGH while SDOUT output is valid.
When a read sequence is initiated and INVSYNC is HIGH, SYNC is driven LOW and remains LOW while
SDOUT output is valid.

In MODE=3 (serial mode) and when EXT/
incomplete read error flag. In slave mode, when a data read is started and not complete when the
following conversion is complete, the current data is lost and RDERROR is pulsed high.

Bit 14 to Bit 17 of the Parallel Port Data output bus. These pins are always outputs regardless of the
interface mode.

Busy Output. Transitions HIGH when a conversion is started, and remains HIGH until the conversion is
complete and the data is latched into the on-chip shift register.
The falling edge of BUSY could be used as a data ready clock signal.

Read Data. When
Chip Select. When

also used to gate the external clock.

is HIGH, RDC/SDIN could be used as a data input to daisy chain the conversion results

INT

is LOW, RDC/SDIN is used to select the read mode. When RDC/SDIN is HIGH, the data is

2C

.

CS

and RD are both LOW, the interface parallel or serial output bus is enabled.

CS

and RD are both LOW, the interface parallel or serial output bus is enabled. CS is

set to a logic HIGH, output data is synchronized to an external clock

INT

is LOW, SDOUT is valid on both edges of SCLK.

INT

is HIGH:

INT

is HIGH, this output, part of the serial port, is used as a

INT

tied LOW, the internal clock is selected

INT

.

INT

pin. The active edge where the data SDOUT is

INT

= Logic LOW). When a read sequence is

Rev. Pr E | Page 8 of 24