ANALOG DEVICES AD7641 Service Manual

18-Bit, 2 MSPS SAR ADC

FEATURES

Throughput

2 MSPS (wideband warp and warp mode)

1.5 MSPS (normal mode) INL: ±2 LSB typical, ±3 LSB max; ±8 ppm of full scale 18-bit resolution with no missing codes Dynamic range: 95.5 dB

REF

(V

= 2.5 V)

REF

= 2.5 V)

REF

up to 2.5 V)

REF

SNR: 93.5 dB typical @ 20 kHz (V THD: −112 dB typical @ 20 kHz (V

2.048 V internal reference: typ drift 10 ppm/°C; TEMP output Differential input range: ±V No pipeline delay (SAR architecture) Parallel (18-, 16-, or 8-bit bus) and

serial 5 V/3.3 V/2.5 V inter face SPI®/QSPI™/MICROWIRE™/DSP compatible Single 2.5 V supply operation Power dissipation

75 mW typical @ 2 MSPS with internal REF

2 μW in power-down mode Pb-free, 48-lead LQFP and 48-lead LFCSP_VQ Speed upgrade of the

AD7674, AD7678, AD7679

APPLICATIONS

Medical instruments High speed data acquisition/high dynamic data acquisition Digital signal processing Spectrum analysis Instrumentation Communications AT E

GENERAL DESCRIPTION

The AD7641 is an 18-bit, 2 MSPS, charge redistribution SAR, fully differential, analog-to-digital converter (ADC) that operates from a single 2.5 V power supply. The part contains a high speed, 18-bit sampling ADC, an internal conversion clock, an internal reference (and buffer), error correction circuits, and both serial and parallel system interface ports. It features two very high sampling rate modes (wideband warp and warp) and a fast mode (normal) for asynchronous rate applications. The AD7641 is hardware factory calibrated and tested to ensure ac parameters, such as signal-to-noise ratio (SNR), in addition to the more traditional dc parameters of gain, offset, and linearity. The AD7641 is available in Pb-free only packages with operation specified from −40°C to +85°C.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD7641

FUNCTIONAL BLOCK DIAGRAM

AGND

AVD D

IN+

IN–

PDREF

PDBUF

PD

RESET

TEMP

REFBUFIN

REF

CONTROL LOG IC AND

CALIBRATION CIRCUITRY

WAR P

REF AMP

SWITCHED

CAP DAC

NORMAL

REF REFGND

AD7641

INTERFACE

CLOCK

CNVST

Figure 1.

Table 1. PulSAR® Selection

Type/kSPS

Pseudo Differential

100 to 250

AD7651, AD7660, AD7661

500 to 570

AD7650, AD7652, AD7664, AD7666

True Bipolar

AD7610,

AD7665

AD7663

True

AD7675 AD7676 AD7677

Differential

18-Bit Multichannel/

AD7631, AD7678

AD7679

Simultaneous AD7654 AD7655

PRODUCT HIGHLIGHTS

1. Fast Throughput.

The AD7641 is a 2 MSPS, charge redistribution, 18-bit SAR ADC.

2. Superior Linearity.

The AD7641 has no missing 18-bit code.

3. Internal Reference.

The AD7641 has a 2.048 V internal reference with a typical drift of ±10 ppm/°C and an on

-chip TEMP sensor.

Single-Supply Operation. 4.

The AD7641 operates from a

5.

Serial or Parallel Interface. Versatile parallel (16- or 8-bit bus) or 2-wire serial interf arrangement compatible with 2.5 V, 3.3 V, or 5 V logic.

2.5 V single supply.

SERIAL

PORT

PARALLEL

650 to 1000

AD7653, AD7667

AD7612, AD7671

AD7634, AD7674

DGNDDVDD

18

OVDD

OGND

D[17:0]

MODE0

MODE1

BUSY

RD

CS

D0/OB/2C

04761-001

>1000

AD7621,

AD7622,

AD7623 AD7641,

AD7643

ace

AD7641

REVISION HISTORY

1/06—Revision 0: Initial Version

Outline Dimensions....................................................................... 28

Ordering Guide .......................................................................... 28

Rev. 0 | Page 2 of 28

AD7641

SPECIFICATIONS

AVDD = DVDD = 2.5 V; OVDD = 2.3 V to 3.6 V; V

Table 2.

Parameter Conditions Min Typ Max Unit

RESOLUTION 18 Bits ANALOG INPUT

Voltage Range V Operating Input Voltage V

IN+

Analog Input CMRR fIN = 100 kHz 58 dB Input Current 2 MSPS throughput 18 μA Input Impedance

2

THROUGHPUT SPEED

Complete Cycle Wideband warp, warp modes 500 ns Throughput Rate Wideband warp, warp modes 0.001 2 MSPS Time Between Conversions Wideband warp, warp modes 1 ms Complete Cycle Normal mode 667 ns Throughput Rate Normal mode 0 1.5 MSPS

DC ACCURACY

Integral Linearity Error Integral Linearity Error T

3

T

MIN

No Missing Codes 18 Bits Differential Linearity Error −1 +2 LSB Transition Noise V Transition Noise V Zero Error, T

MIN

to T

MAX

5

REF

−15 +15 LSB Zero Error Temperature Drift ±0.5 ppm/°C Gain Error, T

MIN

to T

MAX

5

−0.25 +0.25 % of FSR Gain Error Temperature Drift ±1 ppm/°C Power Supply Sensitivity AVDD = 2.5 V ± 5% ±16 LSB

AC ACCURACY

Dynamic Range V

REF

Signal-to-Noise fIN = 20 kHz, V f f

= 20 kHz, V

IN

= 100 kHz, V

IN

Spurious-Free Dynamic Range fIN = 20 kHz, V f f

= 20 kHz, V

IN

= 100 kHz, V

IN

Total Harmonic Distortion fIN = 20 kHz, V f f

= 20 kHz, V

IN

= 100 kHz, V

IN

Signal-to-(Noise + Distortion) fIN = 20 kHz, , V f f

= 20 kHz, V

IN

= 100 kHz, , V

IN

−3 dB Input Bandwidth 50 MHz

SAMPLING DYNAMICS

Aperture Delay 1 ns Aperture Jitter 5 ps rms Transient Response Full-scale step 115 ns

INTERNAL REFERENCE PDREF = PDBUF = low

Output Voltage REF @ 25°C 2.038 2.048 2.058 V Temperature Drift −40°C to +85°C ±10 ppm/°C Line Regulation AVDD = 2.5 V ± 5% ±15 ppm/V

= 2.5 V; all specifications T

REF

− V

−V

IN−

, V

to AGND −0.1 AVDD

IN−

to T

= −40°C to +70°C −3 ±2 +3 LSB

MAX

to T

= −40°C to +85°C −3.5 ±2 +3.5 LSB

MAX

MIN

to T

, unless otherwise noted.

MAX

+V

REF

V

REF

1

V

= 2.5 V 1.6 LSB = 2.048 V 2.0 LSB

= 2.5 V 95.5 dB

= 2.5 V 93.5 dB

REF

= 2.048 V 92 dB

REF

= 2.5 V 93 dB

REF

= 2.5 V 112 dB

REF

= 2.048 V 113 dB

REF

= 2.5 V 101 dB

REF

= 2.5 V −115 dB

REF

= 2.048 V −116 dB

REF

= 2.5 V −101 dB

REF

= 2.5 V 93.5 dB

REF

= 2.048 V 92 dB

REF

= 2.5 V 92.5 dB

REF

4

6

Rev. 0 | Page 3 of 28

AD7641

Parameter Conditions Min Typ Max Unit

Turn-On Settling Time C REFBUFIN Output Voltage REFBUFIN @ 25°C 1.19 V REFBUFIN Output Resistance 6.33 kΩ

EXTERNAL REFERENCE PDREF = PDBUF = high

Voltage Range REF 1.8 2.048 AVDD + 0.1 V Current Drain 2 MSPS throughput 180 μA

REFERENCE BUFFER PDREF = high, PDBUF = low

REFBUFIN Input Voltage Range REF = 2.048 V typ 1.05 1.2 1.30 V REFBUFIN Input Current REFBUFIN = 1.2 V 1 nA

TEMPERATURE PIN

Voltage Output @ 25°C 278 mV Temperature Sensitivity 1 mV/°C Output Resistance 4.7 kΩ

DIGITAL INPUTS

Logic Levels

VIL −0.3 +0.6 V VIH 1.7 5.25 V IIL −1 +1 μA IIH −1 +1 μA

DIGITAL OUTPUTS

Data Format Pipeline Delay

7

8

VOL I VOH I

POWER SUPPLIES

Specified Performance

AVDD 2.37 2.5 2.63 V DVDD 2.37 2.5 2.63 V OVDD 2.30

Operating Current

11

AVD D

10

DVDD 2.5 mA

12

OVDD

Power Dissipation

With Internal Reference Without Internal Reference

In Power-Down Mode

TEMPERATURE RANGE

11

10

12

13

Specified Performance T

1

When using an external reference. With the internal reference, the input range is −0.1 V to V

2

See Analog Inputs section.

3

Linearity is tested using endnotes, not best fit.

4

LSB means least significant bit. With the ±2.048 V input range, 1 LSB is 15.63 μV.

5

See Voltage Reference Input section. These specifications do not include the error contribution from the external reference.

6

All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified.

7

Parallel or serial 18-bit.

8

Conversion results are available immediately after completed conversion.

9

See the Absolute Maximum Ratings section.

10

In warp mode. Tested in parallel reading mode.

11

With internal reference, PDREF and PDBUF are low; without internal reference, PDREF and PDBUF are high.

12

With all digital inputs forced to OVDD.

13

Consult sales for extended temperature range.

= 10 μF 5 ms

REF

= 500 μA 0.4 V

SINK

= −500 μA OVDD − 0.3 V

SOURCE

9

3.6 V 2 MSPS throughput With internal reference 23 mA

0.5 mA

2 MSPS throughput 75 92 mW 2 MSPS throughput 68 85 mW PD = high 2 μW

to T

MIN

−40 +85 °C

MAX

.

REF

Rev. 0 | Page 4 of 28

AD7641

TIMING SPECIFICATIONS

AVDD = DVDD = 2.5 V; OVDD = 2.3 V to 3.6 V; V

Table 3.

Parameter Symbol Min Typ Max Unit

CONVERSION AND RESET (Refer to Figure 29 and Figure 30)

Convert Pulse Width t1 15 70 Time Between Conversions (Warp Mode2/Normal Mode3) t2 500/667 ns CNVST

Low to BUSY High Delay BUSY High All Modes (Except Master Serial Read After Convert) t4 385/520 ns Aperture Delay t5 1 ns End of Conversion to BUSY Low Delay t6 10 ns Conversion Time (Warp Mode/Normal Mode) t7 385/520 ns Acquisition Time (Warp Mode/Normal Mode) t8 115 ns RESET Pulse Width t9 15 ns RESET Low to BUSY High Delay BUSY High Time from RESET Low

4

PARALLEL INTERFACE MODES (Refer to Figure 31 to Figure 34 )

CNVST

Low to Data Valid Delay (Warp Mode/Normal Mode) Data Valid to BUSY Low Delay t11 2 ns Bus Access Request to Data Valid t12 20 ns Bus Relinquish Time t13 2 15 ns

MASTER SERIAL INTERFACE MODES5 (Refer to Figure 35 and Figure 36)

CS

Low to SYNC Valid Delay

CS

Low to Internal SCLK Valid Delay

CS

Low to SDOUT Delay

CNVST

Low to SYNC Delay (Warp Mode/Normal Mode)

5

SYNC Asserted to SCLK First Edge Delay t18 0.5 ns Internal SCLK Period Internal SCLK High Internal SCLK Low SDOUT Valid Setup Time SDOUT Valid Hold Time SCLK Last Edge to SYNC Delay CS

High to SYNC HI-Z

CS

High to Internal SCLK HI-Z

CS

High to SDOUT HI-Z BUSY High in Master Serial Read After Convert CNVST

Low to SYNC Asserted Delay (All Modes)

6

SYNC Deasserted to BUSY Low Delay t30 13 ns

SLAVE SERIAL INTERFACE MODES (Refer to Figure 38 and Figure 39)

External SCLK Setup Time t31 5 ns External SCLK Active Edge to SDOUT Delay t32 1 8 ns SDIN Setup Time t33 5 ns SDIN Hold Time t34 5 ns External SCLK Period t35 12.5 ns External SCLK High t36 5 ns External SCLK Low t37 5 ns

1

See the Conversion Control section.

2

All timings for wideband warp mode are the same as warp mode.

3

In warp mode only, the maximum time between conversions is 1 ms; otherwise, there is no required maximum time.

4

See the Digital Interface section and the RESET section.

5

In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.

6

In serial master read during convert mode. See Table 4 for serial master read after convert mode timing specifications.

= 2.5 V; all specifications T

REF

to T

MIN

t

23 ns

3

t

38

, unless otherwise noted.

MAX

1

ns

10 ns

t39 600 ns

t

385/520 ns

10

t

10 ns

14

t15 10 ns

t

10 ns

16

t

14/137 ns

17

t19 8 14 ns t20 2 ns t21 3 ns t22 1 ns t23 0 ns t24 0 ns t25 10 ns

t

10 ns

26

t

10 ns

27

t28 See Table 4 ns t

383/500 ns

29

Rev. 0 | Page 5 of 28

AD7641

Table 4. Serial Clock Timings in Master Read After Convert Mode

DIVSCLK[1] 0 0 1 1 DIVSCLK[0] Symbol 0 1 0 1 Unit

SYNC to SCLK First Edge Delay Minimum t18 0.5 3 3 3 ns Internal SCLK Period Minimum t19 8 16 32 64 ns Internal SCLK Period Maximum t19 14 26 52 103 ns Internal SCLK High Minimum t20 2 6 15 31 ns Internal SCLK Low Minimum t21 3 7 16 32 ns SDOUT Valid Setup Time Minimum t22 1 5 5 5 ns SDOUT Valid Hold Time Minimum t23 0 0.5 10 28 ns SCLK Last Edge to SYNC Delay Minimum t24 0 0.5 9 26 ns BUSY High Width Maximum t24 0.630 0.870 1.350 2.28 μs

500µAI

OL

TO OUTPUT

C

L

50pF

500µAI

NOTE

IN SERIAL INT ERFACE MODES, THE S YNC, SCLK, AND

SDOUT TIMING ARE DEFINED WIT H A MAXIMUM LOAD

OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.

C

L

1.4V

OH

Figure 2. Load Circuit for Digital Interface Timing,

SDOUT, SYNC, and SCLK Outputs, C

= 10 pF

L

0.8V

t

DELAY

2V

04761-002

0.8V

Figure 3. Voltage Reference Levels for Timing

2V

t

DELAY

2V

0.8V

04761-003

Rev. 0 | Page 6 of 28

AD7641

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Rating

Analog Inputs/Outputs

IN+1, IN−, REF, REFBUFIN, TEMP,

INGND, REFGND to AGND

AVDD + 0.3 V to AGND − 0.3 V

Ground Voltage Differences

AGND, DGND, OGND ±0.3 V

Supply Voltages

AVDD, DVDD −0.3 V to +2.7 V OVDD −0.3 V to +3.8 V AVDD to DVDD ±2.8 V AVDD, DVDD to OVDD −3.8 V to +2.8 V

Digital Inputs −0.3 V to +5.5 V PDREF, PDBUF Internal Power Dissipation Internal Power Dissipation

2

3

4

±20 mA 700 mW

2.5 W Junction Temperature 125°C Storage Temperature Range –65°C to +125°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

1

See Analog Inputs section.

2

See Voltage Reference Input section.

3

Specification is for the device in free air:

48-Lead LQFP; θ

4

Specification is for the device in free air:

48-Lead LFCSP; θJA = 26°C/W.

= 91°C/W, θJC = 30°C/W.

JA

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. 0 | Page 7 of 28

AD7641

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PDBUF

PDREF

REFBUFIN

TEMP

AVD D

IN+

AGND

AGNDNCIN–

REFGND

48 47 46 45 44 39 38 3743 42 41 40

1

AGND

AVD D

MODE0

MODE1

D0/OB/2C

WAR P

NORMAL

D1/A0

D2/A1

D3

D4/DIVSCLK[0] D5/DIVSCLK[1]

NC = NO CONNECT

PIN 1 IDENTIFIER

2

3

4

5

6

7

8

9

10

11

12

13 14 15 16 17 18 19 20 21 22 23 24

D6/EXT/INT

D8/INVSCLK

D7/INVSYNC

AD7641

TOP VIEW

(Not to Scale)

DVDD

OVDD

OGND

D9/RDC/SDIN

DGND

Figure 4. Pin Configuration

Table 6. Pin Function Descriptions

Pin No.

1, 36,

Mnemonic Type

AGND P Analog Power Ground Pin.

1

Description

41, 42 2, 44 AVDD P Input Analog Power Pins. Nominally 2.5 V. 3, 4 MODE[0:1] DI Data Output Interface Mode Selection.

Interface MODE# MODE1 MODE0 Description

0 0 0 18-bit interface 1 0 1 16-bit interface 2 1 0 8-bit (byte) interface 3 1 1 Serial interface 5

D0/OB/

2C

DI/O

When MODE[1:0] = 0 (18-bit interface mode), this pin is Bit 0 of the parallel port data output bus and the data coding is straight binary. In all other modes, this pin allows the choice of straight binary/twos complement. When OB/

2C

is high, the digital output is straight binary; when low,

the MSB is inverted resulting in a twos complement output from its internal shift register.

6 WARP DI

Conversion Mode Selection. When WARP = high and mode with slightly improved linearity and THD. When WARP = high and warp mode. In either mode, these are the fastest modes; maximum throughput is achievable, and

a minimum conversion rate must be applied to guarantee full specified accuracy.

7

NORMAL

DI

Conversion Mode Selection. When

NORMAL = low and WARP = low, this input selects normal mode

where full accuracy is maintained independent of the minimum conversion rate.

8 D1/A0 DI/O

When MODE[1:0] = 0, this pin is Bit 1 of the parallel port data output bus. In all other modes, this input pin controls the form in which data is output as shown in

9 D2/A1 DI/O When MODE[1:0] = 0, this pin is Bit 2 of the parallel port data output bus.

When MODE[1:0] = 1 or 2, this input pin controls the form in which data is output as shown in

10 D3 D0

When MODE[1:0] = 0, 1, or 2, this output is used as Bit 3 of the parallel port data output bus.

This pin is always an output, regardless of the interface mode. 11, 12 D[4:5] DI/O When MODE[1:0] = 0, 1, or 2, these pins are Bit 4 and Bit 5 of the parallel port data output bus. or DIVSCLK[0:1]

When MODE[1:0] = 3 (serial mode), serial clock division selection. When using serial master read

after convert mode (EXT/

INT = low, RDC/SDIN = low), these inputs can be used to slow down the internally generated serial clock that clocks the data output. In other serial modes, these pins are high impedance outputs.

REF

36

AGND

CNVST

35

PD

34

33

RESET

32

CS

31

RD

30

DGND

29

BUSY

28

D17

27

D16

26

D15

25

D14

D11/SCLK

D12/SYNC

D10/SDOUT

D13/RDERROR

04761-004

NORMAL = high, this selects wideband warp

NORMAL = low, this selects

Table 7.

Table 7 .

Rev. 0 | Page 8 of 28

AD7641

Pin No. Mnemonic Type

13 D6 DI/O When MODE[1:0] = 0, 1, or 2, this output is used as Bit 6 of the parallel port data output bus.

14 D7 DI/O When MODE[1:0] = 0, 1, or 2, this output is used as Bit 7 of the parallel port data output bus. or INVSYNC

15 D8 DI/O When MODE[1:0] = 0, 1, or 2, this output is used as Bit 8 of the parallel port data output bus. or INVSCLK

16 D9 DI/O When MODE[1:0] = 0, 1, or 2, this output is used as bit 9 of the parallel port data output bus. or RDC

or SDIN

17 OGND P Input/Output Interface Digital Power Ground. 18 OVDD P

19 DVDD P Digital Power. Nominally at 2.5 V. 20 DGND P Digital Power Ground. 21 D10 DO When MODE[1:0] = 0, 1, or 2, this output is used as Bit 10 of the parallel port data output bus. or SDOUT

22 D11 DI/O When MODE[1:0] = 0, 1, or 2, this output is used as Bit 11 of the parallel port data output bus. or SCLK

23 D12 DO When MODE[1:0] = 0, 1, or 2, this output is used as Bit 12 of the parallel port data output bus. or SYNC

24 D13 DO When MODE[1:0] = 0, 1, or 2, this output is used as Bit 13 of the parallel port data output bus. or RDERROR

or EXT/

INT

1

Description

When MODE[1:0] = 3, (serial mode), serial clock source select. This input is used to select the internally generated (master) or external (slave) serial data clock.

When EXT/ When EXT/INT = high, slave mode. The output data is synchronized to an external clock signal,

gated by CS, connected to the SCLK input.

When MODE[1:0] = 3, (serial mode), invert sync select. In serial master mode (EXT/ input is used to select the active state of the SYNC signal. When INVSYNC = low, SYNC is active high.

When INVSYNC = high, SYNC is active low.

When MODE[1:0] = 3, (serial mode), invert SCLK select. In all serial modes, this input is used to invert the SCLK signal.

When MODE[1:0] = 3, (serial mode), read during convert. When using serial master mode (EXT/

When RDC = high, the previous conversion result is output on SDOUT during conversion and the period of SCLK changes (see the

When RDC = low (read after convert), the current result can be output on SDOUT only when the conversion is complete.

When MODE[1:0] = 3, (serial mode), serial data in. When using serial slave mode, (EXT/ SDIN could be used as a data input to daisy-chain the conversion results from two or more ADCs

onto a single SDOUT line. The digital data level on SDIN is output on SDOUT with a delay of 18 SCLK periods after the initiation of the read sequence.

Input/Output Interface Digital Power. Nominally at the same supply as the supply of the host interface (2.5 V or 3 V).

When MODE[1:0] = 3, (serial mode), serial data output. In serial mode, this pin is used as the serial data output synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7641 provides the conversion result, MSB first, from its internal shift register. The data format is determined by the logic level of OB/

In master mode, EXT/ In slave mode, EXT/

When INVSCLK = low, SDOUT is updated on SCLK rising edge and valid on the next falling edge. When INVSCLK = high, SDOUT is updated on SCLK falling edge and valid on the next rising edge.

When MODE[1:0] = 3, (serial mode), serial clock. In all serial modes, this pin is used as the serial data clock input or output, depending upon the logic state of the EXT/ where the data SDOUT is updated depends on the logic state of the INVSCLK pin.

When MODE[1:0] = 3, (serial mode), frame synchronization. In serial master mode (EXT/ this output is used as a digital output frame synchronization for use with the internal data clock.

When a read sequence is initiated and INVSYNC = low, SYNC is driven high and remains high while SDOUT output is valid.

When a read sequence is initiated and INVSYNC = high, SYNC is driven low and remains low while SDOUT output is valid.

When MODE[1:0] = 3, (serial mode), read error. In serial slave mode (EXT/ is used as an incomplete read error flag. If a data read is started and not completed when the current conversion is complete, the current data is lost and RDERROR is pulsed high.

INT = low, master mode. The internal serial clock is selected on SCLK output.

INT = low), this

INT = low), RDC is used to select the read mode.

Master Serial Interface section).

INT = high),

2C.

INT = low. SDOUT is valid on both edges of SCLK.

INT = high:

INT pin. The active edge

INT= low),

INT = high), this output

Rev. 0 | Page 9 of 28

ANALOG DEVICES AD7641 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

TIMING SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS