ANALOG DEVICES AD7631 Service Manual

18-Bit, 250 kSPS, Differential

VCC

V

FEATURES

Multiple pins/software-programmable input ranges

+5 V (10 V p-p), +10 V (20 V p-p), ±5 V (20 V p-p),

±10 V (40 V p-p)
Pins or serial SPI-compatible input ranges/mode selection
Throughput: 250 kSPS
INL: ±1.5 LSB typical, ±2.5 LSB maximum (±9.5 ppm of FSR)
18-bit resolution with no missing codes
Dynamic range: 102.5 dB
SNR: 101 dB @ 2 kHz
THD: −112 dB @ 2 kHz
iCMOS® process technology
5 V internal reference: typical drift 3 ppm/°C; TEMP output
No pipeline delay (SAR architecture)
Parallel (18-/16-/8-bit bus) and serial 5 V/3.3 V interface
SPI-/QSPI™-/MICROWIRE™-/DSP-compatible
Power dissipation

73 mW @ 250 kSPS
10 mW @ 1 kSPS

Pb-free, 48-lead LQFP and 48-lead LFCSP (7 mm × 7 mm)

APPLICATIONS

Process controls
High speed data acquisition
Digital signal processing
Spectrum analysis
AT E

GENERAL DESCRIPTION

The AD7631 is an 18-bit, charge redistribution, successive
approximation register (SAR), architecture analog-to-digital
converter (ADC) fabricated on Analog Devices, Inc.’s iCMOS
high voltage process. The device is configured through hardware
or via a dedicated write-only serial configuration port for input
range and operating mode. The AD7631 contains a high speed
18-bit sampling ADC, an internal conversion clock, an internal
reference (and buffer), error correction circuits, and both serial
and parallel system interface ports. A falling edge on
samples the fully differential analog inputs on IN+ and IN−.
The AD7631 features four different analog input ranges. Power is
scaled linearly with throughput. Operation is specified from

−40°C to +85°C.

CNVST

Programmable Input PulSAR® ADC

AD7631

FUNCTIONAL BLOCK DIAGRAM

AGND

AVDD

PDREF

PDBUF

IN+

IN–

CNVST

PD

RESET

TEMP

REFBUFIN

REF

CONTROL L OGIC AND

CALIBRAT ION CI RCUITRY

REF REFGND

REF
AMP

SWITCHED

CAP DAC

BIPOLAR TEN

CLOCK

EE

AD7631

SERIAL DATA

CONFIGURATI ON

PARALLEL

INTERFACE

MODE0 MODE1

Figure 1.

Table 1. 48-Lead PulSAR Selection

100 to

Input Type

Res
(Bits)

250
(kSPS)

Bipolar 14 AD7951

Differential

14 AD7952

Bipolar

Unipolar 16 AD7651 AD7650 AD7653
AD7660 AD7652 AD7667
AD7661 AD7664
AD7666

Bipolar 16 AD7610 AD7665 AD7612
AD7663 AD7671

Differential 16 AD7675 AD7676 AD7677 AD7621
Unipolar AD7622
AD7623

Simultaneous/ 16 AD7654

Multichannel

AD7655

Unipolar

Differential 18 AD7678 AD7679 AD7674 AD7641

Unipolar AD7643

Differential

18 AD7631 AD7634

Bipolar

500 to
570
(kSPS)

PORT

SERIAL

PORT

DGNDDVDD

18

570 to
1000
(kSPS)

OVDD

OGND

D[17:0]

BUSY

RD

CS

D0/OB/2C

D1/A0

D2/A1

>1000
(kSPS)

06588-001

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2007–2011 Analog Devices, Inc. All rights reserved.

AD7631

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram ..............................................................1

Revision History ...............................................................................2

Specifications..................................................................................... 3

Timing Specifications ..................................................................5

Absolute Maximum Ratings............................................................ 7

ESD Caution.................................................................................. 7

Pin Configuration and Function Descriptions............................. 8

Typical Performance Characteristics........................................... 12

Terminology.................................................................................... 16

Theory of Operation ......................................................................17

Overview...................................................................................... 17

Converter Operation.................................................................. 17

Transfer Functions......................................................................18

Typical Connection Diagram ...................................................18

Analog Inputs..............................................................................19

Driver Amplifier Choice ........................................................... 20

Voltage Reference Input/Output ..............................................21

Power Supplies............................................................................ 22

Conversion Control................................................................... 23

Interfaces.......................................................................................... 24

Digital Interface.......................................................................... 24

Parallel Interface......................................................................... 24

Serial Interface............................................................................ 25

Master Serial Interface............................................................... 25

Slave Serial Interface.................................................................. 26

Hardware Configuration........................................................... 29

Software Configuration............................................................. 29

Microprocessor Interfacing....................................................... 30

Application Information................................................................ 31

Layout Guidelines....................................................................... 31

Evaluating Performance ............................................................ 31

Outline Dimensions....................................................................... 32

Ordering Guide .......................................................................... 32

REVISION HISTORY

3/11—Rev. 0 to Rev. A

Changes to Resolution Parameter, Table 2 .................................... 3

Changes to Figure 4 and Table 6..................................................... 8

Added Exposed Pad Notation to Outline Dimensions ............. 32

2/07—Revision 0: Initial Version

Rev. A | Page 2 of 32

AD7631

SPECIFICATIONS

AVDD = DVDD = 5 V; OVDD = 2.7 V to 5.5 V; VCC = 15 V; VEE = −15 V; V

Table 2.

Parameter Conditions/Comments Min Typ Max Unit

RESOLUTION 18 Bits
ANALOG INPUTS

Differential Voltage Range, VIN (V

0 V to 5 V VIN = 10 V p-p −V
0 V to 10 V VIN = 20 V p-p −2 V
±5 V VIN = 20 V p-p −2 V
±10 V VIN = 40 V p-p −4 V

Operating Voltage Range V

0 V to 5 V −0.1 +5.1 V
0 V to 10 V −0.1 +10.1 V
±5 V −5.1 +5.1 V
±10 V −10.1 +10.1 V

Common-Mode Voltage Range V

5 V V
10 V V

Bipolar Ranges −0.1 0 +0.1 V
Analog Input CMRR fIN = 100 kHz 75 dB
Input Current 250 kSPS throughput 801 µA
Input Impedance

THROUGHPUT SPEED

Complete Cycle 4.0 µs
Throughput Rate 250 kSPS

DC ACCURACY

Integral Linearity Error2 250 kSPS throughput −2.5 ±1.5 +2.5 LSB3
No Missing Codes 18 Bits
Differential Linearity Error2
Transition Noise 0.75 LSB
Unipolar Zero Error −0.06 +0.06 %FS
Bipolar Zero Error −0.03 +0.03 %FS
Zero-Error Temperature Drift ±0.5 ppm/°C
Bipolar Full-Scale Error −0.09 +0.09 %FS
Unipolar Full-Scale Error −0.07 +0.07 %FS
Full-Scale Error Temperature Drift ±0.5 ppm/°C
Power Supply Sensitivity AVDD = 5 V ± 5% 3 LSB

AC ACCURACY

Dynamic Range VIN = 0 to 5 V, fIN = 2 kHz, −60 dB 100 101.8 dB4
V
Signal-to-Noise Ratio VIN = 0 to 5 V, fIN = 2 kHz 99.5 100.5 dB
V
Signal-to-(Noise + Distortion), SINAD fIN = 2 kHz 100 dB
Total Harmonic Distortion fIN = 2 kHz 112 dB
Spurious-Free Dynamic Range fIN = 2 kHz 113 dB

−3 dB Input Bandwidth VIN = 0 V to 5 V 45 MHz

SAMPLING DYNAMICS

Aperture Delay 2 ns
Aperture Jitter 5 ps rms
Transient Response Full-scale step 500 ns

) − (V

IN+

IN+

IN+

See

)

IN−

, V

to AGND

IN−

, V

IN−

Analog Inputs section

−1 +2.5 LSB

= all other input ranges, fIN = 2 kHz, −60 dB 100 102.5 dB

IN

= all other input ranges, fIN = 2 kHz 100 101 dB

IN

= 5 V; all specifications T

REF

REF

REF

to T

MIN

+V

REF

+2 V

REF

+2 V

REF

+4 V

REF

/2 − 0.1 V

− 0.2 V

, unless otherwise noted.

MAX

/2 V

REF

V

REF

V

REF

V

REF

V

REF

V

REF

/2 + 0.1 V

REF

+ 0.2 V

REF

Rev. A | Page 3 of 32

AD7631

Parameter Conditions/Comments Min Typ Max Unit

INTERNAL REFERENCE PDREF = PDBUF = low

Output Voltage REF @ 25°C 4.965 5.000 5.035 V
Temperature Drift –40°C to +85°C ±3 ppm/°C
Line Regulation AVDD = 5 V ± 5% ±15 ppm/V
Long-Term Drift 1000 hours 50 ppm
Turn-On Settling Time C

REFERENCE BUFFER PDREF = high

REFBUFIN Input Voltage Range 2.4 2.5 2.6 V

EXTERNAL REFERENCE PDREF = PDBUF = high

Voltage Range REF 4.75 5 AVDD + 0.1 V
Current Drain 250 kSPS throughput 250 µA

TEMPERATURE PIN

Voltage Output @ 25°C 311 mV
Temperature Sensitivity 1 mV/°C
Output Resistance 4.33 kΩ

DIGITAL INPUTS

Logic Levels

VIL −0.3 +0.6 V
VIH 2.1 OVDD + 0.3 V
IIL −1 +1 µA
IIH −1 +1 µA

DIGITAL OUTPUTS

Data Format Parallel or serial 18-bit
Pipeline Delay5

VOL I
VOH I

POWER SUPPLIES

Specified Performance

AVDD 4.756 5 5.25 V
DVDD 4.75 5 5.25 V
OVDD 2.7 5.25 V
VCC 7 15 15.75 V
VEE −15.75 −15 0 V

Operating Current7 @ 250 kSPS throughput

AVDD

With Internal Reference8 8.5 mA
With Internal Reference Disabled8 6.1 mA

DVDD 4 mA
OVDD 0.1 mA
VCC VCC = 15 V, with internal reference buffer 1.4 mA

VCC = 15 V 0.8 mA

VEE VEE = −15 V 0.7 mA

Power Dissipation @ 250 kSPS throughput

With Internal Reference8 94 120 mW
With Internal Reference Disabled8 73 100 mW

In Power-Down Mode9 PD = high 10 µW

TEMPERATURE RANGE10

Specified Performance T

1

In all input ranges, the input current scales with throughput. See the An alog In puts section.

2

Linearity is tested using endpoints, not best fit. All linearity is tested with an external 5 V reference.

3

LSB means least significant bit. All specifications in LSB do not include the error contributed by the reference.

4

All specifications in decibels are referred to a full-scale range input, FSR. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified.

5

Conversion results are available immediately after completed conversion.

6

4.75 V or V

7

Tested in parallel reading mode.

8

With internal reference, PDREF = PDBUF = low; with internal reference disabled, PDREF = PDBUF = high. With internal reference buffer, PDBUF = low.

9

With all digital inputs forced to OVDD.

10

Consult sales for extended temperature range.

− 0.1 V, whichever is larger.

REF

= 22 µF 10 ms

REF

= 500 µA 0.4 V

SINK

= −500 µA OVDD − 0.6 V

SOURCE

to T

MIN

−40 +85 °C

MAX

Rev. A | Page 4 of 32

AD7631

TIMING SPECIFICATIONS

AVDD = DVDD = 5 V; OVDD = 2.7 V to 5.5 V; VCC = 15 V; VEE = −15 V; V

Table 3.

Parameter Symbol Min Typ Max Unit

CONVERSION AND RESET (See Figure 35 and Figure 36)

Convert Pulse Width t1 10 ns
Time Between Conversions t2 4.0 µs
CNVST Low to BUSY High Delay
BUSY High All Modes (Except Master Serial Read After Convert) t4
Aperture Delay t5 2 ns
End of Conversion to BUSY Low Delay t6 10 ns
Conversion Time t7
Acquisition Time t8 2.32 ns
RESET Pulse Width t9 10 ns

PARALLEL INTERFACE MODES (See Figure 37 and Figure 39)

CNVST Low to DATA Valid Delay
DATA Valid to BUSY Low Delay t11 20 ns
Bus Access Request to DATA Valid t12 40 ns
Bus Relinquish Time t13 2 15 ns

MASTER SERIAL INTERFACE MODES1 (See Figure 41 and Figure 42)

CS Low to SYNC Valid Delay
CS Low to Internal SDCLK Valid Delay1
CS Low to SDOUT Delay
CNVST Low to SYNC Delay, Read During Convert
SYNC Asserted to SDCLK First Edge Delay t18 3 ns

Internal SDCLK Period2 t
Internal SDCLK High2 t
Internal SDCLK Low2 t
SDOUT Valid Setup Time2 t
SDOUT Valid Hold Time2 t
SDCLK Last Edge to SYNC Delay2 t
CS High to SYNC HIGH-Z

CS High to Internal SDCLK HIGH-Z
CS High to SDOUT HIGH-Z
BUSY High in Master Serial Read After Convert2 t
CNVST Low to SYNC Delay, Read After Convert
SYNC Deasserted to BUSY Low Delay t30 25 ns

SLAVE SERIAL/SERIAL CONFIGURATION INTERFACE MODES1

(See Figure 44, Figure 45, and Figure 47)
External SDCLK, SCCLK Setup Time t31 5 ns
External SDCLK Active Edge to SDOUT Delay t32 2 18 ns
SDIN/SCIN Setup Time t33 5 ns
SDIN/SCIN Hold Time t34 5 ns
External SDCLK/SCCLK Period t35 25 ns
External SDCLK/SCCLK High t36 10 ns
External SDCLK/SCCLK Low t37 10 ns

1

In serial interface modes, the SYNC, SDSCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.

2

In serial master read during convert mode. See Table 4 for serial master read after convert mode.

= 5 V; all specifications T

REF

t

35 ns

3

t

10

t

10 ns

14

t

10 ns

15

t

10 ns

16

t

530 ns

17

30 45 ns

19

15 ns

20

10 ns

21

4 ns

22

5 ns

23

5 ns

24

t

10 ns

25

t

10 ns

26

t

10 ns

27

See Table 4

28

t

29

1.5

MIN

to T

, unless otherwise noted.

MAX

1.68

1.68

1.65

µs

µs

µs

µs

Rev. A | Page 5 of 32

AD7631

Table 4. Serial Clock Timings in Master Read After Convert Mode

DIVSCLK[1] 0 0 1 1
DIVSCLK[0] Symbol 0 1 0 1 Unit

SYNC to SDCLK First Edge Delay Minimum t18 3 20 20 20 ns
Internal SDCLK Period Minimum t19 30 60 120 240 ns
Internal SDCLK Period Maximum t19 45 90 180 360 ns
Internal SDCLK High Minimum t20 15 30 60 120 ns
Internal SDCLK Low Minimum t21 10 25 55 115 ns
SDOUT Valid Setup Time Minimum t22 4 20 20 20 ns
SDOUT Valid Hold Time Minimum t23 5 8 35 90 ns
SDCLK Last Edge to SYNC Delay Minimum t24 5 7 35 90 ns
BUSY High Width Maximum t28 2.55 3.40 5.00 8.20 µs

1.6mA I

TO OUTPUT

PIN

C

L

60pF

500µA I

NOTES

1. IN SERIAL INTERFACE MODES, THE SYNC, SDCLK,
AND SDOUT ARE DEFI NED WITH A M AXIMUM LO AD

OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.

C

L

Figure 2. Load Circuit for Digital Interface Timing,

SDOUT, SYNC, and SDCLK Outputs, C

OL

1.4V

2V

OH

6588-002

0.8V

t

DELAY

t

DELAY

2V

2V

0.8V0.8V

06588-003

Figure 3. Voltage Reference Levels for Timing

= 10 pF

L

Rev. A | Page 6 of 32

AD7631

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Rating

Analog Inputs/Outputs

IN+1, IN−1 to AGND VEE − 0.3 V to VCC + 0.3 V
REF, REFBUFIN, TEMP,

REFGND to AGND

AVDD + 0.3 V to
AGND − 0.3 V

Ground Voltage Differences

AGND, DGND, OGND ±0.3 V

Supply Voltages

AVDD, DVDD, OVDD −0.3 V to +7 V
AVDD to DVDD, AVDD to OVDD ±7 V
DVDD to OVDD ±7 V
VCC to AGND, DGND –0.3 V to +16.5 V
VEE to GND +0.3 V to −16.5 V

Digital Inputs −0.3 V to OVDD + 0 .3 V
PDREF, PDBUF

±20 mA
Internal Power Dissipation2 700 mW
Internal Power Dissipation3 2.5 W
Junction Temperature 125°C
Storage Temperature Range −65°C to +125°C

1

See the Analog Inputs section.

2

Specification is for the device in free air: 48-lead LFQP; θJA = 91°C/W and θJC = 30°C/W.

3

Specification is for the device in free air: 48-lead LFCSP; θJA = 26°C/W.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. A | Page 7 of 32

AD7631

A

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VEE

DGND

IN–

VCC

REFGND

REF

36

BIPOLAR

35

CNVST

34

PD

33

RESET

32

CS

31

RD

30

TEN

29

BUSY

28

D17/SCCS

27

D16/SCCLK

26

D15/SCIN

25

D14/HW/SW

D12/SYNC

D10/SDOUT

D11/SDCLK

D13/RDERROR

06588-004

PDBUF

PDREF

REFBUFIN

48 47 46 45 44 43 42 41 40 39 38 37

1

AGND

AVD D

MODE0

MODE1

D0/OB/2C

OGND

OGND

D1/A0

D2/A1

D3

D4/DIVSCLK[0]

D5/DIVSCLK[1]

NOTES

1. FOR THE LEAD FRAME CHIP SCALE PACKAGE (LFCSP), THE EXPOSED PAD
SHOULD BE CONNECTED TO VEE. THIS CONNECTION IS NOT REQUIREDTO
MEET THE ELECTRIC

PIN 1

2

3

4

5

6

7

8

9

10

11

12

14 15 16 17 18 19 20 21 22 23 24

13

D6/EXT/ INT

D8/INVSCL K

D7/INVSYNC

L PERFORMANCES.

IN+

TEMP

AVD D

AD7631

TOP VIEW

(Not to Scale)

OVDD

OGND

D9/RDC/SDIN

AGND

DVDD

Figure 4. Pin Configuration

Table 6. Pin Function Descriptions

Pin No. Mnemonic Type1 Description

1, 42 AGND P

Analog Power Ground Pins. Ground reference point for all analog I/O. All analog I/O should be
referenced to AGND and should be connected to the analog ground plane of the system. In addition,

the AGND, DGND, and OGND voltages should be at the same potential.
2, 44 AVDD P Analog Power Pins. Nominally 4.75 V to 5.25 V and decoupled with 10 µF and 100 nF capacitors.
3, 4 MODE[0:1] DI

0 Low Low
1 Low High
2 High Low
3 High High
5

D0/OB/2C

DI/O

Data Input/Output Interface Mode Selection.

Interface Mode MODE1 MODE0

Description

18-bit interface
16-bit interface
8-bit (byte) interface
Serial interface

2

In 18-bit parallel mode, this output is used as Bit 0 of the parallel port data output bus, and the data

coding is straight binary. In all other modes, this pin allows the choice of straight binary or twos

complement.

When OB/2C

= high, the digital output is straight binary.
When OB/2C = low, the MSB is inverted resulting in a twos complement output from its internal
shift register.

6, 7, 17 OGND P

Input/Output Interface Digital Power Ground. Ground reference point for digital outputs. Should
be connected to the system digital ground ideally at the same potential as AGND and DGND.

8 D1/A0 DI/O

When MODE[1:0] = 0, this pin is Bit 1 of the parallel port data output bus. In all other modes, this
input pin controls the form in which data is output as shown in Tabl e 7.

9 D2/A1 DI/O

When MODE[1:0] = 0, this pin is Bit 2 of the parallel port data output bus.
When MODE[1:0] = 1 or 2, this input pin controls the form in which data is output as shown in Table 7.

10 D3 DO

When MODE[1:0] = 0, 1, or 2, this output is used as Bit 3 of the parallel port data output bus.
This pin is always an output, regardless of the interface mode.

Rev. A | Page 8 of 32

AD7631

Pin No. Mnemonic Type1 Description

11, 12 D[4:5] or DI/O When MODE[1:0] = 0, 1, or 2, these pins are Bit 4 and Bit 5 of the parallel port data output bus.
DIVSCLK[0:1]

13 D6 or DO/I When MODE[1:0] = 0, 1, or 2, this output is used as Bit 6 of the parallel port data output bus.

14 D7 or
INVSYNC

15 D8 or DI/O When MODE[1:0] = 0, 1, or 2, this output is used as Bit 8 of the parallel port data output bus.
INVSCLK

16 D9 or DI/O When MODE[1:0] = 0, 1, or 2, this output is used as Bit 9 of the parallel port data output bus.
RDC or

SDIN

18 OVDD P

19 DVDD P

20 DGND P

21 D10 or DI/O When MODE[1:0] = 0, 1, or 2, this output is used as Bit 10 of the parallel port data output bus.
SDOUT

22 D11 or DI/O When MODE[1:0] = 0, 1, or 2, this output is used as Bit 11 of the parallel port data output bus.
SDCLK

EXT/INT

DI/O

When MODE[1:0] = 3, serial data clock division selection. When using serial master read after convert
mode (EXT/INT
serial clock that clocks the data output. In other serial modes, these pins are high impedance outputs.

When MODE[1:0] = 3, Serial Data Clock Source Select. In serial mode, this input is used to select the
internally generated (master) or the external (slave) serial data clock for the AD7631 output data.
When EXT/INT

When EXT/INT = high (slave mode), the output data is synchronized to an external clock signal (gated by CS)
connected to the SDCLK input.
When MODE[1:0] = 0, 1, or 2, this output is used as Bit 7 of the parallel port data output bus.

When MODE[1:0] = 3, Serial Data Invert Sync Select. In serial master mode (MODE[1:0] = 3,
EXT/INT = low), this input is used to select the active state of the SYNC signal.
When INVSYNC = low, SYNC is active high.
When INVSYNC = high, SYNC is active low.

When MODE[1:0] = 3, Invert SDCLK/SCCLK Select. This input is used to invert both SDCLK and SCCLK.
When INVSCLK = low, the rising edge of SDCLK/SCCLK are used.
When INVSCLK = high, the falling edge of SDCLK/SCCLK are used.

When MODE[1:0] = 3, Serial Data Read During Convert. In serial master mode (MODE[1:0] = 3,
EXT/INT = low), RDC is used to select the read mode. See the section.
When RDC = low, the current result is read after conversion. Note the maximum throughput is
not attainable in this mode.
When RDC = high, the previous conversion result is read during the current conversion.

When MODE[1:0] = 3, Serial Data In. In serial slave mode (MODE[1:0] = 3, EXT/INT
be used as a data input to daisy-chain the conversion results from two or more ADCs onto a single

SDOUT line. The digital data level on SDIN is output on SDOUT with a delay of 16 SDCLK periods after
the initiation of the read sequence.

Input/Output Interface Digital Power. Nominally at the same supply as the supply of the host
interface 2.5 V, 3 V, or 5 V and decoupled with 10 F and 100 nF capacitors.

Digital Power. Nominally at 4.75 V to 5.25 V and decoupled with 10 F and 100 nF capacitors. Can
be supplied from AVDD.

Digital Power Ground. Ground reference point for digital outputs. Should be connected to system
digital ground ideally at the same potential as AGND and OGND.

When MODE[1:0] = 3, Serial Data Output. In all serial modes, this pin is used as the serial data output
synchronized to SDCLK. Conversion results are stored in an on-chip register. The AD7631 provides
the conversion result, MSB first, from its internal shift register. The data format is determined by
the logic level of OB/2C
When EXT/INT
When EXT/INT

When INVSCLK = low, SDOUT is updated on SDCLK rising edge.
When INVSCLK = high, SDOUT is updated on SDCLK falling edge.

When MODE[1:0] = 3, Serial Data Clock. In all serial modes, this pin is used as the serial data clock
input or output, dependent on the logic state of the EXT/INT
SDOUT is updated depends on the logic state of the INVSCLK pin.

= low, RDC/SDIN = low), these inputs can be used to slow down the internally generated

= low (master mode), the internal serial data clock is selected on SDCLK output.

Master Serial Interface

= high), SDIN can

.
= low (master mode), SDOUT is valid on both edges of SDCLK.
= high (slave mode):

pin. The active edge where the data

Rev. A | Page 9 of 32

AD7631

Pin No. Mnemonic Type1 Description

23 D12 or DO When MODE[1:0] = 0, 1, or 2, this output is used as Bit 12 of the parallel port data output bus.
SYNC

24 D13 or DO When MODE[1:0] = 0, 1, or 2, this output is used as Bit 13 of the parallel port data output bus.
RDERROR

25 D14 or DI/O When MODE[1:0] = 0, 1, or 2, this output is used as Bit 14 of the parallel port data output bus.

26 D15 or DI/O When MODE[1:0] = 0, 1, or 2, this output is used as Bit 15 of the parallel port data output bus.
SCIN

27 D16 or DI/O When MODE[1:0] = 0, 1, or 2, this output is used as Bit 16 of the parallel port data output bus.
SCCLK

28 D17 or DI/O When MODE[1:0] = 0, 1, or 2, this output is used as Bit 17 of the parallel port data output bus.

29 BUSY DO

30 TEN DI2 Input Range Select. Used in conjunction with BIPOLAR per the following.

0 to 5 Low Low
0 to 10 Low High
±5 High Low
±10 High High
31
32

33 RESET DI

34 PD DI2

35

36 BIPOLAR DI2 Input Range Select. See description for Pin 30.

HW/SW

SCCS

RD
CS

CNVST

DI
DI

DI

When MODE[1:0] = 3, Serial Data Frame Synchronization. In serial master mode (MODE[1:0] = 3,

= low), this output is used as a digital output frame synchronization for use with the

EXT/INT
internal data clock.
When a read sequence is initiated and INVSYNC = low, SYNC is driven high and remains high while
the SDOUT output is valid.
When a read sequence is initiated and INVSYNC = high, SYNC is driven low and remains low while
the SDOUT output is valid.

When MODE[1:0] = 3, Serial Data Read Error. In serial slave mode (MODE[1:0] = 3, EXT/INT
this output is used as an incomplete data read error flag. If a data read is started and not completed when

the current conversion is completed, the current data is lost and RDERROR is pulsed high.

When MODE[1:0] = 3, Serial Configuration Hardware/Software Select. In serial mode, this input is
used to configure the AD7631 by hardware or software. See the Hardware Configuration section and
Software Configuration section.
When HW/SW

When HW/SW = high, the AD7631 is configured through dedicated hardware input pins.

When MODE[1:0] = 3, Serial Configuration Data Input. In serial software configuration mode (HW/SW
low), this input is used to serially write in, MSB first, the configuration data into the serial configuration

register. The data on this input is latched with SCCLK. See the section. Software Configuration

When MODE[1:0] = 3, Serial Configuration Clock. In serial software configuration mode (HW/SW
this input is used to clock in the data on SCIN. The active edge where the data SCIN is updated

depends on the logic state of the INVSCLK pin. See the section. Software Configuration

When MODE[1:0] = 3, Serial Configuration Chip Select. In serial software configuration mode
(HW/SW

Busy Output. Transitions high when a conversion is started and remains high until the conversion is
complete and the data is latched into the on-chip shift register. The falling edge of BUSY can be used
as a data-ready clock signal. Note that in master read after convert mode (MODE[1:0] = 3, EXT/INT
RDC = low) the busy time changes according to . Table 4

Input Range (V) BIPOLAR TEN

Read Data. When CS and RD are both low, the interface parallel or serial output bus is enabled.
Chip Select. When CS and RD are both low, the interface parallel or serial output bus is enabled. CS

is also used to gate the external clock in slave serial mode (not used for serial configurable port).
Reset Input. When high, reset the AD7631. Current conversion, if any, is aborted. The falling edge of

RESET resets the data outputs to all zeros (with OB/2C
See the section. If not used, this pin can be tied to OGND. Digital Interface

Power-Down Input. When PD = high, power down the ADC. Power consumption is reduced and
conversions are inhibited after the current one is completed. The digital interface remains active
during power down.

Conversion Start. A falling edge on CNVST puts the internal sample-and-hold into the hold state and
initiates a conversion.

= low, the AD7631 is configured through software using the serial configuration register.

= low), this input enables the serial configuration port. See the section. Software Configuration

= high) and clears the configuration register.

= high),

=

= low)

= low,

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