ANALOG DEVICES AD7623 Service Manual
www.BDTIC.com/ADI
16-Bit, 1.33 MSPS PulSAR® ADC
FEATURES
Throughput: 1.33 MSPS
2.048 V internal reference
Differential input range: ±V
INL: ±1 LSB
typical
16-bit resolution with no missing codes
SINAD: 88 dB typical @ 100 kHz
THD: −97 dB typical @ 100 kHz
No pipeline delay (SAR architecture)
Parallel (16- or 8-bit bus) and serial 5 V/3.3 V/2.5 V interface
SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible
2.5 V single-supply operation
Power dissipation: 45 mW typical @ 1.33 MSPS
48-lead LQFP and LFCSP_VQ packages
Speed upgrade of the AD7677
APPLICATIONS
Medical instruments
High speed data acquisition
Digital signal processing
Communications
Instrumentation
Spectrum analysis
AT E
REF
(V
up to 2.5 V)
REF
AD7623
FUNCTIONAL BLOCK DIAGRAM
AGND
AVDD
IN+
IN–
PDREF
PDBUF
PD
RESET
TEMP
REFBUFIN
REF
CONTROL LOGIC AND
CALIBRATION CIRCUITRY
REF AMP
SWITCHED
CAP DAC
CNVST
REF REFGND
AD7623
INTERFACE
CLOCK
Figure 1.
Table 1. PulSAR Selection
Type/kSPS 100 to 250 500 to 570
Pseudo
Differential
AD7651
AD7660/61
AD7650/52
AD7664/66
True Bipolar AD7663 AD7665 AD7671
True
AD7675 AD7676 AD7677 AD7621
Differential
18-Bit AD7678 AD7679 AD7674 AD7641
Multichannel/
AD7654 AD7655
Simultaneous
DGNDDVDD
OVDD
OGND
SERIAL
PORT
16
D[15:0]
PARALLEL
SER/PAR
BUSY
RD
CS
OB/2C
BYTESWAP
800 to
1000 >1000
AD7653
AD7667
AD7623
05574-001
GENERAL DESCRIPTION
The AD7623 is a 16-bit, 1.33 MSPS, charge redistribution SAR,
fully differential analog-to-digital converter (ADC) that
operates from a single 2.5 V power supply. It contains a high
speed 16-bit sampling ADC, an internal conversion clock, an
internal reference (and buffer), error correction circuits, and
both serial and parallel system interface ports. Power consumption is automatically scaled with throughput, making it ideal
for battery-powered applications. It is available in 48-lead, low
profile quad flat package (LQFP) and a lead frame chip-scale
(LFCSP_VQ) package. Operation is specified from
−40°C to +85°C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
PRODUCT HIGHLIGHTS
1. Fast Throughput.
The AD7623 is a 1.33 MSPS, charge redistribution,
16-bit SAR ADC.
2. Sup
3. Int
4. S
5. Se
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.
erior Linearity.
The AD7623 has no missing 16-bit code.
ernal Reference.
The AD7623 has a 2.048 V internal reference with a
typical drift of ±7 ppm/°C.
ingle-Supply Operation.
The AD7623 operates from a 2.5 V single supply and
typically dissipates 45 mW. Its power dissipation decreases
with the throughput.
rial or Parallel Interface.
Versatile parallel (16- or 8-bit bus) or 2-wire serial interface
arrangement compatible with 2.5 V, 3.3 V, or 5 V logic.
AD7623
www.BDTIC.com/ADI
TABLE OF CONTENTS
Features.............................................................................................. 1
Analog Inputs .............................................................................17
Applications....................................................................................... 1
Functional Block Diagram ..............................................................1
General Description......................................................................... 1
Product Highlights........................................................................... 1
Specifications..................................................................................... 3
Timing Specifications....................................................................... 5
Serial Clock Timing Specifications............................................ 6
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Terminology ....................................................................................11
Typical Performance Characteristics ...........................................12
Theory of Operation ......................................................................15
Circuit Information.................................................................... 15
Converter Operation.................................................................. 15
Driver Amplifier Choice ........................................................... 17
Voltage Reference Input ............................................................ 18
Power Supply............................................................................... 19
Power Dissipation vs. Throughput .......................................... 20
Conversion Control................................................................... 20
Interfaces.......................................................................................... 21
Digital Interface.......................................................................... 21
Parallel Interface......................................................................... 21
Serial Interface............................................................................ 22
Master Serial Interface............................................................... 22
Slave Serial Interface.................................................................. 24
Microprocessor Interfacing....................................................... 26
Application ...................................................................................... 27
Layout .......................................................................................... 27
Evaluating the AD7623 Performance...................................... 27
Transfer Functions......................................................................16
Typical Connection Diagram ................................................... 17
REVISION HISTORY
7/05—Revision 0: Initial Version
Outline Dimensions....................................................................... 28
Ordering Guide .......................................................................... 28
Rev. 0 | Page 2 of 28
AD7623
www.BDTIC.com/ADI
SPECIFICATIONS
AVDD = DVDD = 2.5 V; OVDD = 2.3 V to 3.6 V; V
Table 2.
Parameter Conditions Min Typ Max Unit
RESOLUTION 16 Bits
ANALOG INPUT
Voltage Range
VIN+ − VIN−
Operating Input Voltage VIN+, VIN− to AGND −0.1 AVDD
Analog Input CMRR fIN = 100 kHz 55 dB
Input Current 1.33 MSPS throughput 10 μA
Input Impedance
2
THROUGHPUT SPEED
Complete Cycle 750 ns
Throughput Rate 0 1.33 MSPS
DC ACCURACY
Integral Linearity Error
3
V
No Missing Codes V
Differential Linearity Error V
Transition Noise V
Transition Noise V
Zero Error, T
MIN
to T
MAX
5
−30 +30 LSB
Zero Error Temperature Drift ±1 ppm/°C
Gain Error, T
MIN
to T
MAX
5
−0.38 +0.38 % of FSR
Gain Error Temperature Drift ±2 ppm/°C
Power Supply Sensitivity AVDD = 2.5 V ± 5% ±2 LSB
AC ACCURACY
Dynamic Range fIN = 20 kHz 90 dB
Signal-to-Noise fIN = 20 kHz 88 89.5 dB
f
f
IN
IN
Spurious-Free Dynamic Range fIN = 20 kHz 97 dB
f
IN
Total Harmonic Distortion fIN = 20 kHz –97 dB
f
IN
Signal-to-(Noise + Distortion) fIN = 20 kHz 87.5 88.5 dB
f
f
IN
IN
–3 dB Input Bandwidth 50 MHz
SAMPLING DYNAMICS
Aperture Delay 1 ns
Aperture Jitter 5 ps rms
Transient Response Full-scale step 50 ns
INTERNAL REFERENCE PDREF = PDBUF = low
Output Voltage REF @ 25°C 2.038 2.048 2.058 V
Temperature Drift –40°C to +85°C ±7 ppm/°C
Line Regulation AVDD = 2.5 V ± 5% ±15 ppm/V
Turn-On Settling Time C
REFBUFIN Output Voltage REFBUFIN @ 25°C 1.2 V
REFBUFIN Output Resistance 6.33 kΩ
= 2.5 V; all specifications T
REF
= 2.048 V, PDREF = high −2 ±1 +2 LSB
REF
= 2.048 V, PDREF = high 16 Bits
REF
= 2.048 V, PDREF = high −1 +2 LSB
REF
= 2.5 V 0.70 LSB
REF
= 2.048 V 0.82 LSB
REF
= 20 kHz, V
= 2.048 V 86 88 dB
REF
MIN
to T
−V
, unless otherwise noted.
MAX
+V
REF
V
REF
1
= 100 kHz 89 dB
= 100 kHz 96 dB
= 100 kHz −95 dB
= 20 kHz, V
= 2.048 V 87.5 dB
REF
= 100 kHz 88 dB
= 10 μF 5 ms
REF
V
4
6
Rev. 0 | Page 3 of 28
AD7623
www.BDTIC.com/ADI
Parameter Conditions Min Typ Max Unit
EXTERNAL REFERENCE PDREF = PDBUF = high
Voltage Range REF 1.8 2.048 AVDD V
Current Drain 1.33 MSPS throughput 100 μA
REFERENCE BUFFER PDREF = high, PDBUF = low
REFBUFIN Input Voltage Range 1.05 1.2 1.30 V
TEMPERATURE PIN
Voltage Output @ 25°C 273 mV
Temperature Sensitivity 0.85 mV/°C
Output Resistance 4.7 kΩ
DIGITAL INPUTS
Logic Levels
VIL –0.3 +0.6 V
VIH 1.7 5.25 V
IIL –1 +1 μA
IIH –1 +1 μA
DIGITAL OUTPUTS
Data Format
Pipeline Delay
VOL I
VOH I
POWER SUPPLIES
Specified Performance
AVDD 2.37 2.5 2.63 V
DVDD 2.37 2.5 2.63 V
OVDD 2.30
Operating Current
AVD D
DVDD 1.6 mA
OVDD 0.6 mA
Power Dissipation
With Internal Reference
Without Internal Reference
In Power-Down Mode12 PD = high 600 μW
TEMPERATURE RANGE
Specified Performance T
1
When using an external reference. With the internal reference, the input range is from −0.1 V to V
2
See the Analog Inputs section.
3
Linearity is tested using endpoints, not best fit. Tested with an external reference at 2.048 V.
4
LSB means least significant bit. With the ±2.048 V input range, 1 LSB is 62.5 μV.
5
See the Terminology section. These specifications do not include the error contribution from the external reference.
6
All specifications in dB are referred to a full-scale input FSR. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified.
7
Parallel or serial 16-bit.
8
Conversion results are available immediately after completed conversion.
9
See the Absolute Maximum Ratings section.
10
Tested in parallel reading mode.
11
With internal reference, PDREF and PDBUF are low; without internal reference, PDREF and PDBUF are high.
12
With all digital inputs forced to OVDD.
13
Consult sales for extended temperature range.
7
8
10
11
10
11
11
13
= 500 μA 0.4 V
SINK
= –500 μA OVDD − 0.3 V
SOURCE
9
3.6 V
1.33 MSPS throughput
With internal reference 15 mA
1.33 MSPS throughput 50 55 mW
1.33 MSPS throughput 45 53 mW
to T
MIN
–40 +85 °C
MAX
.
REF
Rev. 0 | Page 4 of 28
AD7623
www.BDTIC.com/ADI
TIMING SPECIFICATIONS
AVDD = DVDD = 2.5 V; OVDD = 2.3 V to 3.6 V; V
Table 3.
Parameter Symbol Min Typ Max Unit
CONVERSION AND RESET (Refer to Figure 31 and Figure 32)
Convert Pulse Width t1 15 70
Time Between Conversions t2 750 ns
CNVST Low to BUSY High Delay
BUSY High All Modes (Except Master Serial Read After Convert) t4 560 ns
Aperture Delay t5 1 ns
End of Conversion to BUSY Low Delay t6 10 ns
Conversion Time t7 560 ns
Acquisition Time t8 125 ns
RESET Pulse Width t9 15 ns
RESET Low to BUSY High Delay
BUSY High Time from RESET Low
2
2
PARALLEL INTERFACE MODES (Refer to Figure 33 to Figure 35).
CNVST Low to DATA Valid Delay
DATA Valid to BUSY Low Delay t11 2 ns
Bus Access Request to DATA Valid t12 20 ns
Bus Relinquish Time t13 2 15 ns
MASTER SERIAL INTERFACE MODES3 (Refer to Figure 37 and Figure 38)
CS Low to SYNC Valid Delay
CS Low to Internal SCLK Valid Delay
3
CS Low to SDOUT Delay
CNVST Low to SYNC Delay
SYNC Asserted to SCLK First Edge Delay t18 0.5 ns
Internal SCLK Period
Internal SCLK High
Internal SCLK Low
SDOUT Valid Setup Time
SDOUT Valid Hold Time
SCLK Last Edge to SYNC Delay
4
4
4
4
4
4
CS High to SYNC HI-Z
CS High to Internal SCLK HI-Z
CS High to SDOUT HI-Z
BUSY High in Master Serial Read after Convert
CNVST Low to SYNC Asserted Delay
SYNC Deasserted to BUSY Low Delay t30 13 ns
SLAVE SERIAL INTERFACE MODES3 (Refer to Figure 40 and Figure 41)
External SCLK Setup Time t31 5 ns
External SCLK Active Edge to SDOUT Delay t32 1 8 ns
SDIN Setup Time t33 5 ns
SDIN Hold Time t34 5 ns
External SCLK Period t35 12.5 ns
External SCLK High t36 5 ns
External SCLK Low t37 5 ns
1
See the Conversion Control section.
2
See the Digital Interface and RESET sections.
3
In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.
4
In serial master read during convert mode. See Table 4 for serial master read after convert mode timing specifications.
= 2.5 V; all specifications T
REF
4
to T
MIN
23 ns
t
3
, unless otherwise noted.
MAX
1
ns
t38 10 ns
t39 600 ns
560 ns
t
10
10 ns
t
14
t15 10 ns
10 ns
t
16
263 ns
t
17
t19 8 12 ns
t20 2 ns
t21 3 ns
t22 1 ns
t23 0 ns
t24 0 ns
10 ns
t
25
10 ns
t
26
10 ns
t
27
t28 See Table 4
500 ns
t
29
Rev. 0 | Page 5 of 28
AD7623
www.BDTIC.com/ADI
SERIAL CLOCK TIMING SPECIFICATIONS
Table 4. Serial Clock Timings in Master Read After Convert Mode
DIVSCLK[1] 0 0 1 1
DIVSCLK[0] Symbol 0 1 0 1 Unit
SYNC to SCLK First Edge Delay Minimum t18 0.5 3 3 3 ns
Internal SCLK Period Minimum t19 8 16 32 64 ns
Internal SCLK Period Maximum t19 12 25 50 100 ns
Internal SCLK High Minimum t20 2 6 15 31 ns
Internal SCLK Low Minimum t21 3 7 16 32 ns
SDOUT Valid Setup Time Minimum t22 1 5 5 5 ns
SDOUT Valid Hold Time Minimum t23 0 0.5 10 28 ns
SCLK Last Edge to SYNC Delay Minimum t24 0 0.5 9 26 ns
BUSY High Width Maximum t28 0.780 1.000 1.440 2.320 μs
500μAI
TO OUTPUT
PIN
C
L
50pF
500μAI
NOTE
IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND
SDOUT ARE DEFINED WITH A MAXIMUM LOAD.
OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.
C
L
Figure 2. Load Circuit for Digital Interface Timing,
SDOUT, SYNC, and SCLK Outputs, C
OL
1.4V
OH
05574-002
= 10 pF
L
0.8V
t
DELAY
2V
0.8V
Figure 3. Voltage Reference Levels for Timing
2V
t
DELAY
2V
0.8V
05574-003
Rev. 0 | Page 6 of 28
AD7623
www.BDTIC.com/ADI
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Rating
Analog Inputs/Outputs
IN+1, IN−, REF, REFBUFIN, TEMP,
INGND, REFGND to AGND
Ground Voltage Differences
AGND, DGND, OGND ±0.3 V
Supply Voltages
AVDD, DVDD –0.3 V to +2.7 V
OVDD –0.3 V to +3.8 V
AVDD to DVDD ±2.8 V
AVDD to OVDD +2.8 V to −3.8 V
OVDD to DVDD
Digital Inputs −0.3 V to +5.5 V
PDREF, PDBUF
Internal Power Dissipation
Internal Power Dissipation
Junction Temperature 125°C
Storage Temperature Range –65°C to +125°C
1
See the Analog Inputs section.
2
See the Power Supply section.
3
See the Voltage Reference Input section.
4
Specification is for the device in free air: 48-Lead LQFP; θJA = 91°C/W,
θJC = 30°C/W.
5
Specification is for the device in free air: 48-Lead LFCSP; θJA = 26°C/W.
2
3
4
5
AVDD + 0.3 V to
AGND − 0.3 V
≤ +0.3 V if DVDD < 2.3 V
±20 mA
700 mW
2.5 W
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate
on the human body and test equipment and can discharge without detection. Although this product
features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to
high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid
performance degradation or loss of functionality.
Rev. 0 | Page 7 of 28
AD7623
www.BDTIC.com/ADI
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PDBUF
PDREF
REFBUFIN
TEMP
AVDD
IN+
AGND
OVDD
OGND
AGNDNCIN–
DVDD
DGND
D8/SDOUT
48 47 46 45 44 39 38 3743 42 41 40
1
AGND
AVDD
NC
BYTESWAP
OB/2C
DGND
DGND
SER/PAR
D0
D1
D2/DIVSCLK[0]
D3/DIVSCLK[1]
NC = NO CONNECT
PIN 1
IDENTIFIER
2
3
4
5
6
7
8
9
10
11
12
13 14 15 16 17 18 19 20 21 22 23 24
D4/EXT/INT
(Not to Scale)
D6/INVSCLK
D5/INVSYNC
D7/RDC/SDIN
AD7623
TOP VIEW
Figure 4. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Type1Description
1, 41, 42 AGND P Analog Power Ground Pin.
2, 44 AVDD P Input Analog Power Pins. Nominally 2.5 V.
3, 40 NC
4 BYTESWAP DI
No Connect.
Parallel Mode Selection (8-Bit/16-Bit). When high, the LSB is output on D[15:8] and the MSB is output
on D[7:0]; when low, the LSB is output on D[7:0] and the MSB is output on D[15:8].
5
OB/2C
DI
Straight Binary/Binary Twos Complement Output. When high, the digital output is straight binary;
when low, the MSB is inverted resulting in a twos complement output from its internal shift register.
6, 7 DGND P
8
SER/PA R
DI
Digital Power Ground.
Serial/Parallel Selection Input. When high, the serial interface is selected and some bits of the data bus
are used as a serial port; the remaining data bits are high impedance outputs. When SER/PA R
the parallel port is selected.
9, 10 D[0:1] DO
11, 12 D[2:3] DI/O
or
DIVSCLK[0:1]
Bit 0 and Bit 1 of the Parallel Port Data Output Bus.
When SER/PA R
When SER/PA R
mode (EXT/INT
= low, these outputs are used as Bit 2 and Bit 3 of the parallel port data output bus.
= high, serial clock division selection. When using serial master read after convert
= low, RDC/SDIN = low), these inputs can be used to slow down the internally
generated serial clock that clocks the data output. In other serial modes, these pins are high
impedance outputs.
13 D4 DI/O
or EXT/INT
When SER/PA R
When SER/PA R
= low, this output is used as Bit 4 of the parallel port data output bus.
= high, serial clock source select. This input is used to select the internally generated
(master ) or external (slave) serial data clock.
When EXT/INT
= low, master mode. The internal serial clock is selected on SCLK output.
When EXT/INT = high, slave mode. The output data is synchronized to an external clock signal, gated
by CS
, connected to the SCLK input.
D9/SCLK
REFGND
D10/SYNC
REF
36
35
34
33
32
31
30
29
28
27
26
25
D11/RDERROR
AGND
CNVST
PD
RESET
CS
RD
DGND
BUSY
D15
D14
D13
D12
05574-004
= low,
14 D5 DI/O
or INVSYNC
When SER/PA R
When SER/PA R
= low, this output is used as Bit 5 of the parallel port data output bus.
= high, invert sync select. In serial master mode (EXT/INT = low), this input is used to
select the active state of the SYNC signal.
When INVSYNC = low, SYNC is active high.
When INVSYNC = high, SYNC is active low.
15 D6 DI/O
When SER/
PA R
= low, this output is used as Bit 6 of the parallel port data output bus.
or INVSCLK Invert SCLK Select. In all serial modes, this input is used to invert the SCLK signal.
Rev. 0 | Page 8 of 28
AD7623
www.BDTIC.com/ADI
Pin No. Mnemonic Type1Description
16 D7 DI/O Bit 7 of the Parallel Port Data Output Bus.
or RDC
or SDIN
17 OGND P Input/Output Interface Digital Power Ground.
18 OVDD P
19 DVDD P Digital Power. Nominally at 2.5 V.
20 DGND P Digital Power Ground.
21 D8 DO
or SDOUT
22 D9 DI/O
or SCLK
23 D10 DO
or SYNC
24 D11 DO
or RDERROR
25 to 28 D[12:15] DO Bit 12 to Bit 15 of the Parallel Port Data Output Bus.
29 BUSY DO
30 DGND P Digital Power Ground.
31
RD
DI
When SER/PA R
used to select the read mode.
When RDC = high, the previous conversion result is read during current conversion and the period of
SCLK changes (see the Master Serial Interface section).
When RDC = low (read after convert), the current result is read after conversion.
Serial Data In. When using serial slave mode, (EXT/INT
daisy-chain the conversion results from two or more ADCs onto a single SDOUT line. The digital data
level on SDIN is output on SDOUT with a delay of 16 SCLK periods after the initiation of the read
sequence.
Input/Output Interface Digital Power. Nominally at the same sup
(2.5 V or 3 V).
When SER/PA R
When SER/PA R
synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7623 provides the
conversion result, MSB first, from its internal shift register. The data format is determined by the logic
level of OB/2C.
In master mode, (EXT/INT
In slave mode, (EXT/INT
When INVSCLK = low, SDOUT is updated on SCLK rising edge and valid on the next falling edge.
When INVSCLK = high, SDOUT is updated on SCLK falling edge and valid on the next rising edge.
Parallel Port Data Output Bus Bit 9. When SER/PA R
data output bus.
Serial Clock. When SER/PAR
clock input or output, dependent on the logic state of the EXT/INT
SDOUT is updated depends on the logic state of the INVSCLK pin.
When SER/PA R
When SER/PA R
used as a digital output frame synchronization for use with the internal data clock.
When a read sequence is initiated and INVSYNC = low
SDOUT output is valid.
When a read sequence is initiated and INVSYNC = high, SYNC is driven low and remains low while
SDOUT output is valid.
Parallel Port Data Output Bus Bit 11. When SER/PA R
port data output bus.
Read Error. When SER/PAR
as an incomplete read error flag. If a data read is started and not completed when the current
conversion is complete, the current data is lost and RDERROR is pulsed high.
Busy Output. Transitions high when a conversion is started, and remains high until the conversion is
omplete and the data is latched into the on-chip shift register. The falling edge of BUSY can be used
c
as a data ready clock signal.
Read Data. When CS
= high, read during convert. When using serial master mode (EXT/INT = low), RDC is
= high), SDIN could be used as a data input to
ply as the supply of the host interface
= low, this output is used as Bit 8 of the parallel port data output bus.
= high, serial data output. In serial mode, this pin is used as the serial data output
= low). SDOUT is valid on both edges of SCLK.
= high):
= low, this output is used as Bit 9 of the parallel port
= high, serial clock. In all serial modes, this pin is used as the serial data
pin. The active edge where the data
= low, this output is used as Bit 10 of the parallel port data output bus.
= high, frame synchronization. In serial master mode (EXT/INT= low), this output is
, SYNC is driven high and remains high while
= low, this output is used as Bit 11 of the parallel
= high, read error. In serial slave mode (EXT/INT = high), this output is used
and RD are both low, the interface parallel or serial output bus is enabled.
32
33 RESET DI
34 PD DI
CS
DI
Chip Select. When CS
also used to gate the external clock in slave serial mode.
Reset Input. When high, reset the AD7623. Current conversion if any is aborted. Falling edge of RESET
enables the cali
not used
Power-Down Input. When high, power down the ADC. Power consumption is reduced and conversions
ar
, this pin can be tied to DGND.
e inhibited after the current one is completed.
and RD are both low, the interface parallel or serial output bus is enabled. CS is
bration mode indicated by pulsing BUSY high. Refer to the Digital Interface section. If
Rev. 0 | Page 9 of 28
Loading...