ANALOG DEVICES AD7622 Service Manual

16-Bit, 1.5 LSB INL, 2 MSPS PulSAR® ADC

FEATURES

Throughput

2 MSPS (wideband warp and warp mode)

1.5 MSPS (normal mode) INL: ±0.5 LSB typical, ±1.5 LSB maximum (±23 ppm of FSR) 16-bit resolution with no missing codes Dynamic range: 92.5 dB typical SINAD: 91 dB minimum @ 20 kHz (V THD: −115 dB typical @ 20 kHz (V

2.048 V internal reference: typical drift Differential input range: ±V

REF

(V No pipeline delay (SAR architecture) Parallel (16-, or 8-bit bus) and serial 5 V/3.3 V/2.5 V interface SPI®/QSPI™/MICROWIRE™/DSP compatible Single 2.5 V supply operation Power dissipation

70 mW typical @ 2 MSPS with internal REF

2 μW in power-down mode Pb-free, 48-lead LQFP and 48-lead LFCSP_VQ Pin compatible with other PulSAR 48-lead ADCs

APPLICATIONS

Medical instruments High speed data acquisition/high dynamic data acquisition Digital signal processing Spectrum analysis Instrumentation Communications AT E

GENERAL DESCRIPTION

The AD7622 is a 16-bit, 2 MSPS, charge redistribution SAR, fully differential, analog-to-digital converter (ADC) that operates from a single 2.5 V power supply. The part contains a high speed, 16-bit sampling ADC, an internal conversion clock, an internal reference (and buffer), error correction circuits, and both serial and parallel system interface ports. It features two very high sampling rate modes (wideband warp and warp) and a fast mode (normal) for asynchronous rate applications. The AD7622 is hardware factory calibrated and tested to ensure ac parameters, such as signal-to-noise ratio (SNR), in addition to the more traditional dc parameters of gain, offset, and linearity. The AD7622 is available in Pb-free only packages with operation specified from −40°C to +85°C.

= 2.5 V)

REF

= 2.5 V)

REF

8 ppm/°C; TEMP output

up to 2.5 V)

REF

AD7622

FUNCTIONAL BLOCK DIAGRAM

REF AMP

SWITCHED

CAP DAC

NORMAL

REF REFG ND

AD7622

INTERFACE

CLOCK

CNVST

Figure 1.

AGND

AVD D

IN+

IN–

PDREF

PDBUF

PD

RESET

REFBUFIN

TEMP

REF

CONTROL LO GIC AND

CALIBRATION CIRCUITRY

WAR P

Table 1. PulSAR 48-Lead ADC Selection

Type/kSPS

Pseudo Differential

100 to 250

AD7651, AD7660, AD7661

500 to 570

AD7650, AD7652, AD7664, AD7666

True Bipolar

AD7610,

AD7665

AD7663

True

AD7675 AD7676 AD7677

Differential

18-Bit Multichannel/

AD7631, AD7678

AD7679

Simultaneous AD7654 AD7655

1.50

1.00

0.50

0

INL (LSB)

–0.50

–1.00

–1.50

0 16384 32768 49152 65536

Figure 2. Integral Nonlinearity vs. Code

POSITIVE INL = +0.43 LSB NEGATIVE INL = –0. 49 LSB

CODE

SERIAL

PORT

PARALLEL

650 to 1000

AD7653, AD7667

AD7612, AD7671

AD7634, AD7674

DGNDDVDD

16

OVDD

OGND

D[15:0]

SER/PAR

BUSY

RD

CS

OB/2C

BYTESWAP

06023-001

>1000

AD7621,

AD7622,

AD7623 AD7641,

AD7643

06023-005

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD7622

REVISION HISTORY

6/06—Revision 0: Initial Version

Ordering Guide .......................................................................... 28

Rev. 0 | Page 2 of 28

AD7622

SPECIFICATIONS

AVDD = DVDD = 2.5 V; OVDD = 2.3 V to 3.6 V; V

Table 2.

Parameter Conditions Min Typ Max Unit

RESOLUTION 16 Bits ANALOG INPUT

Voltage Range V Operating Input Voltage V

IN+

Analog Input CMRR fIN = 100 kHz 58 dB Input Current 2 MSPS throughput 3.5 μA Input Impedance

2

THROUGHPUT SPEED

Complete Cycle Wideband warp, warp modes 500 ns Throughput Rate Wideband warp, warp modes 0.001 2 MSPS Time Between Conversions Wideband warp, warp modes 1 ms Complete Cycle Normal mode 667 ns Throughput Rate Normal mode 0 1.5 MSPS

DC ACCURACY

Integral Linearity Error

3

T

MIN

No Missing Codes 16 Bits Differential Linearity Error −1 +1.25 LSB Transition Noise V Transition Noise V Zero Error, T

MIN

to T

MAX

5

REF

−10 +10 LSB Zero Error Temperature Drift ±0.5 ppm/°C Gain Error, T

MIN

to T

MAX

5

−8 +8 LSB Gain Error Temperature Drift ±0.5 ppm/°C Power Supply Sensitivity AVDD = 2.5 V ± 5% ±4 LSB

AC ACCURACY

Dynamic Range V

REF

Signal-to-Noise fIN = 20 kHz, V f f

= 20 kHz, V

IN

= 100 kHz, V

IN

Spurious-Free Dynamic Range fIN = 20 kHz, V f f

= 20 kHz, V

IN

= 100 kHz, V

IN

Total Harmonic Distortion fIN = 20 kHz, V f f

= 20 kHz, V

IN

= 100 kHz, V

IN

Signal-to-(Noise + Distortion) fIN = 20 kHz, V f f

= 20 kHz, V

IN

= 100 kHz, V

IN

−3 dB Input Bandwidth 50 MHz

SAMPLING DYNAMICS

Aperture Delay 1 ns Aperture Jitter 5 ps rms Transient Response Full-scale step 140 ns

INTERNAL REFERENCE PDREF = PDBUF = low

Output Voltage REF @ 25°C 2.038 2.048 2.058 V Temperature Drift −40°C to +85°C ±8 ppm/°C Line Regulation AVDD = 2.5 V ± 5% ±15 ppm/V Turn-On Settling Time C

REF

= 2.5 V; all specifications T

REF

− V

IN−

, V

to AGND −0.1 AVDD

IN−

to T

= −40°C to +85°C −1.5 ±0.5 +1.5 LSB

MAX

MIN

−V

to T

REF

, unless otherwise noted.

MAX

+V

REF

1

V

= 2.5 V 0.5 LSB = 2.048 V 0.6 LSB

= 2.5 V 91.5 92.5 dB

= 2.5 V 91 92 dB

REF

= 2.048 V 89.5 90.5 dB

REF

= 2.5 V 91 dB

REF

= 2.5 V 117 dB

REF

= 2.048 V 110 dB

REF

= 2.5 V 101 dB

REF

= 2.5 V −115 dB

REF

= 2.048 V −109 dB

REF

= 2.5 V −100 dB

REF

= 2.5 V 91 92 dB

REF

= 2.048 V 89.5 90.5 dB

REF

= 2.5 V 91 dB

REF

= 10 μF 5 ms

4

6

Rev. 0 | Page 3 of 28

AD7622

Parameter Conditions Min Typ Max Unit

REFBUFIN Output Voltage REFBUFIN @ 25°C 1.19 V REFBUFIN Output Resistance 6.33 kΩ

EXTERNAL REFERENCE PDREF = PDBUF = high

Voltage Range REF 1.8 2.5 AVDD + 0.1 V Current Drain 2 MSPS throughput 150 μA

REFERENCE BUFFER PDREF = high, PDBUF = low

REFBUFIN Input Voltage Range REF = 2.048 V typ 1.05 1.2 1.30 V REFBUFIN Input Current REFBUFIN = 1.2 V 1 nA

TEMPERATURE PIN

Voltage Output @ 25°C 278 mV Temperature Sensitivity 1 mV/°C Output Resistance 4.7 kΩ

DIGITAL INPUTS

Logic Levels

V

IL

V

IH

I

IL

I

IH

DIGITAL OUTPUTS

Data Format7 Pipeline Delay

V

OL

V

OH

8

POWER SUPPLIES

Specified Performance

AVDD 2.37 2.5 2.63 V DVDD 2.37 2.5 2.63 V OVDD 2.30

Operating Current

11

AVD D

10

AVDD Without internal reference 23 mA DVDD 2.5 mA

12

OVDD

Power Dissipation

With Internal Reference Without Internal Reference

In Power-Down Mode

TEMPERATURE RANGE

11

10

12

13

Specified Performance T

1

When using an external reference. With the internal reference, the input range is −0.1 V to V

2

See Analog Inputs section.

3

Linearity is tested using endpoints, not best fit.

4

LSB means least significant bit. With the ±2.048 V input range, 1 LSB is 62.5 μV.

5

See Voltage Reference Input section. These specifications do not include the error contribution from the external reference.

6

All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified.

7

Parallel or serial 16-bit.

8

Conversion results are available immediately after completed conversion.

9

See the Absolute Maximum Ratings section.

10

In wideband and warp modes. Tested in parallel reading mode.

11

With internal reference, PDREF and PDBUF are low; without internal reference, PDREF and PDBUF are high.

12

With all digital inputs forced to OVDD.

13

Consult sales for extended temperature range.

−0.3 +0.6 V

1.7 5.25 V

−1 +1 μA

I

= 500 μA 0.4 V

SINK

I

= −500 μA OVDD − 0.3 V

SOURCE

9

3.6 V 2 MSPS throughput With internal reference 24 mA

1 mA

2 MSPS throughput 70 85 mW 2 MSPS throughput 65 80 mW PD = high 2 μW

MIN

to T

MAX

−40 +85 °C

.

REF

Rev. 0 | Page 4 of 28

AD7622

TIMING SPECIFICATIONS

AVDD = DVDD = 2.5 V; OVDD = 2.3 V to 3.6 V; V

Table 3.

Parameter Symbol Min Typ Max Unit

CONVERSION AND RESET (Refer to Figure 31 and Figure 32)

Convert Pulse Width t Time Between Conversions (Warp Mode2/Normal Mode3) t CNVST

Low to BUSY High Delay

BUSY High All Modes (Except Master Serial Read After Convert)

Warp Mode/Normal Mode t Aperture Delay t End of Conversion to BUSY Low Delay t Conversion Time (Warp Mode/Normal Mode) t Acquisition Time (Warp Mode/Normal Mode) t RESET Pulse Width t RESET Low to BUSY High Delay BUSY High Time from RESET Low

4

PARALLEL INTERFACE MODES (Refer to Figure 33 to Figure 36 )

CNVST

Low to Data Valid Delay (Warp Mode/Normal Mode) Data Valid to BUSY Low Delay t Bus Access Request to Data Valid t Bus Relinquish Time t

MASTER SERIAL INTERFACE MODES5 (Refer to Figure 37 and Figure 38)

CS

Low to SYNC Valid Delay

CS

Low to Internal SCLK Valid Delay

CS

Low to SDOUT Delay

CNVST

Low to SYNC Delay (Warp Mode/Normal Mode)

5

SYNC Asserted to SCLK First Edge Delay t Internal SCLK Period Internal SCLK High Internal SCLK Low SDOUT Valid Setup Time SDOUT Valid Hold Time SCLK Last Edge to SYNC Delay CS

High to SYNC HI-Z

CS

High to Internal SCLK HI-Z

CS

High to SDOUT HI-Z

6

BUSY High in Master Serial Read After Convert CNVST

Low to SYNC Asserted Delay (Warp Mode/Normal Mode) SYNC Deasserted to BUSY Low Delay t

SLAVE SERIAL INTERFACE MODES (Refer to Figure 40 and Figure 41)

External SCLK Setup Time t External SCLK Active Edge to SDOUT Delay t SDIN Setup Time t SDIN Hold Time t External SCLK Period t External SCLK High t External SCLK Low t

See Notes on next page.

= 2.5 V; all specifications T

REF

6

to T

MIN

1

2

t

3

4

5

6

7

8

9

t

38

t

39

t

10

11

12

13

t

14

t

15

t

16

t

17

18

t

19

t

20

t

21

t

22

t

23

t

24

t

25

t

26

t

27

t

28

t

29

30

31

32

33

34

35

36

37

, unless otherwise noted.

MAX

15 70

1

ns 500/667 ns 23 ns

360/485 ns 1 ns 10 ns 360/485 ns 140/182 ns 15 ns 10 ns 500 ns

360/485 ns 2 ns

20 ns 2 15 ns

10 ns 10 ns 10 ns 15/135 ns 2 ns

8 20 ns 2 ns 3 ns 1 ns 0 ns 0 ns 10 ns

10 ns 10 ns See Table 4 ns

375/500 ns 13 ns

5 ns 1 8 ns 5 ns 5 ns

12.5 ns 5 ns 5 ns

Rev. 0 | Page 5 of 28

AD7622

1

See the Conversion Control section.

2

All timings for wideband warp mode are the same as warp mode.

3

In warp mode only, the maximum time between conversions is 1 ms; otherwise, there is no required maximum time.

4

See the Digital Interface section and the RESET section.

5

In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.

6

In serial master read during convert mode. See Table 4 for serial master read after convert mode timing specifications.

Table 4. Serial Clock Timings in Master Read After Convert Mode

DIVSCLK[1] 0 0 1 1 DIVSCLK[0] Symbol 0 1 0 1 Unit

SYNC to SCLK First Edge Delay Minimum t Internal SCLK Period Minimum t Internal SCLK Period Maximum t Internal SCLK High Minimum t Internal SCLK Low Minimum t SDOUT Valid Setup Time Minimum t SDOUT Valid Hold Time Minimum t SCLK Last Edge to SYNC Delay Minimum t

18

19

20

21

22

23

24

BUSY High Width Maximum

Warp Mode t Normal Mode t

28

3 3 3 3 ns 8 16 32 64 ns 20 40 60 140 ns 2 8 16 32 ns 2 8 16 32 ns 1 5 15 5 ns 0 0.5 10 28 ns 0 0.5 9 26 ns

0.64 0.92 1.47 2.57 μs

0.76 1.04 1.59 2.69 μs

500µA I

TO OUTPUT

C

L

50pF

500µA I

NOTE IN SERIAL INT ERFACE MODES, THE S YNC, SCLK, AND SDOUT TI MING ARE DEFINED WIT H A MAXIMUM LOAD

OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.

C

L

OL

1.4V

OH

Figure 3. Load Circuit for Digital Interface Timing,

SDOUT, SYNC, and SCLK Outputs, C

= 10 pF

L

0.8V

t

DELAY

2V

0.8V

6023-002

Figure 4. Voltage Reference Levels for Timing

2V

t

DELAY

2V

0.8V

6023-003

Rev. 0 | Page 6 of 28

AD7622

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Rating

Analog Inputs/Outputs

IN+1, IN−, REF, REFBUFIN, TEMP,

INGND, REFGND to AGND

AVDD + 0.3 V to AGND − 0.3 V

Ground Voltage Differences

AGND, DGND, OGND ±0.3 V

Supply Voltages

AVDD, DVDD −0.3 V to +2.7 V OVDD −0.3 V to +3.8 V AVDD to DVDD ±2.8 V

AVDD, DVDD to OVDD −3.8 V to +2.8 V Digital Inputs −0.3 V to +5.5 V PDREF, PDBUF Internal Power Dissipation Internal Power Dissipation

2

3

4

±20 mA 700 mW

2.5 W Junction Temperature 125°C Storage Temperature Range –65°C to +125°C

1

See Analog Inputs section.

2

See Voltage Reference Input section.

3

Specification is for the device in free air:

48-Lead LQFP; θJA = 91°C/W, θJC = 30°C/W.

4

Specification is for the device in free air:

48-Lead LFCSP; θJA = 26°C/W.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. 0 | Page 7 of 28

AD7622

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PDBUF

PDREF

REFBUFIN

TEMP

AVD D

IN+

AGND

AGNDNCIN–

REFGND

48 47 46 45 44 39 38 3743 42 41 40

1

AGND

AVD D

DGND

BYTESWAP

OB/2C

WAR P

NORMAL

SER/PAR

D0

D1

D2/DIVSCL K[0] D3/DIVSCL K[1]

NC = NO CONNECT

PIN 1 IDENTIFIER

2

3

4

5

6

7

8

9

10

11

12

13 14 15 16 17 18 19 20 21 22 23 24

D4/EXT/INT

D6/INVSCLK

D5/INVSYNC

AD7622

TOP VIEW

(Not to Scale)

DVDD

OVDD

OGND

D7/RDC/SDIN

Figure 5. Pin Configuration

Table 6. Pin Function Descriptions

Pin No.

1, 36,

Mnemonic Type

AGND P Analog Power Ground.

1

Description

41, 42 2, 44 AVDD P Input Analog Power Pins. Nominally 2.5 V. 3 DGND P Digital Power Ground. 4 BYTESWAP DI

Parallel Mode Selection (8-Bit/16-Bit). When high, the LSB is output on D[15:8] and the MSB is output on D[7:0]; when low, the LSB is output on D[7:0] and the MSB is output on D[15:8].

5

OB/

2C

DI

Straight Binary/Binary Twos Complement Output. When high, the digital output is straight binary; when low, the MSB is inverted resulting in a twos complement output from its internal shift register.

6 WARP DI

Conversion Mode Selection. When WARP = high and mode with slightly improved linearity and THD. When WARP = high and warp mode. In either mode, these are the fastest modes; maximum throughput is achievable, and

a minimum conversion rate must be applied to guarantee full specified accuracy.

7

NORMAL

DI

Conversion Mode Selection. When

NORMAL = low and WARP = low, this input selects normal mode

where full accuracy is maintained independent of the minimum conversion rate.

8

SER/

PA R

DI/O Serial/Parallel Selection Input.

When SER/

PA R = high, the serial interface is selected and some bits of the data bus are used as a

serial port; the remaining data bits are high impedance outputs.

9, 10 D[0:1] DO

When SER/ Bit 0 and Bit 1 of the Parallel Port Data Output Bus. These pins are always outputs, regardless of

PA R = low, the parallel port is selected.

the interface mode. 11, 12 D[2:3] DI/O or DIVSCLK[0:1]

When SER/

(EXT/

PA R = low, these outputs are used as Bit 2 and Bit 3 of the parallel port data output bus. PA R = high, serial clock division selection. When using serial master read after convert mode

INT = low, RDC/SDIN = low), these inputs can be used to slow down the internally generated

serial clock that clocks the data output. In other serial modes, these pins are high impedance outputs. 13 D4 DI/O

or EXT/

INT

When SER/

PA R = low, this output is used as Bit 4 of the parallel port data output bus. PA R = high, serial clock source select. This input is used to select the internally generated

(master) or external (slave) serial data clock.

When EXT/

INT = low, master mode. The internal serial clock is selected on SCLK output. INT = high, slave mode. The output data is synchronized to an external clock signal,

gated by CS, connected to the SCLK input.

DGND

REF

36

AGND

CNVST

35

34

PD

33

RESET

32

CS

31

RD

30

DGND

29

BUSY

28

D15

27

D14

26

D13

25

D12

D9/SCLK

D10/SYNC

D8/SDOUT

06023-004

D11/RDERROR

NORMAL = high, this selects wideband warp

NORMAL = low, this selects

Rev. 0 | Page 8 of 28

AD7622

Pin No. Mnemonic Type

14 D5 DI/O or INVSYNC

15 D6 DI/O or INVSCLK

16 D7 DI/O or RDC

or SDIN

17 OGND P Input/Output Interface Digital Power Ground. 18 OVDD P

19 DVDD P Digital Power. Nominally at 2.5 V. 20 DGND P Digital Power Ground. 21 D8 DO

or SDOUT

22 D9 DI/O or SCLK

23 D10 DO or SYNC

24 D11 DO or RDERROR

25 to

D[12:15] DO

28 29 BUSY DO

30 DGND P Digital Power Ground.

1

Description

When SER/ When SER/

PA R = low, this output is used as Bit 5 of the parallel port data output bus.

PA R = high, invert sync select. In serial master mode (EXT/INT = low), this input is used to select the active state of the SYNC signal. When INVSYNC = low, SYNC is active high.

When INVSYNC = high, SYNC is active low. When SER/ When SER/

PA R = low, this output is used as Bit 6 of the parallel port data output bus.

PA R] = high, invert SCLK select. In all serial modes, this input is used to invert the SCLK signal.

When SER/ When SER/

PA R = low, this output is used as bit 7 of the parallel port data output bus.

PA R = high, read during convert. When using serial master mode (EXT/INT = low), RDC is used to select the read mode.

When RDC = high, the previous conversion result is output on SDOUT during conversion and the period of SCLK changes (see the

Master Serial Interface section).

When RDC = low (read after convert), the current result can be output on SDOUT only when the conversion is complete.

When SER/

PA R = low, serial data in. When using serial slave mode, (EXT/INT = high), SDIN could be used as a data input to daisy-chain the conversion results from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on SDOUT with a delay of 16 SCLK periods after

the initiation of the read sequence. If not used, connect to OVDD or OGND.

Input/Output Interface Digital Power. Nominally at the same supply as the supply of the host interface (2.5 V or 3 V).

When SER/ When SER/

PA R = low, this output is used as Bit 8 of the parallel port data output bus.

PA R = high, serial data output. In serial mode, this pin is used as the serial data output synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7622 provides the

conversion result, MSB first, from its internal shift register. The data format is determined by the logic level of OB/2C.

In master mode, EXT/ In slave mode, EXT/

INT = low, SDOUT is valid on both edges of SCLK.

INT = high: When INVSCLK = low, SDOUT is updated on SCLK rising edge and valid on the next falling edge. When INVSCLK = high, SDOUT is updated on SCLK falling edge and valid on the next rising edge.

When SER/ When SER/

data clock input or output, depending upon the logic state of the EXT/

PA R = low, this output is used as Bit 9 of the parallel port data output bus. PA R = high, serial clock. In all serial modes, this pin is used as the serial

INT pin. The active edge

where the data SDOUT is updated, depends on the logic state of the INVSCLK pin. When SER/ When SER/

PA R = low, this output is used as Bit 10 of the parallel port data output bus. PA R = high, frame synchronization. In serial master mode (EXT/INT= low),

this output is used as a digital output frame synchronization for use with the internal data clock. When a read sequence is initiated and INVSYNC = low, SYNC is driven high and remains high

while SDOUT output is valid. When a read sequence is initiated and INVSYNC = high, SYNC is driven low and remains low

while SDOUT output is valid. When SER/ When SER/

PA R = low, this output is used as Bit 11 of the parallel port data output bus.

PA R = high, read error. In serial slave mode (EXT/INT = high), this output is used as an incomplete read error flag. If a data read is started and not completed when the current conversion is complete, the current data is lost and RDERROR is pulsed high.

Bit 12 to Bit 15 of the parallel port data output bus. These pins are always outputs, regardless of the interface mode.

Busy Output. Transitions high when a conversion is started and remains high until the conversion is complete and the data is latched into the on-chip shift register. The falling edge of BUSY can be used as a data-ready clock signal.

2

Rev. 0 | Page 9 of 28

ANALOG DEVICES AD7622 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

TIMING SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS