Analog Devices AD7621 pre Datasheet
16-Bit, 1 LSB INL, 3 MSPS PulSAR® ADC
Preliminary Technical Data
FEATURES
Throughput:
3 MSPS (Wideband Warp and Warp mode)
2 MSPS (Normal mode)
1.25 MSPS (Impulse mode)
2.048V internal reference.
(V
Differential input range: ±V
INL: ±2 LSB max; ± 1 LSB typ
16-bit resolution with no missing codes
SINAD: 87 dB Typ @ 100 kHz
THD: -103 dB Typ @ 100 kHz
No pipeline delay ( SAR architecture )
Parallel (16- or 8-bit bus) and serial 5 V/3.3 V/2.5 V interface
SPI®/QSPI™/MICROWIRE™/DSP compatible
Single 2.5 V supply operation
Power dissipation: 75 mW Typ @ 3 MSPS
48-lead LQFP and 48-lead LFCSP packages
Speed upgrade of the AD7677
APPLICATIONS
Medical instruments
High speed data acquisition
Digital signal porcessing
Communications
Instrumentation
Spectrum analysis
ATE
GENERAL DESCRIPTION
The AD7621 is a 16-bit, 3 MSPS, charge redistribution SAR,
fully differential analog-to-digital converter that operates from
a single 2.5 V power supply. The part contains a high-speed 16bit sampling ADC, an internal conversion clock, an internal
reference (and buffer), error correction circuits, and both serial
and parallel system interface ports. It features a very high
sampling rate mode (Wideband Warp) for undersampling
applications, a fast mode (Normal) for asynchronous rate
applications, and for reduced power mode (Impulse) for low
power applications where the power is scaled with the
throughput. The AD7621 is hardware factory-calibrated and
comprehensively tested to ensure ac parameters such as signalto-noise ratio (SNR) and total harmonic distortion (THD) in
addition to the more traditional dc parameters of gain, offset,
and linearity. Operation is specified from –40°C to +85°C.
REF
up to 2.5V)
REF
AD7621
FUNCTIONAL BLOCK DIAGRAM
REF AMP
SWITCHED
CAP DAC
IMPULSE
REF REFGND
AD7621
CLOCK
CNVST
Figure 1.
AGND
AVDD
IN+
IN-
PDREF
PDBUF
PD
RESET
TEMP
REFBUFIN
REF
CONTROL LOGIC AND
CALIBRATION CIRCUITRY
WARP
Table 1. PulSAR® Selection
Type / kSPS 100 - 250 500 - 570
Pseudo
Differential
AD7651
AD7660/61
AD7650/52
AD7664/66
True Bipolar AD7663 AD7665 AD7671
True
Differential
AD7675 AD7676 AD7677 AD7621
18 Bit AD7678 AD7679 AD7674 AD7641
Multichannel/
Simultaneous
AD7654
PRODUCT HIGHLIGHTS
1. Fast Throughput
The AD7621 is a 3 MSPS, charge redistribution, 16-bit SAR
ADC with internal error correction circuitry.
2. Superior INL
The AD7621 has a maximum integral nonlinearity of 2
LSB with no missing 16-bit code.
3. Internal Reference
The AD7621 has a 2.048V internal reference.
4. Single-Supply Operation
The AD7621 operates from a single 2.5 V supply and
typically dissipates only 108 mW. In impulse mode, its
power dissipation decreases with the throughput.
5. Serial or Parallel Interface
Versatile parallel (16 or 8 bits bus) or 2-wire serial interface
arrangement compatible with either 2.5V, 3.3V or 5 V logic.
DGNDDVDD
SERIAL
PORT
16
PARALLEL
INTERFACE
800 1000 >1000
AD7653
AD7667
AD7655
OVDD
OGND
D[15:0]
SER/PAR
BUSY
RD
CS
OB/2C
BYTESWAP
xxxxx-x-001
Rev. PrE
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
AD7621 Preliminary Technical Data
TABLE OF CONTENTS
Specifications..................................................................................... 3
Voltage Reference Input ............................................................19
Timing Specifications....................................................................... 5
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Te r m in o l o g y .................................................................................... 11
Typical Performance Characteristics........................................... 12
Applications Information ..............................................................16
Circuit Information.................................................................... 16
Converter Operation.................................................................. 16
Modes of Operation ...................................................................16
Transfer Fu nctions...................................................................... 17
Typical Connection Diag ram ................................................... 18
Analog Inputs.............................................................................. 18
Driver Amplifier Choice............................................................ 18
Power Supply............................................................................... 20
Power Dissipation vs. Throughput........................................... 20
Conversion Control................................................................... 21
Digital Interface.......................................................................... 21
Parallel Interface ......................................................................... 22
Serial interface ............................................................................ 22
Master Serial Interface............................................................... 23
Slave Serial Interface .................................................................. 24
Microprocessor Interfacing....................................................... 26
Application Hints ........................................................................... 27
Layout .......................................................................................... 27
Evaluating the AD7621 Performance...................................... 27
Outline Dimensions....................................................................... 28
Ordering Guide .......................................................................... 28
REVISION HISTORY
Revision PrE: Preliminary Version
Rev. PrE | Page 2 of 28
Preliminary Technical Data AD7621
SPECIFICATIONS
Table 2. (AVDD = DVDD = 2.5V; OVDD = 2.5V to 3.3V; V
Parameter Conditions Min Typ Max Unit
RESOLUTION 16 Bits
ANALOG INPUT
Voltage Range V
Operating Input Voltage V
– V
IN+
IN-
to AGND –0.1 AVDD
IN+, VIN-
Analog Input CMRR fIN = 100 kHz 55 dB
Input Current 3 MSPS Throughput 50 µA
Input Impedance
2
THROUGHPUT SPEED
Complete Cycle In Wideband Warp Mode 333 ns
Throughput Rate In Wideband Warp Mode 0.1 3 MSPS
Throughput Rate In Warp Mode 0.001 3 MSPS
Time between Conversions In Warp Mode 1 ms
Complete Cycle In Normal Mode 500 µs
Throughput Rate In Normal Mode 0 2 MSPS
Complete Cycle In Impulse Mode 800 µs
Throughput Rate In Impulse Mode 0 1.25 MSPS
DC ACCURACY
Integral Linearity Error -2 ±1 +2 LSB
No Missing Codes 16 Bits
Differential Linearity Error -1 +2 LSB
Transition Noise V
Zero Error, T
MIN
to T
MAX
4
= AVDD 0.76 LSB
REF
±30 LSB
Zero Error Temperature Drift ±1.0 ppm/°C
Gain Error, T
MIN
to T
MAX
4
REF = 2.5 V ±0.40 % of FSR
Gain Error Temperature Drift ±1.0 ppm/°C
Power Supply Sensitivity AVDD = 2.5 V ± 5% ±3 LSB
AC ACCURACY
Signal-to-Noise fIN = 20kHz, V
f
= 100kHz, V
IN
Spurious Free Dynamic Range fIN = 20 kHz 105 dB
f
= 100kHz 103 dB
IN
Total Harmonic Distortion fIN = 20 kHz –105 dB
f
= 100kHz -103 dB
IN
Signal-to-(Noise + Distortion) fIN = 20 kHz 89 dB
f
= 100kHz 87 dB
IN
–60 dB Input, fIN = 20 kHz 30 dB
–3 dB Input Bandwidth 50 MHz
SAMPLING DYNAMICS
Aperture Delay 1 ns
Aperture Jitter 5 ps rms
Transient Response Full-Scale Step 50 ns
INTERNAL REFERENCE PDREF = PDBUF = LOW
Output Voltage @ 25°C 2.048 V
Output Voltage Hysteresis –40°C to +85°C 50 ppm
Temperature Drift –40°C to +85°C ±3 ppm/°C
Long-Term Drift 100 ppm/1000 Hours
Line Regulation AVDD = 2.5 V ± 5% ±15 ppm/V
Turn-On Settling Time C
= 10 µF 5 ms
REF
= 2.5V; all specifications T
REF
-V
REF
= AVDD 89.5 dB
REF
= AVDD 87.5 dB
REF
to T
MIN
V
unless otherwise noted.)
MAX
REF
1
V
V
3
5
Rev. PrE | Page 3 of 28
AD7621 Preliminary Technical Data
Parameter Conditions Min Typ Max Unit
Bandgap (REFBUFIN) Output Voltage 1.2 V
Bandgap (REFBUFIN) Output Resistance 6.33 kΩ
EXTERNAL REFERENCE PDREF = PDBUF = HIGH
Voltage Range 1.8 2.048 AVDD + 0.1 V
Current Drain 3 MSPS Throughput 270 µA
REFERENCE BUFFER PDREF = HIGH, PDBUF = LOW
Input Voltage Range 1.05 1.2 1.52 V
TEMPERATURE PIN @ 25°C
Voltage Output 300 mV
Temperature Sensitivity 1 mV/°C
Output Resistance 4.7 kΩ
DIGITAL INPUTS
Logic Levels
V
IL
V
IH
I
IL
I
IH
DIGITAL OUTPUTS
Data Format
Pipeline Delay
V
OL
V
OH
6
7
POWER SUPPLIES
Specified Performance
AVDD 2.37 2.5 2.63 V
DVDD 2.37 2.5 2.63 V
OVDD 2.30 3.6 V
Operating Current
9
AVDD
10
DVDD
8
OVDD9 1 mA
Power Dissipation
8,
With REF
Without REF
With REF
Without REF
8
8,
8
8, 9
1.25MSPS Throughput 43 mW
8, 9
1.25 MSPS Throughput 37 mW
In Power-Down Mode PD = HIGH 140 µW
TEMPERATURE RANGE
11
Specified Performance T
1
When using an external reference. With the internal reference, the input range is from -0.1V to V
2
See An section. alog Inputs
3
LSB means least significant bit. With the ±2.048 V input range, 1 LSB is 62.5 µV.
4
See Vo section. These specifications do not include the error contribution from the external reference. ltage Reference Input
5
All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified.
6
Parallel or serial 16-bit.
7
Conversion results are available immediately after completed conversion.
8
In Warp mode.
9
With REF, PDREF and PDBUF are LOW; without REF, PDREF and PDBUF are HIGH.
10
Impulse mode. Tested in parallel reading mode
11
Consult factory for extended temperature range.
–0.3 +0.6 V
1.7 5.25 V
–1 +1 µA
–1 +1 µA
I
= 500 µA 0.4 V
SINK
I
= –500 µA OVDD – 0.3 V
SOURCE
3 MSPS Throughput
With Reference and Buffer 24 mA
4.5 mA
3 MSPS Throughput 75 mW
3 MSPS Throughput 65 mW
MIN
to T
MAX
–40 +85 °C
.
REF
Rev. PrE | Page 4 of 28
Preliminary Technical Data AD7621
TIMING SPECIFICATIONS
Table 3. (AVDD = DVDD = 2.5V; OVDD = 2.5V to 3.3V; V
Parameter Symbol Min Typ Max Unit
Refer to Figure 34 and Figure 35
Convert Pulse Width t
Time between Conversions (Warp Mode/Normal Mode/Impulse Mode)1t
CNVST Low to BUSY High Delay
BUSY High All Modes (except Master Serial Read after Convert) t
Aperture Delay t
End of Conversion to BUSY Low Delay t
Conversion Time t
Acquisition Time t
RESET Pulse Width t
Refer to Figure 36, Figure 37, and Figure 38 (Parallel Interface Modes)
CNVST Low to DATA Valid Delay
DATA Valid to BUSY Low Delay t
Bus Access Request to DATA Valid t
Bus Relinquish Time t
Refer to Figure 40 and Figure 41 (Master Serial Interface Modes)
CS Low to SYNC Valid Delay
CS Low to Internal SCLK Valid Delay2
CS Low to SDOUT Delay
CNVST Low to SYNC Delay
SYNC Asserted to SCLK First Edge Delay t
Internal SCLK Period
3
Internal SCLK High3 t
Internal SCLK Low3 t
SDOUT Valid Setup Time3 t
SDOUT Valid Hold Time3 t
SCLK Last Edge to SYNC Delay3 t
CS High to SYNC HI-Z
CS High to Internal SCLK HI-Z
CS High to SDOUT HI-Z
BUSY High in Master Serial Read after Convert3 t
CNVST Low to SYNC Asserted Delay (all Modes)
SYNC Deasserted to BUSY Low Delay t
Refer to Figure 43 and Figure 44 (Slave Serial Interface Modes)2
External SCLK Setup Time t
External SCLK Active Edge to SDOUT Delay t
SDIN Setup Time t
SDIN Hold Time t
External SCLK Period t
External SCLK High t
External SCLK Low t
1
In Warp mode only, the time between conversions is 1ms; otherwise there is no required maximum time.
2
In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.
3
In Serial Master Read During Convert mode. See
Table 4 for Serial Master Read After Convert Mode
= 2.5V; all specifications T
REF
1
2
t
3
4
5
6
7
8
9
t
10
11
12
2
13
t
14
t
15
t
16
t
17
18
t
19
20
21
22
23
24
t
25
t
26
t
27
28
t
29
30
31
32
33
34
35
36
37
MIN
to T
unless otherwise noted.)
MAX
5 ns
333/500/800 ns
30 ns
263/400/750 ns
1 ns
10 ns
263/400/750 Ns
70/100/50 ns
10 ns
263/400/750 µs
20 ns
40 ns
2 17? ns
10 ns
10 ns
10 ns
12/137/263 ns
3 ns
12 40 ns
4 ns
4 ns
2 ns
1 ns
0 ns
10 ns
10 ns
10 ns
See Table 4
263/400/750 µs
13 ns
5 ns
2 7 ns
5 ns
5 ns
12.5 ns
5 ns
5 ns
Rev. PrE | Page 5 of 28
AD7621 Preliminary Technical Data
Table 4. Serial Clock Timings in Master Read After Convert Mode
DIVSCLK[1] 0 0 1 1
DIVSCLK[0] Symbol 0 1 0 1 Unit
SYNC to SCLK First Edge Delay Minimum t
Internal SCLK Period Minimum t
Internal SCLK Period Maximum t
Internal SCLK High Minimum t
Internal SCLK Low Minimum t
SDOUT Valid Setup Time Minimum t
SDOUT Valid Hold Time Minimum t
SCLK Last Edge to SYNC Delay Minimum t
BUSY High Width Maximum t
18
19
19
20
21
22
23
24
24
TBD TBD TBD TBD ns
TBD TBD TBD TBD ns
TBD TBD TBD TBD ns
TBD TBD TBD TBD ns
TBD TBD TBD TBD ns
TBD TBD TBD TBD ns
TBD TBD TBD TBD ns
TBD TBD TBD TBD ns
TBD TBD TBD TBD µs
Rev. PrE | Page 6 of 28
Preliminary Technical Data AD7621
ABSOLUTE MAXIMUM RATINGS
Table 5. AD7621 Stress Ratings
Parameter Rating
Analog Inputs/Outputs
IN+2, IN-, REF, REFBUFIN, TEMP,
INGND, REFGND to AGND
Ground Voltage Differences
AGND, DGND, OGND ±0.3 V
Supply Voltages
AVDD, DVDD –0.3 V to +2.7 V
OVDD –0.3 V to +3.8 V
Digital Inputs –0.3 V to 5.5 V
PDREF, PDBUF
3
Internal Power Dissipation
Internal Power Dissipation
Junction Temperature 150°C
Storage Temperature Range –65°C to +150°C
Lead Temperature Range
(Soldering 10 sec) 300°C
1
Stresses above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional
operation of the device at these or any other conditions above those listed
in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device
reliability.
2
See section. Analog Inputs
3
See the Voltage Reference Input section.
4
Specification is for the device in free air:
48-Lead LQFP; θ
5
Specification is for the device in free air:
48-Lead LFCSP; θ
= 91°C/W, θJC = 30°C/W.
JA
= 26°C/W
JA
1
AVDD + 0.3 V to
AGND – 0.3 V
±TBDm
4
5
700 mW
2.5 W
500µA
TO OUTPUT
PIN
*IN SERIAL INTERFACE MODES,THE SYNC, SCLK, AND
SDOUT TIMINGS ARE DEFINEDWITH A MAXIMUM LOAD
OF 10pF; OTHERWISE,THE LOAD IS 60pF MAXIMUM.
C
L
50pF
C
L
*
500µA
I
OL
I
OH
Figure 2. Load Circuit for Digital Interface Timing,
SDOUT, SYNC, SCLK Outputs C
2V
0.8V
t
DELAY
2V
0.8V
Figure 3. Voltage Reference Levels for Timing
= 10 pF
L
t
DELAY
2V
0.8V
1.4V
-002
-003
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
this product features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
Rev. PrE | Page 7 of 28
AD7621 Preliminary Technical Data
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PDBUF
PDREF
REFBUFIN
TEMP
AVDD
IN+
AGND
19 20
DVDD
OVDD
AGNDNCIN-
DGND
AGND
AVDD
NC
BYTESWAP
OB/2C
WARP
IMPULSE
SER/PAR
D0
D1
D2/DIVSCLK[0]
D3/DIVSCLK[1]
NC = NO CONNECT
48
47 46 45 44 39 38 3743 42 41 40
1
PIN 1
2
IDENTIFIER
3
4
5
6
7
8
9
10
11
12
13 14
15 16 17 18
D4/EXT/INT
D6/INVSCLK
D5/INVSYNC
AD7621
TOP VIEW
(Not to Scale)
OGND
D7/RDC/SDIN
Figure 4. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Type1 Description
1, 41, 42 AGND P Analog Power Ground Pin.
2, 44 AVDD P Input Analog Power Pins. Nominally 2.5 V.
3, 40 NC No Connect.
4 BYTESWAP DI
Parallel Mode Selection (8-bit/16-bit). When HIGH, the LSB is output on D[15:8] and the MSB is output
on D[7:0]; when LOW, the LSB is output on D[7:0] and the MSB is output on D[15:8].
5
OB/
2C
DI
Straight Binary/Binary Two’s Complement Output. When HIGH, the digital output is straight binary;
when LOW, the MSB is inverted resulting in a two’s complement output from its internal shift register.
6 WARP DI
Conversion Mode Selection. When WARP = HIGH and IMPULSE = LOW, this input selects the fastest
mode, Warp; the maximum throughput is achievable, and a minimum conversion rate must be
applied in order to guarantee full specified accuracy. When WARP = LOW and IMPULSE = LOW this
input selects NORMAL mode where full accuracy is maintained independent of the minimum
conversion rate.
7 IMPULSE DI
Conversion Mode Selection. When IMPULSE = HIGH and WARP = LOW, this input selects Impulse
mode, a reduced power mode. In this mode, the power dissipation is approximately proportional to
the sampling rate.
8
SER/
PAR
DI
Serial/Parallel Selection Input. When SER/
PAR
the data bus are used as a serial port; the remaining data bits are high impedance outputs. When
PAR
SER/
= LOW, the parallel port is selected.
9, 10 D[0:1] DO Bits 0 and 1 of the parallel port data output bus.
11, 12 D[2:3] DI/O
or
DIVSCLK[0:1]
When SER/
When SER/
Mode (EXT/
PAR
= LOW, these outputs are used as bits 2 and 3 of the parallel port data output bus.
PAR
= HIGH, Serial Clock Division Selection. When using Serial Master Read after Convert
INT
= LOW, RDC/SDIN= LOW) these inputs can be used to slow down the internally
generated serial clock which clocks the data output. In other serial modes, these pins are high
impedance outputs.
13 D4 DI/O
or EXT/
INT
When SER/
When SER/
PAR
= LOW, this output is used as bit 4 of the parallel port data output bus.
PAR
= HIGH, Serial Clock Source Select. This input is used to select the internally generated,
(Master ) or external (Slave) serial data clock.
INT
When EXT/
When EXT/
CS
, connected to the SCLK input.
= LOW: Master Mode, the internal clock is selected on SCLK output.
INT
= HIGH: Slave Mode output data is synchronized to an external clock signal, gated by
REFGND
REF
36
AGND
CNVST
35
34
PD
33
RESET
32
CS
31
RD
30
DGND
29
BUSY
28
D15
27
D14
26
D13
25
D12
21 22 23 24
D9/SCLK
D10/SYNC
D8/SDOUT
-004
D11/RDERROR
=HIGH the serial interface is selected and some bits of
Rev. PrE | Page 8 of 28
Preliminary Technical Data AD7621
Pin No. Mnemonic Type1 Description
14 D5 DI/O
or INVSYNC
15 D6 DI/O
or INVSCLK Invert SCLK Select. In all Serial modes, this input is used to invert the SCLK signal.
16 D7 DI/O Bit 7 of the Parallel Port Data Output Bus.
or RDC
or SDIN
17 OGND P Input/Output Interface Digital Power Ground.
18 OVDD P
19 DVDD P Digital Power. Nominally at 2.5 V.
20 DGND P Digital Power Ground.
21 D8 DO
or SDOUT
22 D9 DI/O
or SCLK
23 D10 DO
or SYNC
24 D11 DO
or RDERROR
25-28 D[12:15 DO Bit 12 to Bit 15 of the Parallel Port Data output bus.
29 BUSY DO
30 DGND P Digital Power Ground.
31
32
RD
CS
DI
DI
When SER/
When SER/
select the active state of the SYNC signal.
When INVSYNC = LOW, SYNC is active HIGH.
When INVSYNC = HIGH, SYNC is active LOW.
When SER/
When SER/
used to select the read mode.
When RDC = HIGH, the previous conversion result is read during current conversion and the period of
SCLK changes (see Master Serial Interface section).
When RDC = LOW (read after convert) the current result is read after conversion.
Serial Data In. When using Serial Slave mode, (EXT/
daisy chain the conversion results from two or more ADCs onto a single SDOUT line. The digital data
level on SDIN is output on SDOUT with a delay of 16 SCLK periods after the initiation of the read
sequence.
Input/Output Interface Digital Power. Nominally at the same supply than the supply of the host
interface (2.5 V or 3 V).
When SER/
When SER/
synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7621 provides the
conversion result, MSB first, from its internal shift register. The data format is determined by the logic
level of OB/
In Master mode (EXT/
In Slave mode (EXT/
When INVSCLK = LOW, SDOUT is updated on SCLK rising edge and valid on the next falling edge.
When INVSCLK = HIGH, SDOUT is updated on SCLK falling edge and valid on the next rising edge.
When SER/
When SER/
output, dependent upon the logic state of the EXT/
updated depends upon the logic state of the INVSCLK pin.
When SER/
When SER/
used as a digital output frame synchronization for use with the internal data clock.
When a read sequence is initiated and INVSYNC = LOW, SYNC is driven HIGH and remains HIGH while
SDOUT output is valid.
When a read sequence is initiated and INVSYNC = HIGH, SYNC is driven LOW and remains LOW while
SDOUT output is valid.
When SER/
When SER/
incomplete read error flag. If a data read is started and not completed when the current conversion is
complete, the current data is lost and RDERROR is pulsed high.
Busy Output. Transitions HIGH when a conversion is started, and remains HIGH until the conversion is
complete and the data is latched into the on-chip shift register. The falling edge of BUSY could be
used as a data ready clock signal.
Read Data. When
Chip Select. When
also used to gate the external clock.
PAR
= LOW this output is used as bit 5 of the parallel port data output bus.
PAR
= HIGH, Invert SYNC Select. In Serial Master mode (EXT/
PAR
= LOW this output is used as bit 6 of the Parallel Port Data Output Bus.
PAR
= HIGH , Read During Convert. When using Serial Master mode (EXT/
INT
= HIGH), SDIN could be used as a data input to
PAR
= LOW this output is used as bit 8 of the Parallel Port Data Output Bus.
PAR
= HIGH, Serial Data Output. In Serial mode, this pin is used as the serial data output
2C
.
INT
= LOW), SDOUT is valid on both edges of SCLK.
INT
= HIGH):
PAR
= LOW this output is used as bit 9 of the Parallel Port Data Output Bus.
PAR
= HIGH, Serial Clock. In all Serial modes, this pin is used as the serial data clock input or
INT
pin. The active edge where the data SDOUT is
PAR
= LOW this output is used as bit 10 of the Parallel Port Data Output Bus.
PAR
= HIGH, Frame Syncronization. In Serial Master mode (EXT/
PAR
= LOW this output is used as bit 11 of the Parallel Port Data Output Bus.
PAR
= HIGH, Read Error. In Serial Slave mode (EXT/
CS
and RD are both LOW, the interface parallel or serial output bus is enabled.
CS
and RD are both LOW, the interface parallel or serial output bus is enabled. CS is
INT
INT
= LOW), this input is used to
INT
= LOW), RDC is
INT
= LOW), this output is
= HIGH), this output is used as an
Rev. PrE | Page 9 of 28
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