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ANALOG DEVICES
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AD7621
Service Manual
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ANALOG DEVICES AD7621 Service Manual

www.BDTIC.com/ADI
16-Bit, 2 LSB INL, 3 MSPS PulSAR® ADC

FEATURES

Throughput
3 MSPS (wideband warp and warp mode) 2 MSPS (normal mode)
1.25 MSPS (impulse mode)
2.048 V internal reference (V
Differential input range: ±V INL: ±2 LSB maximum, ±1 LSB typical 16-bit resolution with no missing codes SINAD: 89 dB typical @ 100 kHz THD: −101 dB typical @ 100 kHz
No pipeline delay (SAR architecture) Parallel (16- or 8-bit bus) and serial 5 V/3.3 V/2.5 V interface SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible
2.5 V single-supply operation
Power dissipation: 65 mW typical @ 3 MSPS 48-lead LQFP and 48-lead LFCSP_VQ packages Speed upgrade of the A
D7677

APPLICATIONS

Medical instruments High speed data acquisition Digital signal processing Communications Instrumentation Spectrum analysis ATE
REF
up to 2.5 V)
REF
AD7621

FUNCTIONAL BLOCK DIAGRAM

AGND AVDD
IN+ IN–
PDREF PDBUF
PD
RESET
TEMP
REFBUFIN
REF
CONTROL LOGIC AND
CALIBRATION CIRCUITRY
WARP
REF AMP
SWITCHED
CAP DAC
IMPULSE
REF REFGND
AD7621
CLOCK
CNVST
Figure 1.
Table 1. PulSAR Selection
Type/kSPS 100 to 250 500 to 570
Pseudo
Differential
AD7651 AD7660/61
AD7650/52
AD7664/66
True Bipolar AD7663 AD7665 AD7671 True
Differential AD7675 AD7676 AD7677 AD7621 18-Bit AD7678 AD7679 AD7674 AD7641 Multichannel/
Simultaneous
AD7654 AD7655
DGNDDVDD
OVDD OGND
SERIAL
PORT
16
D[15:0]
PARALLEL
INTERFACE
SER/PAR BUSY RD CS OB/2C BYTESWAP
800 to 1000 >1000
AD7653 AD7667
04565-001

GENERAL DESCRIPTION

The AD7621 is a 16-bit, 3 MSPS, charge redistribution SAR, fully differential analog-to-digital converter (ADC) that operates from a single 2.5 V power supply. It contains a high speed 16-bit sampling ADC, an internal conversion clock, an internal reference (and buffer), error correction circuits, and both serial and parallel system interface ports. It features two very high sampling rate modes (wideband warp and warp), a fast mode (normal) for asynchronous rate applications, and a reduced power mode (impulse) for low power applications where the power is scaled with the throughput. Operation is specified from −40°C to +85°C.
Rev. 0

PRODUCT HIGHLIGHTS

1. Fast Throughput.
The AD7621 is a 3 MSPS, charge redistribution, 16-bit SAR ADC.
2. Superior Linearity.
The AD7621 has no missing 16-bit code.
3. Internal Reference.
The AD7621 has a 2.048 V internal reference with a typical drift of ±7 ppm/°C.
4. Single-Supply Operation.
The AD7621 operates from a 2.5 V single supply and typically dissipates 65 mW. In impulse mod
e
dissipation decreases with th Se
rial or Parallel Interface.
5.
Versatile parallel (16- or 8-bit bus) or 2-wire serial interf arrangement compatible with 2.5 V, 3.3 V, or 5 V logic.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2005 Analog Devices, Inc. All rights reserved.
throughput.
e, its power
ace
AD7621
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TABLE OF CONTENTS
Specifications..................................................................................... 3
Voltage Reference Input ............................................................ 18
Timing Specifications....................................................................... 5
Serial Clock Timing Specifications ............................................ 6
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Te r mi n ol o g y .................................................................................... 11
Typical Performance Characteristics........................................... 12
Theory of Operation ...................................................................... 15
Circuit Information.................................................................... 15
Converter Operation.................................................................. 15
Modes of Operation ................................................................... 15
Transfer Fu nctions...................................................................... 16
Typical Conne ction Diagram ................................................... 17
Analog Inputs.............................................................................. 17
Driver Amplifier Choice............................................................ 17
Power Supply............................................................................... 19
Power Dissipation vs. Throughput .......................................... 20
Conversion Control ...................................................................20
Interfaces.......................................................................................... 21
Digital Interface.......................................................................... 21
Parallel Interface......................................................................... 21
Serial Interface............................................................................ 22
Master Serial Interface............................................................... 22
Slave Serial Interface .................................................................. 24
Microprocessor Interfacing....................................................... 26
Application...................................................................................... 27
Layout ..........................................................................................27
Evaluating the AD7621 Performance...................................... 27
Outline Dimensions .......................................................................28
Ordering Guide .......................................................................... 29
REVISION HISTORY
5/05 — Revision 0: Initial Version
Rev. 0 | Page 2 of 32
AD7621
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SPECIFICATIONS

AVDD = DVDD = 2.5 V; OVDD = 2.3 V to 3.6 V; V
Table 2.
Parameter Conditions Min Typ Max Unit
RESOLUTION 16 Bits ANALOG INPUT
Voltage Range
VIN+ − VIN− Operating Input Voltage VIN+, VIN− to AGND −0.1 AVDD Analog Input CMRR fIN = 100 kHz 55 dB Input Current 3 MSPS throughput 25 μA Input Impedance
2
THROUGHPUT SPEED
Complete Cycle Wideband warp, warp modes 333 ns Throughput Rate Wideband warp, warp modes 0.001 3 MSPS Time Between Conversions Wideband warp, warp modes 1 ms Complete Cycle Normal mode 500 ns Throughput Rate Normal mode 0 2 MSPS Complete Cycle Impulse mode 800 ns Throughput Rate Impulse mode 0 1.25 MSPS
DC ACCURACY All modes
Integral Linearity Error
3
V No Missing Codes V Differential Linearity Error V Transition Noise V Transition Noise V Zero Error, T
MIN
to T
MAX
5
−30 +30 LSB Zero Error Temperature Drift ±1 ppm/°C Gain Error, T
MIN
to T
MAX
5
−0.38 +0.38 % of FSR Gain Error Temperature Drift ±2 ppm/°C Power Supply Sensitivity AVDD = 2.5 V ± 5% ±3 LSB
AC ACCURACY
Dynamic Range fIN = 20 kHz, V Signal-to-Noise fIN = 20 kHz, V f f
IN
IN
Spurious-Free Dynamic Range fIN = 20 kHz 103 dB f
IN
Total Harmonic Distortion fIN = 20 kHz –102 dB f
IN
Signal-to-(Noise + Distortion) fIN = 20 kHz, V
f f
IN
IN
–3 dB Input Bandwidth 50 MHz
SAMPLING DYNAMICS
Aperture Delay 1 ns Aperture Jitter 5 ps rms Transient Response Full-scale step 50 ns
INTERNAL REFERENCE PDREF = PDBUF = low
Output Voltage REF @ 25°C 2.038 2.048 2.058 V Temperature Drift –40°C to +85°C ±7 ppm/°C Line Regulation AVDD = 2.5 V ± 5% ±15 ppm/V
= 2.5 V; all specifications T
REF
= 2.048 V, PDREF = high −2 ±1 +2 LSB
REF
= 2.048 V, PDREF = high 16 Bits
REF
= 2.048 V, PDREF = high −1 +2 LSB
REF
= 2.5 V 0.69 LSB
REF
= 2.048 V 0.82 LSB
REF
= 2.5 V 90.5 dB
REF
= 2.5 V 88 90 dB
REF
= 20 kHz, V = 100 kHz, V
= 2.048 V 86 88 dB
REF
= 2.5 V 89.2 dB
REF
−V
REF
MIN
to T
, unless otherwise noted.
MAX
V
REF
1
= 100 kHz 101 dB
= 100 kHz −100 dB
= 2.5 V 87.5 89.8 dB
REF
= 20 kHz, V = 100 kHz, V
= 2.048 V 87.5 dB
REF
= 2.5 V 89 dB
REF
V V
4
6
Rev. 0 | Page 3 of 32
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Parameter Conditions Min Typ Max Unit
Turn-On Settling Time C REFBUFIN Output Voltage REFBUFIN @ 25°C 1.2 V REFBUFIN Output Resistance 6.33 kΩ
EXTERNAL REFERENCE PDREF = PDBUF = high
Voltage Range REF 1.8 2.048 AVDD V Current Drain 3 MSPS throughput 250 μA
REFERENCE BUFFER PDREF = high, PDBUF = low
REFBUFIN Input Voltage Range 1.05 1.2 1.30 V
TEMPERATURE PIN
Voltage Output @ 25°C 273 mV Temperature Sensitivity 0.85 mV/°C Output Resistance 4.7 kΩ
DIGITAL INPUTS
Logic Levels
V
IL
V
IH
I
IL
I
IH
DIGITAL OUTPUTS
Data Format Pipeline Delay
V
OL
V
OH
7
8
POWER SUPPLIES
Specified Performance
AVDD 2.37 2.5 2.63 V DVDD 2.37 2.5 2.63 V OVDD 2.30
Operating Current
11
AVDD
10
DVDD 3.6 mA OVDD 1 mA
Power Dissipation
With Internal Reference Without Internal Reference With Internal Reference Without Internal Reference
11
10
10
12
12
In Power-Down Mode13 PD = high 600 μW
TEMPERATURE RANGE
Specified Performance T
1
When using an external reference. With the internal reference, the input range is −0.1 V to V
2
See the Analog Inputs section.
3
Linearity is tested using endpoints, not best fit. Tested with an external reference at 2.048 V.
4
LSB means least significant bit. With the ±2.048 V input range, 1 LSB is 62.5 μV.
5
See the Voltage Reference Input section. These specifications do not include the error contribution from the external reference.
6
All specifications in dB are referred to a full-scale input FSR. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified.
7
Parallel or serial 16-bit.
8
Conversion results are available immediately after completed conversion.
9
See the Absolute Maximum Ratings section.
10
In warp mode. Tested in parallel reading mode.
11
With internal reference, PDREF and PDBUF are low; without internal reference, PDREF and PDBUF are high.
12
In impulse mode. Tested in parallel reading mode.
13
With all digital inputs forced to OVDD.
14
Consult factory for extended temperature range.
14
= 10 μF 5 ms
REF
–0.3 +0.6 V
1.7 5.25 V –1 +1 μA –1 +1 μA
I
= 500 μA 0.4 V
SINK
I
= –500 μA OVDD − 0.3 V
SOURCE
9
3.6 V 3 MSPS throughput With internal reference 25.2 mA
3 MSPS throughput 70 86 mW 3 MSPS throughput 65 80 mW
1.25 MSPS throughput 42 55 mW
1.25 MSPS throughput 37 50 mW
MIN
to T
MAX
–40 +85 °C
.
REF
Rev. 0 | Page 4 of 32
AD7621
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TIMING SPECIFICATIONS

AVDD = DVDD = 2.5 V; OVDD = 2.3 V to 3.6 V; V
Table 3.
Parameter Symbol Min Typ Max Unit
CONVERSION AND RESET (Refer to Figure 31 and Figure 32)
Convert Pulse Width t Time Between Conversions (Warp2 Mode/Normal Mode/Impulse Mode)3t CNVST Low to BUSY High Delay BUSY High All Modes (Except Master Serial Read After Convert) t Aperture Delay t End of Conversion to BUSY Low Delay t Conversion Time (Warp Mode/Normal Mode/Impulse Mode) t Acquisition Time (Warp Mode/Normal Mode/Impulse Mode) t RESET Pulse Width t RESET Low to BUSY High Delay BUSY High Time from RESET Low
4
4
PARALLEL INTERFACE MODES (Refer to Figure 33 and Figure 35)
CNVST Low to DATA Valid Delay
(Warp Mode/Normal Mode/Impulse Mode) DATA Valid to BUSY Low Delay t Bus Access Request to DATA Valid t Bus Relinquish Time t
MASTER SERIAL INTERFACE MODES5 (Refer to Figure 37 and Figure 38)
CS Low to SYNC Valid Delay CS Low to Internal SCLK Valid Delay
5
CS Low to SDOUT Delay CNVST Low to SYNC Delay
(Warp Mode/Normal Mode/Impulse Mode) t SYNC Asserted to SCLK First Edge Delay t Internal SCLK Period Internal SCLK High Internal SCLK Low SDOUT Valid Setup Time SDOUT Valid Hold Time SCLK Last Edge to SYNC Delay
6
6
6
6
6
6
CS High to SYNC HI-Z CS High to Internal SCLK HI-Z CS High to SDOUT HI-Z BUSY High in Master Serial Read after Convert CNVST Low to SYNC Asserted Delay (All Modes) SYNC Deasserted to BUSY Low Delay t
= 2.5 V; all specifications T
REF
6
to T
MIN
1
2
t
3
4
5
6
7
8
9
t
38
t
39
t
10
11
12
13
t
14
t
15
t
16
, unless otherwise noted.
MAX
15 70
1
ns
333/500/800 ns 23 ns
283/430/560 ns 1 ns 10 ns 283/430/560 ns 50/70/50 ns 15 ns 10 ns 600 ns
283/430/560 ns
2 ns 20 ns 2 15 ns
10 ns 10 ns 10 ns
17
18
t
19
t
20
t
21
t
22
t
23
t
24
t
25
t
26
t
27
t
28
t
29
30
12/137/263 ns
0.5 ns 8 12 ns 2 ns 3 ns 1 ns 0 ns 0 ns
10 ns 10 ns 10 ns
See Table 4 275/400/500 ns
13 ns
Rev. 0 | Page 5 of 32
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Parameter Symbol Min Typ Max Unit
SLAVE SERIAL INTERFACE MODES5 (Refer to Figure 40 and Figure 41)
External SCLK Setup Time t External SCLK Active Edge to SDOUT Delay t SDIN Setup Time t SDIN Hold Time t External SCLK Period t External SCLK High t External SCLK Low t
1
See the Conversion Control section.
2
All timings for wideband warp mode are the same as warp mode.
3
In warp mode only, the time between conversions is 1 ms; otherwise, there is no required maximum time.
4
See the Digital Interface, and RESET sections.
5
In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.
6
In serial master read during convert mode. See Table 4 for serial master read after convert mode timing specifications.
31
32
33
34
35
36
37

SERIAL CLOCK TIMING SPECIFICATIONS

Table 4. Serial Clock Timings in Master Read After Convert Mode
DIVSCLK[1] 0 0 1 1 DIVSCLK[0] Symbol 0 1 0 1 Unit
SYNC to SCLK First Edge Delay Minimum t Internal SCLK Period Minimum t Internal SCLK Period Maximum t Internal SCLK High Minimum t Internal SCLK Low Minimum t SDOUT Valid Setup Time Minimum t SDOUT Valid Hold Time Minimum t SCLK Last Edge to SYNC Delay Minimum t BUSY High Width Maximum (Wideband and Warp Modes) t BUSY High Width Maximum (Normal Mode) t BUSY High Width Maximum (Impulse Mode) t
18
19
19
20
21
22
23
24
28
28
28
5 ns 1 8 ns 5 ns 5 ns
12.5 ns 5 ns 5 ns
0.5 3 3 3 ns 8 16 32 64 ns 12 25 50 100 ns 2 6 15 31 ns 3 7 16 32 ns 1 5 5 5 ns 0 0.5 10 28 ns 0 0.5 9 26 ns
0.500 0.720 1.160 2.040 μs
0.650 0.870 1.310 2.190 μs
0.780 1.000 1.440 2.320 μs
500μAI
TO OUTPUT
PIN
C
L
50pF
500μAI
NOTE IN SERIAL INTERFACE MODES, THE SYNC, SCLK AND SDOUT ARE DEFINED WITH A MAXIMUM LOAD. C
OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.
L
Figure 2. Load Circuit for Digital Interface Timing,
, SYNC, and SCLK Outputs, C
SDOUT
OL
1.4V
OH
04565-002
= 10 pF
L
0.8V
t
DELAY
2V
0.8V
Figure 3. Voltage Reference Levels for Timing
Rev. 0 | Page 6 of 32
2V
t
DELAY
2V
0.8V
05665-003
AD7621
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ABSOLUTE MAXIMUM RATINGS

Table 5.
Parameter Rating
Analog Inputs/Outputs
IN+1, IN−, REF, REFBUFIN, TEMP,
INGND, REFGND to AGND
Ground Voltage Differences
AGND, DGND, OGND ±0.3 V
Supply Voltages
AVDD, DVDD –0.3 V to +2.7 V OVDD –0.3 V to +3.8 V AVDD to DVDD ±2.8 V AVDD to OVDD +2.8 V to −3.8 V OVDD to DVDD
Digital Inputs −0.3 V to +5.5 V PDREF, PDBUF Internal Power Dissipation Internal Power Dissipation Junction Temperature 125°C Storage Temperature Range –65°C to +125°C
1
See the Analog Inputs section.
2
See the Power Supply section.
3
See the Voltage Reference Input section.
4
Specification is for the device in free air: 48-Lead LQFP; θJA = 91°C/W,
θJC = 30°C/W.
5
Specification is for the device in free air: 48-Lead LFCSP; θJA = 26°C/W.
2
3
4
5
AVDD + 0.3 V to
AGND − 0.3 V
≤ +0.3 V if DVDD < 2.3 V
±20 mA 700 mW
2.5 W
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device.
Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to
performance degradation or loss of functionality.
avoid
Rev. 0 | Page 7 of 32
AD7621
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PDBUF
PDREF
REFBUFIN
TEMP
AVDD
IN+
AGND
AGNDNCIN–
DGND
D8/SDOUT
D9/SCLK
REFGND
D10/SYNC
48 47 46 45 44 39 38 3743 42 41 40
1
AGND AVDD
NC
BYTESWAP
OB/2C
WARP IMPULSE SER/PAR
D0
D1 D2/DIVSCLK[0] D3/DIVSCLK[1]
NC = NO CONNECT
PIN 1 IDENTIFIER
2 3 4 5 6 7 8
9 10 11 12
13 14 15 16 17 18 19 20 21 22 23 24
D4/EXT/INT
D6/INVSCLK
D5/INVSYNC
AD7621
TOP VIEW
(Not to Scale)
DVDD
OVDD
OGND
D7/RDC/SDIN
Figure 4. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Type1 Description
1, 41, 42 AGND P Analog Power Ground Pin. 2, 44 AVDD P Input Analog Power Pins. Nominally 2.5 V. 3, 40 NC 4 BYTESWAP DI
No Connect. Parallel Mode Selection (8-Bit/16-Bit). When high, the LSB is output on D[15:8] and the MSB is output
on D[7:0]; when low, the LSB is output on D[7:0] and the MSB is output on D[15:8].
5
OB/2C
DI
Straight Binary/Binary Twos Complement Output. When high, the digital output is straight binary; when low, the MSB is inverted resulting in a twos complement output from its internal shift register.
6 WARP DI
Conversion Mode Selection. When WARP = high and IMPULSE = high, this selects wideband mode with slightly improved linearity and THD. When WARP = high and IMPULSE = low, this selects warp mode. In either mode, these are the fastest modes; maximum throughput is achievable, and a minimum conversion rate must be applied in order to guarantee full specified accuracy.
When WARP = low and IMPULSE = low, this input selects normal mode where full accuracy is maintained independent of the minimum conversion rate.
7 IMPULSE DI
Conversion Mode Selection. When IMPULSE = high and WARP = low, this input selects impulse mode, a reduced power mode. In this mode, the power dissipation is approximately proportional to the sampling rate.
8
SER/PAR
DI
Serial/Parallel Selection Input. When high, the serial interface is selected and some bits of the data bus are used as a serial port; the remaining data bits are high impedance outputs. When SER/PAR
the parallel port is selected. 9, 10 D[0:1] DO Bit 0 and Bit 1 of the Parallel Port Data Output Bus. 11, 12 D[2:3] DI/O
or DIVSCLK[0:1]
When SER/PAR = low, these outputs are used as Bit 2 and Bit 3 of the parallel port data output bus.
When SER/PAR
mode (EXT/INT
= high, serial clock division selection. When using serial master read after convert
= low, RDC/SDIN = low) these inputs can be used to slow down the internally generated serial clock that clocks the data output. In other serial modes, these pins are high impedance outputs.
13 D4 DI/O
or EXT/INT
When SER/PAR When SER/PAR
= low, this output is used as Bit 4 of the parallel port data output bus.
= high, serial clock source select. This input is used to select the internally generated (master ) or external (slave) serial data clock.
When EXT/INT When EXT/INT
= low: master mode. The internal serial clock is selected on SCLK output. = high: slave mode. The output data is synchronized to an external clock signal, gated
by CS, connected to the SCLK input.
REF
D11/RDERROR
36 35 34 33 32 31 30 29 28 27 26 25
AGND CNVST PD RESET CS RD DGND BUSY D15 D14 D13 D12
04565-004
= low,
Rev. 0 | Page 8 of 32
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Pin No. Mnemonic Type1 Description
14 D5 DI/O or INVSYNC
15 D6 DI/O or INVSCLK Invert SCLK Select. In all serial modes, this input is used to invert the SCLK signal.
16 D7 DI/O Bit 7 of the Parallel Port Data Output Bus. or RDC
or SDIN
17 OGND P Input/Output Interface Digital Power Ground. 18 OVDD P
19 DVDD P Digital Power. Nominally at 2.5 V. 20 DGND P Digital Power Ground. 21 D8 DO
or SDOUT
22 D9 DI/O
or SCLK
23 D10 DO or SYNC
24 D11 DO
or RDERROR
25 to 28 D[12:15] DO Bit 12 to Bit 15 of the Parallel Port Data Output Bus. 29 BUSY DO
30 DGND P Digital Power Ground. 31
RD
DI
When SER/PAR When SER/PAR
select the active state of the SYNC signal. When INVSYNC = low, SYNC is active high. When INVSYNC = high, SYNC is active low.
When SER/
When SER/PAR used to select the read mode.
When RDC = high, the previous conversion result is read during SCLK changes (see the Master Serial Interface section).
When RDC = low (read after convert), the current result is read after conversi Serial Data In. When using serial slave mode, (EXT/INT
daisy-chain the conversion results from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on SDOUT with a delay of 16 SCLK periods after the initiation of the read sequence.
Input/Output Interface Digital Power. Nomin (2.5 V or 3 V).
When SER/PAR When SER/PAR
synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7621 provides the conversion result, MSB first, from its internal shift register. The data format is determined by the logic level of OB/2C.
In master mode (EXT/INT In slave mode (EXT/INT
When INVSCLK = low, SDOUT is updated on SCLK rising edge and valid on the next falling edge. When INVSCLK = high, SDOUT is updated on SCLK falling edge and valid on the next rising edge.
Parallel Port Data Output Bus Bit 9. When SER/PAR data output bus.
Serial Clock. When SER/PAR clock input or output, dependent upon the logic state of the EXT/INT data SDOUT is updated depends upon the logic state of the INVSCLK pin. When SER/PAR
When SER/PAR used as a digital output frame synchronization for use with the internal data clock.
When a read sequence is initiated and INVSYNC = low, SYNC is driven high and remains high while SDOUT output i When a read sequence is initiated and INVSYNC = high, SYNC is driven low and remains low while SDOUT output is valid.
Parallel Port Data Output Bus Bit 11. When SER/PAR port data output bus.
Read Error. When SER/PAR as an incomplete read error flag. If a data read is started and not completed when the current conversion is complete, the current data is lost and RDERROR is pulsed high.
Busy Output. Transitions high when a conversion is started, and remains hig complete and the data is latched into the on-chip shift register. The falling edge of BUSY can be used as a data ready clock signal.
Read Data. When CS
= low this output is used as Bit 5 of the parallel port data output bus. = high, invert sync select. In serial master mode (EXT/INT = low), this input is used to
PAR
= low this output is used as Bit 6 of the parallel port data output bus.
= high, read during convert. When using Serial Master mode (EXT/INT = low), RDC is
current conversion and the period of
on.
= high), SDIN could be used as a data input to
ally at the same supply as the supply of the host interface
= low this output is used as Bit 8 of the parallel port data output bus. = high, serial data output. In serial mode, this pin is used as the serial data output
= low). SDOUT is valid on both edges of SCLK.
= high):
= low, this output is used as Bit 9 of the parallel port
= high, serial clock. In all serial modes, this pin is used as the serial data
pin. The active edge where the
= low, this output is used as Bit 10 of the parallel port data output bus. = high, frame synchronization. In serial master mode (EXT/INT= low), this output is
s valid.
= low, this output is used as Bit 11 of the parallel
= high, read error. In serial slave mode (EXT/INT = high), this output is used
h until the conversion is
and RD are both low, the interface parallel or serial output bus is enabled.
Rev. 0 | Page 9 of 32
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Pin No. Mnemonic Type1 Description
32
33 RESET DI
34 PD DI
35
36 AGND P Analog Power Ground Pin. 37 REF AI/O
38 REFGND AI Reference Input Analog Ground. 39 IN− AI Differential Negative Analog Input. 43 IN+ AI Differential Positive Analog Input. 45 TEMP AO Temperature Sensor Analog Output. 46 REFBUFIN AI/O
47 PDREF DI
48 PDBUF DI
1
AI = analog input; AI/O = bidirectional analog; AO = analog output; DI = digital input; DI/O = bidirectional digital; DO = digital output; P = power.
CS
CNVST
DI
DI
Chip Select. When CS and RD are both low, the interface parallel or serial output bus is enabled. CS is also used to gate the external clock in slave serial mode.
Reset Input. When high, reset the AD7621. Current conversi enables the calibration mode indicated by pulsing BUSY high. Refer to the Digital Interface section. If not used, this pin can be tied to DGND.
Power-Down Input. When high, power down the ADC. Power consumption is reduced and
sions are inhibited after the current one is completed.
conver Conversion Start. A falling edge on CNVST
initiates a conversion.
Reference Output/Input.
PDREF/PDBUF = low, the internal reference and buffer are enabled producing 2.048 V on this pin.
When When PDREF/PDBUF = high, the internal reference and buffer are disabled allowing an externally supplied voltage reference up to AVDD volts. Decoupling is required with or without the internal reference and buffer. Refer to the Voltage Reference Input section.
Internal Reference Output/Reference Buffer Input.
When PDREF/PDBUF = low, the (typical) bandgap output on this pin, which needs external decoupling. The internal fixed gain reference buffer uses this to produce 2.048V on the REF pin. When using an external reference with the internal reference buffer (PDBUF = low, PDREF = high), applying 1.2 V on this pin produces 2.048 V on the REF pin. Refer to the Voltage Reference Input section.
Internal Reference Power-Down Input.
When low, the i When high, the internal reference is powered down and an external reference must been used.
Internal Reference Buffer Power-Down Input.
When low, the buffer is enabled (must be low when using inter When high, the buffer is powered-down.
nternal reference is enabled.
puts the internal sample-and-hold into the hold state and
internal reference and buffer are enabled producing the 1.2 V
on if any is aborted. Falling edge of RESET
nal reference).
Rev. 0 | Page 10 of 32
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