ANALOG DEVICES AD7610 Service Manual

16-Bit, 250 kSPS, Unipolar/Bipolar

P

VCCV

FEATURES

Multiple pins/software programmable input ranges:

5 V, 1 0 V, ± 5 V, ±1 0 V
Pins or serial SPI®-compatible input ranges/mode selection
Throughput: 250 kSPS
16-bit resolution with no missing codes
INL: ±0.75 LSB typ, ±1.5 LSB max (±23 ppm of FSR)
SNR: 94 dB @ 2 kHz
iCMOS® process technology
5 V internal reference: typical drift 3 ppm/°C;
On-chip temperature sensor
No pipeline delay (SAR architecture)
Parallel (16- or 8-bit bus) and serial 5 V/3.3 V interface
SPI-/QSPI™-/MICROWIRE™-/DSP-compatible
Power dissipation

90 mW @ 250 kSPS

10 mW @ 1 kSPS
48-lead LQFP and LFCSP (7 mm × 7 mm) packages

APPLICATIONS

Process control
Medical instruments
High speed data acquisition
Digital signal processing
Instrumentation
Spectrum analysis
AT E

Programmable Input PulSAR® ADC

AD7610

FUNCTIONAL BLOCK DIAGRAM

AGND

AVDD

PDREF

PDBUF

IN+

IN–

CNVST

PD

RESET

REFBUFI N

TEM

REF
AMP

REF

SWITCHED

CAP DAC

CONTROL LOG IC AND

CALIBRATION CIRCUIT RY

BIPOLAR TEN

REF REFGND

CLOCK

Figure 1.

EE

AD7610

DATAPORT

CONFIG URATIO N

PARALLEL

INTERF ACE

SERIAL

SERIAL

PORT

DGNDDVDD

OVDD

OGND

16

D[15:0]

SER/PAR

BYTESWAP

OB/2C

BUSY

RD

CS

06395-001

GENERAL DESCRIPTION

The AD7610 is a 16-bit charge redistribution successive approxi­mation register (SAR), architecture analog-to-digital converter
(ADC) fabricated on Analog Devices, Inc.’s iCMOS high voltage
process. The device is configured through hardware or via a
dedicated write only serial configuration port for input range
and operating mode. The AD7610 contains a high speed 16-bit
sampling ADC, an internal conversion clock, an internal reference
(and buffer), error correction circuits, and both serial and parallel
system interface ports. A falling edge on
analog input on IN+ with respect to a ground sense, IN−. The
AD7610 features four different analog input ranges: 0 V to 5 V, 0 V
to 1 0 V, ±5 V, a nd ±1 0 V. Po we r co n su m pt i on i s s ca l e d l i ne a rl y
with throughput. The device is available in Pb-free 48-lead, low­profile quad flat package (LQFP) and a lead frame chip-scale
(LFCSP_VQ) package. Operation is specified from −40°C to
+85°C.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

CNVST

samples the

Table 1. 48-Lead 14-/16-/18-Bit PulSAR Selection

100 kSPS to

Type

Pseudo
Differential

True Bipolar AD7610

True
Differential

18-Bit, True
Differential

Multichannel/
Simultaneous

250 kSPS

AD7651
AD7660
AD7661

AD7663

AD7675 AD7676 AD7677 AD7621

AD7678 AD7679 AD7674 AD7641

AD7654

500 kSPS to
570 kSPS

AD7650
AD7652
AD7664
AD7666

AD7665 AD7612

AD7655

800 kSPS to
1000 kSPS

AD7653
AD7667

AD7671
AD7951

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006 Analog Devices, Inc. All rights reserved.

>1000
kSPS

AD7622
AD7623

AD7643

AD7610

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram ..............................................................1

General Description......................................................................... 1

Revision History ...............................................................................2

Specifications..................................................................................... 3

Timing Specifications ..................................................................5

Absolute Maximum Ratings............................................................ 7

ESD Caution.................................................................................. 7

Pin Configuration and Function Descriptions............................. 8

Typical Performance Characteristics........................................... 11

Terminology.................................................................................... 15

Theory of Operation ......................................................................16

Overview...................................................................................... 16

Converter Operation.................................................................. 16

Transfer Functions......................................................................17

Typical Connection Diagram ...................................................18

Analog Inputs..............................................................................19

Driver Amplifier Choice ........................................................... 20

Voltage Reference Input/Output ..............................................20

Power Supplies............................................................................ 21

Conversion Control................................................................... 22

Interfaces.......................................................................................... 23

Digital Interface.......................................................................... 23

Parallel Interface......................................................................... 23

Serial Interface............................................................................ 24

Master Serial Interface............................................................... 24

Slave Serial Interface.................................................................. 26

Hardware Configuration........................................................... 28

Software Configuration............................................................. 28

Microprocessor Interfacing....................................................... 29

Application Information................................................................ 30

Layout Guidelines....................................................................... 30

Evaluating Performance ............................................................ 30

Outline Dimensions....................................................................... 31

Ordering Guide .......................................................................... 31

REVISION HISTORY

10/06—Revision 0: Initial Version

Rev. 0 | Page 2 of 32

AD7610

SPECIFICATIONS

AVDD = DVDD = 5 V; OVDD = 2.7 V to 5.5 V; VCC = 15 V; VEE = −15 V; V

Table 2.

Parameter Conditions/Comments Min Typ Max Unit

RESOLUTION 16 Bits
ANALOG INPUT

Voltage Range, VIN V
V
V
V
V

Analog Input CMRR fIN = 100 kHz 75 dB
Input Current V
Input Impedance

THROUGHPUT SPEED

Complete Cycle 4 s
Throughput Rate 250 kSPS

DC ACCURACY

Integral Linearity Error
No Missing Codes
Differential Linearity Error

2

2

2

Transition Noise 0.55 LSB
Zero Error (Unipolar or Bipolar) −35 +35 LSB
Zero Error Temperature Drift ±1 ppm/°C
Bipolar Full-Scale Error −50 +50 LSB
Unipolar Full-Scale Error −70 +70 LSB
Full-Scale Error Temperature Drift ±1 ppm/°C
Power Supply Sensitivity AVDD = 5 V ± 5% 3 LSB

AC ACCURACY

Dynamic Range VIN = 0 V to 5 V, fIN = 2 kHz, −60 dB 92.5 93.5 dB
V
V
Signal-to-Noise Ratio VIN = 0 V to 5 V, 0 V to 10 V, fIN = 2 kHz 92 93 dB
V
V
Signal-to-(Noise + Distortion) (SINAD) VIN = ±5 V, fIN = 2 kHz 92.5 dB
V
V
Total Harmonic Distortion fIN = 2 kHz −107 dB
Spurious-Free Dynamic Range fIN = 2 kHz 107 dB
–3 dB Input Bandwidth VIN = 0 V to 5 V 650 kHz
Aperture Delay 2 ns
Aperture Jitter 5 ps rms
Transient Response Full-scale step 500 ns

INTERNAL REFERENCE PDREF = PDBUF = low

Output Voltage REF @ 25°C 4.965 5.000 5.035 V

Temperature Drift –40°C to +85°C ±3 ppm/°C

Line Regulation AVDD = 5 V ± 5% ±15 ppm/V

Long-Term Drift 1000 hours 50 ppm

Turn-On Settling Time C
REFERENCE BUFFER PDREF = high

REFBUFIN Input Voltage Range 2.4 2.5 2.6 V

− V

= 0 V to 5 V −0.1 +5.1 V

IN+

IN−

− V

= 0 V to 10 V −0.1 +10.1 V

IN+

IN−

− V

= ±5 V −5.1 +5.1 V

IN+

IN−

− V

= ±10 V −10.1 +10.1 V

IN+

IN−

to AGND −0.1 +0.1 V

IN−

= ±5 V, ±10 V @ 250 kSPS 100

IN

Analog Inputs section

See

−1.5 ±0.75 +1.5 LSB
16 Bits

−1 +1.5 LSB

= 0 V to 10 V, ±5 V, fIN = 2 kHz, −60 dB 94 dB

IN

= ±10 V, fIN = 2 kHz, −60 dB 94.5 dB

IN

= ±5 V, ±10 V, fIN = 2 kHz 94 dB

IN

= 0 V to 5 V, fIN = 20 kHz 93.5 dB

IN

= 0 V to 10 V, ±5 V, fIN = 2 kHz 93 dB

IN

= ±10 V, fIN = 2 kHz 93.5 dB

IN

= 22 µF 10 ms

REF

= 5 V; all specifications T

REF

to T

MIN

, unless otherwise noted.

MAX

1

µA

3

4

Rev. 0 | Page 3 of 32

AD7610

Parameter Conditions/Comments Min Typ Max Unit

EXTERNAL REFERENCE PDREF = PDBUF = high

Voltage Range REF 4.75 5 AVDD + 0.1 V
Current Drain 250 kSPS throughput 30 µA

TEMPERATURE PIN

Voltage Output @ 25°C 311 mV
Temperature Sensitivity 1 mV/°C
Output Resistance 4.33 kΩ

DIGITAL INPUTS

Logic Levels

VIL −0.3 +0.6 V
VIH 2.1 OVDD + 0.3 V
IIL −1 +1 µA
IIH −1 +1 µA

DIGITAL OUTPUTS

Data Format Parallel or serial 16-bit
Pipeline Delay

VOL I
VOH I

POWER SUPPLIES

Specified Performance

AVDD 4.75
DVDD 4.75 5 5.25 V
OVDD 2.7 5.25 V
VCC 7 15 15.75 V
VEE −15.75 −15 0 V

Operating Current

AVDD

With Internal Reference 8 mA

With Internal Reference Disabled 6.3 mA
DVDD 3.3 mA
OVDD 0.3 mA
VCC VCC = 15 V, with internal reference buffer 1.4 mA
VCC = 15 V 0.8 mA
VEE VEE = −15 V 0.7 mA

Power Dissipation @ 250 kSPS throughput

With Internal Reference PDREF = PDBUF = low 90 110 mW
With Internal Reference Disabled PDREF = PDBUF = high 70 90 mW

In Power-Down Mode9 PD = high 10 µW

TEMPERATURE RANGE

Specified Performance T

1

With VIN = 0 V to 5 V or 0 V to 10 V ranges, the input current is typically 40 A. In all input ranges, the input current scales with throughput. See the Ana log Inp uts section.

2

Linearity is tested using endpoints, not best fit. All linearity is tested with an external 5 V reference.

3

LSB means least significant bit. All specifications in LSB do not include the error contributed by the reference.

4

All specifications in dB are referred to a full-scale range input, FSR. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified.

5

Conversion results are available immediately after completed conversion.

6

4.75 V or V

7

Tested in parallel reading mode.

8

With internal reference, PDREF = PDBUF = low; with internal reference disabled, PDREF = PDBUF = high. With internal reference buffer, PDBUF = low.

9

With all digital inputs forced to OVDD.

10

Consult sales for extended temperature range.

5

7, 8

10

– 0.1 V, whichever is larger.

REF

= 500 µA 0.4 V

SINK

= –500 µA OVDD − 0.6 V

SOURCE

6

5 5.25 V

@ 250 kSPS throughput

to T

MIN

−40 +85 °C

MAX

Rev. 0 | Page 4 of 32

AD7610

TIMING SPECIFICATIONS

AVDD = DVDD = 5 V; OVDD = 2.7 V to 5.5 V; VCC = 15 V; VEE = −15 V; V

Table 3.

Parameter Symbol Min Typ Max Unit

CONVERSION AND RESET (See Figure 33 and Figure 34)

Convert Pulse Width t1 10 ns
Time Between Conversions t2 4 μs
CNVST Low to BUSY High Delay
BUSY High (Except Master Serial Read After Convert) t4 1.45 μs
Aperture Delay t5 2 ns
End of Conversion to BUSY Low Delay t6 10 ns
Conversion Time t7 1.45 μs
Acquisition Time t8 380 ns
RESET Pulse Width t9 10 ns

PARALLEL INTERFACE MODES (See Figure 35 and Figure 37)

CNVST Low to DATA Valid Delay
DATA Valid to BUSY Low Delay t11 20 ns
Bus Access Request to DATA Valid t12 40 ns
Bus Relinquish Time t13 2 15 ns

MASTER SERIAL INTERFACE MODES1 (See Figure 39 and Figure 40)

CS Low to SYNC Valid Delay
CS Low to Internal SDCLK Valid Delay1
CS Low to SDOUT Delay
CNVST Low to SYNC Delay, Read During Convert
SYNC Asserted to SDCLK First Edge Delay t18 3 ns

Internal SDCLK Period2 t
Internal SDCLK High2 t
Internal SDCLK Low2 t
SDOUT Valid Setup Time2 t
SDOUT Valid Hold Time2 t
SDCLK Last Edge to SYNC Delay2 t
CS High to SYNC HI-Z

CS High to Internal SDCLK HI-Z
CS High to SDOUT HI-Z
BUSY High in Master Serial Read After Convert2 t
CNVST Low to SYNC Delay, Read After Convert
SYNC Deasserted to BUSY Low Delay t30 25 ns

SLAVE SERIAL/SERIAL CONFIGURATION INTERFACE MODES1 (See Figure 42,
Figure 43, and Figure 45)

External SDCLK, SCCLK Setup Time t31 5 ns
External SDCLK Active Edge to SDOUT Delay t32 2 18 ns
SDIN/SCIN Setup Time t33 5 ns
SDIN/SCIN Hold Time t34 5 ns
External SDCLK/SCCLK Period t35 25 ns
External SDCLK/SCCLK High t36 10 ns
External SDCLK/SCCLK Low t37 10 ns

1

In serial interface modes, the SDSYNC, SDSCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.

2

In serial master read during convert mode. See Table 4 for serial mode read after convert mode.

= 5 V; all specifications T

REF

t

35 ns

3

t

1.41 μs

10

t

10 ns

14

t

10 ns

15

t

10 ns

16

t

560 ns

17

30 45 ns

19

15 ns

20

10 ns

21

4 ns

22

5 ns

23

5 ns

24

t

10 ns

25

t

10 ns

26

t

10 ns

27

See Table 4

28

t

1.31 μs

29

MIN

to T

, unless otherwise noted.

MAX

Rev. 0 | Page 5 of 32

AD7610

Table 4. Serial Clock Timings in Master Read After Convert Mode

DIVSCLK[1]

0 0 1 1

DIVSCLK[0] Symbol 0 1 0 1 Unit

SYNC to SDCLK First Edge Delay Minimum t18 3 20 20 20 ns
Internal SDCLK Period Minimum t19 30 60 120 240 ns
Internal SDCLK Period Maximum t19 45 90 180 360 ns
Internal SDCLK High Minimum t20 15 30 60 120 ns
Internal SDCLK Low Minimum t21 10 25 55 115 ns
SDOUT Valid Setup Time Minimum t22 4 20 20 20 ns
SDOUT Valid Hold Time Minimum t23 5 8 35 90 ns
SDCLK Last Edge to SYNC Delay Minimum t24 5 7 35 90 ns
BUSY High Width Maximum t28 2.25 3.00 4.40 7.30 µs

1.6mA I

TO OUTPUT

PIN

C

L

60pF

500µA I

NOTES

1. IN SERIAL INTERFACE MODES, THE SY NC, SCLK, AND
SDOUT ARE DEFI NED WITH A MAX IMUM LOAD

OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.

C

L

Figure 2. Load Circuit for Digital Interface Timing,

SDOUT, SYNC, and SCLK Outputs, C

OL

1.4V

2V

OH

6395-002

0.8V

t

DELAY

t

DELAY

2V

2V

0.8V0.8V

06395-003

Figure 3. Voltage Reference Levels for Timing

= 10 pF

L

Rev. 0 | Page 6 of 32

AD7610

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Rating

Analog Inputs/Outputs

IN+, IN−1 to AGND VEE − 0.3 V to VCC + 0.3 V
REF, REFBUFIN, TEMP,
REFGND to AGND

AVDD + 0.3 V to
AGND − 0.3 V

Ground Voltage Differences

AGND, DGND, OGND ±0.3 V

Supply Voltages

AVDD, DVDD, OVDD −0.3 V to +7 V
AVDD to DVDD, AVDD to OVDD ±7 V
DVDD to OVDD ±7 V
VCC to AGND, DGND –0.3 V to +16.5 V

VEE to GND +0.3 V to −16.5 V
Digital Inputs −0.3 V to OVDD +0.3 V
PDREF, PDBUF

2

±20 mA
Internal Power Dissipation3 700 mW
Internal Power Dissipation4 2.5 W
Junction Temperature 125°C
Storage Temperature Range −65°C to +125°C

1

See the Analog Inputs section.

2

See the Voltage Reference Input section.

3

Specification is for the device in free air: 48-Lead LQFP; θJA = 91°C/W,

θJC = 30°C/W.

4

Specification is for the device in free air: 48-Lead LFCSP; θJA = 26°C/W.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. 0 | Page 7 of 32

AD7610

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PDBUF

PDREF

REFBUFIN

TEMP

AVDD

IN+

AGND

VEE

VCC

IN–

REFGND

REF

36

BIPOL AR

35

CNVST

34

PD

33

RESET

32

CS

31

RD

30

TEN

29

BUSY

28

D15/SCCS

27

D14/SCCLK

26

D13/SCIN

25

D12/HW/ SW

D10/SYNC

D8/SDOUT

D9/SDCLK

D11/RDERROR

06395-004

AGND

AVDD

AGND

BYTESWAP

OB/2C

OGND

OGND

SER/PAR

D0

D1

D2/DIVSCLK[0]

D3/DIVSCLK[1]

48 47 46 45 44 43 42 41 40 39 38 37

1

PIN 1

2

3

4

5

6

7

8

9

10

11

12

13

14 15 16 17 18 19 20 21 22 23 24

D4/EXT/INT

D5/INVSYNC

AD7610

TOP VIEW

(Not to Scale)

D6/INVSCLK

D7/RDC/SDIN

DVDD

OVDD

OGND

Figure 4. Pin Configuration

DGND

Table 6. Pin Function Descriptions

Pin No. Mnemonic Type1Description

1, 3, 42 AGND P Analog Power Ground Pins. Ground reference point for all analog I/O. All analog I/O should be referenced to

2, 44 AVDD P Analog Power Pins. Nominally 4.75 V to 5.25 V and decoupled with 10 F and 100 nF capacitors.
4 BYTESWAP DI Parallel Mode Selection (8-Bit/16-Bit). When high, the LSB is output on D[15:8] and the MSB is output on

5

OB/

2C

DI

6, 7, 17 OGND P Input/Output Interface Digital Power Ground. Ground reference point for digital outputs. Should be

8

SER/

PAR

DI Serial/Parallel Selection Input.

9, 10 D[0:1] DO Bit 0 and Bit 1 of the parallel port data output bus. These pins are always outputs regardless of the state of

11, 12 D[2:3] or DI/O In parallel mode, these outputs are used as Bit 2 and Bit 3 of the parallel port data output bus.
DIVSCLK[0:1]

13 D4 or DI/O In parallel mode, this output is used as Bit 4 of the parallel port data output bus.

EXT/

INT

AGND and should be connected to the analog ground plane of the system. In addition, the AGND, DGND, and
OGND voltages should be at the same potential.

D[7:0]; when low, the LSB is output on D[7:0] and the MSB is output on D[15:8].

2

Straight Binary/Binary Twos Complement Output. When high, the digital output is straight binary. When low,
the MSB is inverted resulting in a twos complement output from its internal shift register.

connected to the system digital ground ideally at the same potential as AGND and DGND.

When SER/
When SER/

PAR

= low, the parallel mode is selected.

PAR

= high, the serial modes are selected. Some bits of the data bus are used as a serial port and

the remaining data bits are high impedance outputs.

PAR

SER/

Serial Data Division Clock Selection. In serial master read after convert mode (SER/
EXT/

.

PAR

= high,

INT

= low, RDC/SDIN = low) these inputs can be used to slow down the internally generated serial data

clock that clocks the data output. In other serial modes, these pins are high impedance outputs.

Serial Data Clock Source Select. In serial mode, this input is used to select the internally generated (master) or
external (slave) serial data clock for the AD7610 output data.
When EXT/
When EXT/

INT

= low, master mode; the internal serial data clock is selected on SDCLK output.

INT

= high, slave mode; the output data is synchronized to an external clock signal (gated by CS)

connected to the SDCLK input.

Rev. 0 | Page 8 of 32

AD7610

Pin No. Mnemonic Type1 Description

14 D5 or DI/O In parallel mode, this output is used as Bit 5 of the parallel port data output bus.
INVSYNC

15 D6 or DI/O In parallel mode, this output is used as Bit 6 of the parallel port data output bus.
INVSCLK In all serial modes, invert SDCLK/SCCLK select. This input is used to invert both SDCLK and SCCLK.

16 D7 or DI/O In parallel mode, this output is used as Bit 7 of the parallel port data output bus.
RDC or

SDIN

18 OVDD P Input/Output Interface Digital Power. Nominally at the same supply as the supply of the host interface 2.5 V, 3

19 DVDD P Digital Power. Nominally at 4.75 V to 5.25 V and decoupled with 10 μF and 100 nF capacitors. Can be supplied

20 DGND P Digital Power Ground. Ground reference point for digital outputs. Should be connected to system digital

21 D8 or DO In parallel mode, this output is used as Bit 8 of the parallel port data output bus.
SDOUT Serial Data output. In all serial modes this pin is used as the serial data output synchronized to SDCLK.

22 D9 or DI/O In parallel mode, this output is used as Bit 9 of the parallel port data output bus.
SDCLK Serial Data Clock. In all serial modes, this pin is used as the serial data clock input or output, dependent on the

23 D10 or DO In parallel mode, this output is used as Bit 10 of the parallel port data output bus.
SYNC

24 D11 or DO In parallel mode, this output is used as Bit 11 of the parallel port data output bus.
RDERROR

25 D12 or DI/O In parallel mode, this output is used as Bit 12 of the parallel port data output bus.

26 D13 or DI/O In parallel mode, this output is used as Bit 13 of the parallel port data output bus.
SCIN

HW/

SW

Serial Configuration Hardware/Software Select. In serial mode, this input is used to configure the AD7610 by

Serial Data Invert Sync Select. In serial master mode (SER/
select the active state of the SYNC signal.
When INVSYNC = low, SYNC is active high.
When INVSYNC = high, SYNC is active low.

When INVSCLK = low, the rising edge of SDCLK/SCCLK are used.
When INVSCLK = high, the falling edge of SDCLK/SCCLK are used.

Serial Data Read During Convert. In serial master mode (SER/
the read mode. See the
When RDC = low, the current result is read after conversion. Note the maximum throughput is not attainable

in this mode.
When RDC = high, the previous conversion result is read during the current conversion.

Serial Data In. In serial slave mode (SER/
chain the conversion results from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is
output on SDOUT with a delay of 16 SDCLK periods after the initiation of the read sequence.

V, or 5 V and decoupled with 10 μF and 100 nF capacitors.

from AVDD.

ground ideally at the same potential as AGND and OGND.

Conversion results are stored in an on-chip register. The AD7610 provides the conversion result, MSB first,
from its internal shift register. The data format is determined by the logic level of OB/
When EXT/
When EXT/
When INVSCLK = low, SDOUT is updated on SDCLK rising edge.
When INVSCLK = high, SDOUT is updated on SDCLK falling edge.

logic state of the EXT/
the INVSCLK pin.

Serial Data Frame Synchronization. In serial master mode (SER/
as a digital output frame synchronization for use with the internal data clock.
When a read sequence is initiated and INVSYNC = low, SYNC is driven high and remains high while the SDOUT
output is valid.
When a read sequence is initiated and INVSYNC = high, SYNC is driven low and remains low while the SDOUT
output is valid.

Serial Data Read Error. In serial slave mode (SER/
incomplete data read error flag. If a data read is started and not completed when the current conversion is
complete, the current data is lost and RDERROR is pulsed high.

hardware or software. See the
When HW/
When HW/

Serial Configuration Data Input. In serial software configuration mode (SER/
input is used to serially write in, MSB first, the configuration data into the serial configuration register. The
data on this input is latched with SCCLK. See the

INT

= low, (master mode) SDOUT is valid on both edges of SDCLK.

INT

= high (slave mode).

SW

= low, the AD7610 is configured through software using the serial configuration register.

SW

= high, the AD7610 is configured through dedicated hardware input pins.

Master Serial Interface section.

PAR

= high EXT/

INT

pin. The active edge where the data SDOUT is updated depends on the logic state of

PAR

Hardware Configuration section and Software Configuration section.

Software Configuration section.

PAR

= high, EXT/

PAR

= high, EXT/

INT

= high) SDIN can be used as a data input to daisy-

PAR

= high, EXT/

INT

INT

= low). This input is used to

INT

= low) RDC is used to select

2C

.

= high, EXT/

= high), this output is used as an

INT

= low), this output is used

PAR

= high, HW/SW = low) this

Rev. 0 | Page 9 of 32

AD7610

Pin No. Mnemonic Type1Description

27 D14 or DI/O In parallel mode, this output is used as Bit 14 of the parallel port data output bus.
SCCLK

Serial Configuration Clock. In serial software configuration mode (SER/
used to clock in the data on SCIN. The active edge where the data SCIN is updated depends on the logic state
of the INVSCLK pin. See the

Software Configuration section.

28 D15 or DI/O In parallel mode, this output is used as Bit 15 of the parallel port data output bus.

SCCS

Serial Configuration Chip Select. In serial software configuration mode (SER/
input enables the serial configuration port. See the

Software Configuration section.

29 BUSY DO Busy Output. Transitions high when a conversion is started, and remains high until the conversion

is complete and the data is latched into the on-chip shift register. The falling edge of BUSY can be
used as a data ready clock signal. Note that in master read after convert mode (SER/

Table 4.

30 TEN DI

RDC = low) the busy time changes according to

2

Input Range Select. Used in conjunction with BIPOLAR per the following:

Input Range BIPOLAR TEN

0 V to 5 V Low Low
0 V to 10 V Low High
±5 V High Low
±10 V High High

31
32

RD
CS

DI
DI

Read Data. When
Chip Select. When

CS

and RD are both low, the interface parallel or serial output bus is enabled.

CS

and RD are both low, the interface parallel or serial output bus is enabled. CS is also

used to gate the external clock in slave serial mode (not used for serial programmable port).

33 RESET DI Reset Input. When high, reset the AD7610. Current conversion, if any, is aborted. The falling edge of RESET

resets the data outputs to all zero’s (with OB/

2C

= high) and clears the configuration register. See the Digital

Interface section. If not used, this pin can be tied to OGND.

34 PD DI

2

Power-Down Input. When PD = high, power down the ADC. Power consumption is reduced and conversions
are inhibited after the current one is completed. The digital interface remains active during power down.

35

CNVST

DI

Conversion Start. A falling edge on

CNVST

puts the internal sample-and-hold into the hold state and initiates

a conversion.

36 BIPOLAR DI

2

Input Range Select. See description for Pin 30.

37 REF AI/O Reference Input/Output. When PDREF/PDBUF = low, the internal reference and buffer are enabled, producing 5 V

on this pin. When PDREF/PDBUF = high, the internal reference and buffer are disabled, allowing an externally
supplied voltage reference up to AVDD volts. Decoupling with at least a 22 F is required with or without the
internal reference and buffer. See the

Reference Decoupling section.

38 REFGND AI Reference Input Analog Ground. Connected to analog ground plane.
39 IN− AI Analog Input Ground Sense. Should be connected to the analog ground plane or to a remote sense ground.
40 VCC P High Voltage Positive Supply. Normally +7 V to +15 V.
41 VEE P High Voltage Negative Supply. Normally 0 V to −15 V (0 V in unipolar ranges).
43 IN+ AI Analog Input. Referenced to IN−.
45 TEMP AO Temperature Sensor Analog Output. Enabled when the internal reference is turned on (PDREF = PDBUF =

low). See the

Temperature Sensor section.

46 REFBUFIN AI Reference Buffer Input. When using an external reference with the internal reference buffer (PDBUF = low,

PDREF = high), applying 2.5 V on this pin produces 5 V on the REF pin. See the

47 PDREF DI Internal Reference Power-Down Input.

When low, the internal reference is enabled.
When high, the internal reference is powered down, and an external reference must be used.

48 PDBUF DI Internal Reference Buffer Power-Down Input.

When low, the buffer is enabled (must be low when using internal reference).
When high, the buffer is powered-down.

1

AI = analog input; AI/O = bidirectional analog; AO = analog output; DI = digital input; DI/O = bidirectional digital; DO = digital output; P = power.

2

In serial configuration mode (SER/

PAR

= high, HW/SW = low), this input is programmed with the serial configuration register and this pin is a don’t care. See the

Hardware Configuration section and Software Configuration section.

PAR

= high, HW/SW = low) this input is

PAR

= high, HW/SW = low) this

PAR

= high, EXT/

Voltage Reference Input section.

INT

= low,

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