How it Works
ANALOG DEVICES
Loading...
AD7609
Service Manual
36 pgs811.91 Kb0
Table of contents
Loading...

ANALOG DEVICES AD7609 Service Manual

Bipolar, Simultaneous Sampling ADC
AD7609
18 Bits
AD7608
AD76091
8
V1+ V1–
R
FB
R
FB
R
FB
R
FB
R
FB
R
FB
R
FB
R
FB
R
FB
R
FB
R
FB
R
FB
R
FB
R
FB
R
FB
R
FB
1MΩ
1MΩ
CLAMP CLAMP
T/H
V2+ V2–
1MΩ
1MΩ
CLAMP CLAMP
T/H
V3+ V3–
1MΩ
1MΩ
CLAMP CLAMP
T/H
V4+ V4–
1MΩ
1MΩ
CLAMP CLAMP
T/H
V5+ V5–
1MΩ
1MΩ
CLAMP CLAMP
T/H
V6+ V6–
1MΩ
1MΩ
CLAMP CLAMP
T/H
V7+ V7–
1MΩ
1MΩ
CLAMP CLAMP
T/H
V8+ V8–
1MΩ
1MΩ
CLAMP CLAMP
T/H
8:1
MUX
AGND
BUSY FRSTDATA
CONVST A
CONVST B
RESET
RANGE
CONTROL
INPUTS
CLK OSC
REFIN/REFOUT
REF SELECT AGND
OS 2 OS 1 OS 0
D
OUT
A
D
OUT
B
RD/SCLK CS
PAR/SER SEL V
DRIVE
18-BIT
SAR
DIGITAL
FILTER
PARALLEL/
SERIAL
INTERFACE
2.5V REF
REFCAPB
REFCAPA
SERIAL
PARALLEL
REGCAP
2.5V LDO
REGCAP
2.5V LDO
AV
CC
AV
CC
DB[15:0]
AD7609
09760-001
SECOND-
ORDER LPF
SECOND-
ORDER LPF
SECOND-
ORDER LPF
SECOND-
ORDER LPF
SECOND-
ORDER LPF
SECOND-
ORDER LPF
SECOND-
ORDER LPF
SECOND-
ORDER LPF
Data Sheet

FEATURES

8 simultaneously sampled inputs True differential inputs True bipolar analog input ranges: ±10 V, ±5 V Single 5 V analog supply and 2.3 V to 5.25 V V Fully integrated data acquisition solution
Analog input clamp protection Input buffer with 1 MΩ analog input impedance Second-order antialiasing analog filter On-chip accurate reference and reference buffer 18-bit ADC with 200 kSPS on all channels
Oversampling capability with digital filter Flexible parallel/serial interface SPI/QSPI™/MICROWIRE™/DSP compatible Performance
7 kV ESD rating on analog input channels
98 dB SNR, −107 dB THD
Dynamic range: up to 105 dB typical
Low power: 100 mW
Standby mode: 25 mW 64-lead LQFP package
8-Channel Differential DAS with 18-Bit,

APPLICATIONS

Power line monitoring and protection systems Multiphase motor control Instrumentation and control systems
DRIVE
Multiaxis positioning systems Data acquisition systems (DAS)

COMPANION PRODUCTS

External References: ADR421, ADR431 Digital Isolators: ADuM1402, ADuM5000, ADuM5402 Power: ADIsimPower, Supervisor Parametric Search
Additional companion products on the AD7609 product page
Table 1. High Resolution, Bipolar Input, Simultaneous Sampling DAS Solutions
Single­Ended
Resolution
Inputs
16 Bits AD7606 8 AD7606-6 6 AD7606-4 4 14 Bits AD7607 8
1
Patent pending.
True Differential Inputs
Number of Simultaneous Sampling Channels
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

FUNCTIONAL BLOCK DIAGRAM

Figure 1.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com
AD7609 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Companion Products ....................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
General Description ......................................................................... 3
Specifications ..................................................................................... 4
Timing Specifications .................................................................. 7
Absolute Maximum Ratings .......................................................... 11
Thermal Resistance .................................................................... 11
ESD Caution ................................................................................ 11
Pin Configuration and Function Descriptions ........................... 12
Typical Performance Characteristics ........................................... 15
Terminology .................................................................................... 19
Theory of Operation ...................................................................... 21
Converter Details ....................................................................... 21
Analog Input ............................................................................... 21
ADC Transfer Function ............................................................. 22
Internal/External Reference ...................................................... 23
Typical Connection Diagram ................................................... 24
Power-Down Modes .................................................................. 24
Conversion Control ................................................................... 25
Digital Interface .............................................................................. 26
Parallel Interface (
Serial Interface (
Reading During Conversion ..................................................... 27
Digital Filter ................................................................................ 28
Layout Guidelines....................................................................... 32
Outline Dimensions ....................................................................... 34
Ordering Guide .......................................................................... 34
PAR
/SER SEL = 0) ...................................... 26
PAR
/SER SEL = 1) ......................................... 26

REVISION HISTORY

2/12—Rev. 0 to R e v. A
Changes to Analog Input Ranges Section .................................... 21
7/11—Revision 0: Initial Version
Rev. A | Page 2 of 36
Data Sheet AD7609

GENERAL DESCRIPTION

The AD7609 is an 18-bit, 8-channel, true differential, simultaneous sampling analog-to-digital data acquisition system (DAS). The part contains analog input clamp protection, a second-order antialiasing filter, a track-and-hold amplifier, an 18-bit charge redistribution successive approximation analog­to-digital converter (ADC), a flexible digital filter, a 2.5 V reference and reference buffer, and high speed serial and parallel interfaces.
The AD7609 operates from a single 5 V supply and can accommodate ±10 V and ±5 V true bipolar differential input signals while sampling at throughput rates up to 200 kSPS for all channels. The input clamp protection circuitry can tolerate voltages up to ±16.5 V. T he AD7609 has 1 MΩ analog input impedance regardless of sampling frequency. The single supply operation, on-chip filtering, and high input impedance elimi­nate the need for driver op amps and external bipolar supplies. The AD7609 antialiasing filter has a −3 dB cutoff frequency of 32 kHz and provides 40 dB antialias rejection when sampling at 200 kSPS. The flexible digital filter is pin driven, yields improvements in SNR, and reduces the −3 dB bandwidth.
Rev. A | Page 3 of 36
AD7609 Data Sheet
DYNAMIC PERFORMANCE
fIN = 1 kHz sine wave unless otherwise noted
Peak Harmonic or Spurious Noise (SFDR)2
−108
dB
±5 V range
±90 LSB
Positive Full-Scale Error Matching2
±10 V range
12
80
LSB
Bipolar Zero Code Error Matching2
±10 V range
2.7
30
LSB
Negative Full-Scale Error Matching2
±10 V range
12
80
LSB

SPECIFICATIONS

V
= 2.5 V external/internal, AVCC = 4.75 V to 5.25 V, V
REF
1
noted.
Table 2.
Parameter Test Conditions/Comments Min Typ Max Unit
= 2.3 V to 5.25 V; f
DRIVE
= 200 kSPS, TA = T
SAMPLE
MIN
to T
, unless otherwise
MAX
Signal-to-Noise Ratio (SNR)
2, 3
Oversampling by 16; ±10 V range; fIN = 160 Hz 98 101 dB Oversampling by 16; ±5 V range; fIN = 160 Hz 100 dB No oversampling; ±10 V range 90 91 dB No oversampling; ±5 V range 89.5 90.5 dB Signal-to-(Noise + Distortion) (SINAD)2 No oversampling; ±10 V range 89.5 91 dB No oversampling; ±5 V range 89 90 dB Dynamic Range No oversampling; ±10 V range 91.5 dB No oversampling; ±5 V range 90.5 dB Total Harmonic Distortion (THD)
2, 3
No oversampling; ±10 V range −107 −97 dB
No oversampling; ±5 V range −110 −96 dB
Intermodulation Distortion (IMD)2 fa = 1 kHz, fb = 1.1 kHz
Second-Order Terms −110 dB Third-Order Terms −106 dB
Channel-to-Channel Isolation2 fIN on unselected channels up to 160 kHz −95 dB
ANALOG INPUT FILTER
Full Power Bandwidth −3 dB, ±10 V range 32 kHz
−3 dB, ±5 V range 23 kHz
−0.1 dB, ±10 V range 13 kHz
−0.1 dB, ±5 V range 10 kHz t
GROUP DELAY
±10 V range 7.1 µs
±5 V range 10.2 µs
DC ACCURACY
Resolution No missing codes 18 Bits Differential Nonlinearity2 ±0.75 −0.99/+2 LSB4 Integral Nonlinearity2 ±3 ±7.5 LSB Total Unadjusted Error (TUE) ±10 V range ±10 LSB
Positive Full-Scale Error
2, 5
External reference ±8 ±140 LSB Internal reference ±40 LSB Positive Full-Scale Error Drift External reference ±2 ppm/°C Internal reference ±7 ppm/°C
±5 V range 40 100 LSB Bipolar Zero Code Error2, 6 ±10 V range ±3 ±24 LSB ± 5 V range ±3 ±48 LSB Bipolar Zero Code Error Drift ±10 V range 10 µV/°C ± 5 V range 5 µV/°C
±5 V range 13 65 LSB Negative Full-Scale Error
2, 5
External reference ±8 ±140 LSB Internal reference ±40 LSB Negative Full-Scale Error Drift External reference ±4 ppm/°C Internal reference ±8 ppm/°C
±5 V range 40 100 LSB
Rev. A | Page 4 of 36
Data Sheet AD7609
Absolute Voltage Input
±10 V range, see the Analog Input Clamp
−10 +10
V
Analog Input Current
10 V, see Figure 28
5.4 µA
LOGIC INPUTS
CONVERSION RATE
Parameter Test Conditions/Comments Min Typ Max Unit
ANALOG INPUT
Differential Input Voltage Ranges VIN = Vx+ − (Vx−) RANGE = 1; ±10 V −20 +20 V RANGE = 0; ±5 V −10 +10 V
Protection section ±5 V range, see the Analog Input Clamp
Protection section Common-Mode Input Range −4 ±5 +4 V CMRR −70 dB
5 V, see Figure 28 2.5 µA Input Capacitance7 5 pF Input Impedance 1 MΩ
REFERENCE INPUT/OUTPUT
Reference Input Voltage Range 2.475 2.5 2.525 V DC Leakage Current ±1 µA Input Capacitance7 REF SELECT = 1 7.5 pF Reference Output Voltage REFIN/REFOUT
Reference Temperature Coefficient ±10 ppm/°C
−5 +5 V
2.49/
V
2.505
Input High Voltage (V Input Low Voltage (V
) 0.7 × V
INH
) 0.3 × V
INL
V
DRIVE
DRIVE
V Input Current (IIN) ±2 µA Input Capacitance (CIN)7 5 pF
LOGIC OUTPUTS
Output High Voltage (VOH) I Output Low Voltage (VOL) I
= 100 µA V
SOURCE
= 100 µA 0.2 V
SINK
− 0.2 V
DRIVE
Floating-State Leakage Current ±1 ±20 µA Floating-State Output Capacitance7 5 pF Output Coding Twos complement
Conversion Time All eight channels included 4 µs Track-and-Hold Acquisition Time 1 µs Throughput Rate Per channel, all eight channels included 200 kSPS
POWER REQUIREMENTS
AVCC 4.75 5.25 V V
2.3 5.25 V
DRIVE
I
Digital inputs = 0 V or V
TOTA L
DRIVE
Normal Mode (Static) 16 22 mA Normal Mode (Operational)8 f
= 200 kSPS 20 28.5 mA
SAMPLE
Standby Mode 5 8 mA Shutdown Mode 2 11 µA
Rev. A | Page 5 of 36
AD7609 Data Sheet
Shutdown Mode
10
60.5
µW
Parameter Test Conditions/Comments Min Typ Max Unit
Power Dissipation
Normal Mode (Static) 80 115.5 mW Normal Mode (Operational)8 f Standby Mode 25 42 mW
1
Temperature range for B version is −40°C to +85°C.
2
See the Terminology section.
3
This specification applies when reading during a conversion or after a conversion. If reading during a conversion in parallel and serial modes with V
by 1.5 dB and THD by 3 dB.
4
LSB means least significant bit. With ±5 V input range, 1 LSB = 76.29 µV. With ±10 V input range, 1 LSB = 152.58 µV.
5
These specifications include the full temperature range variation and contribution from the internal reference buffer but do not include the error contribution from
the external reference.
6
Bipolar zero code error is calculated with respect to the analog input voltage. See the Analog Input Clamp Protection section.
7
Sample tested during initial release to ensure compliance.
8
Operational power/current figure includes contribution when running in oversampling mode.
= 200 kSPS 100 157 mW
SAMPLE
= 5 V, SNR typically reduces
DRIVE
Rev. A | Page 6 of 36
Data Sheet AD7609
t
Conversion time
133 158
µs
Oversampling by 32
t1
45
ns
CONVST x high to BUSY high
t8 0 ns
CS to RD setup time
37
ns
V
above 2.3 V

TIMING SPECIFICATIONS

AVCC = 4.75 V to 5.25 V, V unless otherwise noted.
Table 3.
Limit at T Parameter Min Ty p Max Unit Description
PARALLEL/SERIAL/BYTE MODE
t
1/throughput rate
CYCLE
5 µs
5 µs Parallel mode reading after conversion V
10.1 µs Serial mode reading after conversion; V
11.5 µs Serial mode reading after a conversion; V
CONV
3.45 4 4.15 µs Oversampling off
7.87 9.1 µs Oversampling by 2
16.05 18.8 µs Oversampling by 4 33 39 µs Oversampling by 8 66 78 µs Oversampling by 16
= 2.3 V to 5.25 V, V
DRIVE
1
MIN
= 2.5 V external reference/ internal reference, TA = T
REF
, T
MAX
Parallel mode, reading during; or after conversion V serial mode: V and D
OUT
B lines
= 3.3 V to 5.25 V, reading during a conversion using D
DRIVE
DRIVE
= 2.7 V, D
DRIVE
DRIVE
to T
MIN
= 2.3 V
= 2.3 V, D
,
MAX
= 2.7 V to 5.25 V; or
DRIVE
A and D
OUT
OUT
A and D
OUT
OUT
B lines
B lines
OUT
A
257 315 µs Oversampling by 64 t
WAKE -UP STANDBY
t
WAKE -UP SHUTDOWN
Internal Reference 30 ms
100 µs
STBY rising edge to CONVST x rising edge; power-up time from standby mode
STBY rising edge to CONVST x rising edge; power-up time from shutdown mode
External Reference 13 ms
STBY rising edge to CONVST x rising edge; power-up time from shutdown mode
t
50 ns RESET high pulse width
RESET
t
20 ns BUSY to OS x pin setup time
OS_SETUP
t
OS_HOLD
20 ns BUSY to OS x pin hold time
t2 25 ns Minimum CONVST x low pulse t3 25 ns Minimum CONVST x high pulse t4 0 ns
2
t
0.5 ms Maximum delay allowed between CONVST A, CONVST B rising edges
5
t6 25 ns
BUSY falling edge to
Maximum time between last
CS falling edge setup time
CS rising edge and BUSY falling edge
t7 25 ns Minimum delay between RESET low to CONVST x high
PARALLEL READ OPERATION
t9 0 ns t10 19 ns V
24 ns V 30 ns V
t11 15 ns t12 22 ns
CS to RD hold time RD low pulse width
above 4.75 V
DRIVE
above 3.3 V
DRIVE
above 2.7 V
DRIVE
DRIVE
RD high pulse width CS high pulse width (see Figure 5); CS and RD linked
Rev. A | Page 7 of 36
AD7609 Data Sheet
30
ns
V
above 2.7 V
23
ns
V
above 3.3 V
23
ns
V
above 3.3 V
Limit at T Parameter Min Ty p Max Unit Description
t13 19 ns V
24 ns V 30 ns V 37 ns V
3
t
14
19 ns V 24 ns V
37 ns V t15 6 ns
t16 6 ns t17 22 ns
SERIAL READ OPERATION
f
Frequency of serial read clock
SCLK
20 MHz V 15 MHz V
12.5 MHz V 10 MHz V t18
18 ns V
35 ns V
3
t
Data access time after SCLK rising edge
19
20 ns V 26 ns V 32 ns V 39 ns V t20 0.4 t t21 0.4 t
SCLK
SCLK
t22 7 SCLK rising edge to D t23 22 ns
FRSTDATA OPERATION
t24 18 ns V
30 ns V 35 ns V t25 ns
18 ns V 23 ns V 30 ns V 35 ns V t26 19 ns V 23 ns V 30 ns V 35 ns V
, T
MIN
MAX
Delay from
above 4.75 V
DRIVE
above 3.3 V
DRIVE
above 2.7 V
DRIVE
above 2.3 V
DRIVE
CS until DB[15:0] three-state disabled
Data access time after
above 4.75 V
DRIVE
above 3.3 V
DRIVE
DRIVE
above 2.3 V
DRIVE
Data hold time after
RD falling edge CS to DB[15:0] hold time Delay from
DRIVE
DRIVE
DRIVE
DRIVE
Delay from
CS rising edge to DB[15:0] three-state enabled
above 4.75 V above 3.3 V above 2.7 V above 2.3 V
CS until D
OUT
MSB valid
above 4.75 V
DRIVE
DRIVE
= 2.3 V to 2.7 V
DRIVE
above 4.75 V
DRIVE
above 3.3 V
DRIVE
above 2.7 V
DRIVE
above 2.3 V
DRIVE
ns SCLK low pulse width ns SCLK high pulse width
CS rising edge to D
Delay from
above 4.75 V
DRIVE
DRIVE
above 2.7 V
DRIVE
above 2.3 V
DRIVE
Delay from
above 4.75 V
DRIVE
above 3.3 V
DRIVE
above 2.7 V
DRIVE
above 2.3 V
DRIVE
Delay from
above 4.75 V
DRIVE
above 3.3 V
DRIVE
above 2.7 V
DRIVE
above 2.3 V
DRIVE
OUT
CS falling edge until FRSTDATA three-state disabled
CS falling edge until FRSTDATA high, serial mode
RD falling edge to FRSTDATA high
RD falling edge
A/D
B three-state disabled/delay from CS until
OUT
A/D
OUT
A/D
B valid hold time
OUT
B three-state enabled
OUT
Rev. A | Page 8 of 36
Data Sheet AD7609
t
CYCLE
t
3
t
5
t
2
t
4
t
1
t
7
t
RESET
t
CONV
CONVST A/
CONVST B
CONVST A/
CONVST B
BUSY
CS
RESET
09760-002
t
CYCLE
t
3
t
5
t
6
t
2
t
1
t
CONV
CONVST A/
CONVST B
CONVST A/
CONVST B
BUSY
CS
t
7
t
RESET
RESET
09760-003
DATA:
DB[15:0]
FRSTDATA
CS
RD
INVALID
V1
[17:2]
V1
[1:0]
V2
[17:2]
V8
[17:2]
V8
[1:0]
V2
[1:0]
t
10
t
8
t
13
t
24
t
26
t
27
t
14
t
11
t
9
t
16
t
17
t
29
t
15
09760-004
Limit at T Parameter Min Ty p Max Unit Description
t27 22 ns V
29 ns V t28 Delay from 18th SCLK falling edge to FRSTDATA low 20 ns V 27 ns V t29 29 ns
1
Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (30% to 70% of VDD) and timed from a voltage level of 1.6 V.
2
The delay between the CONVST x signals was measured as the maximum time allowed while ensuring a <40 LSB performance matching between channel sets.
3
A buffer is used on the data output pins for these measurements, which is equivalent to a load of 20 pF on the output pins.

Timing Diagrams

MIN
, T
MAX
Delay from
= 3.3 V to 5.25 V
DRIVE
= 2.3 V to 2.7 V
DRIVE
= 3.3 V to 5.25 V
DRIVE
= 2.3 V to 2.7 V
DRIVE
Delay from
RD falling edge to FRSTDATA low
CS rising edge until FRSTDATA three-state enabled
Figure 2. CONVST x Timing—Reading After a Conversion
Figure 3. CONVST x Timing—Reading During a Conversion
Figure 4. Parallel Mode Separate
Rev. A | Page 9 of 36
CS
and RD Pulses
AD7609 Data Sheet
DATA:
DB[15:0]
FRSTDATA
CS, RD
V1
[17:2]V1[1:0]V2[17:2]
V2
[1:0]
V7
[17:2]V7[1:0]V8[17:2]V8[1:0]
t
12
t
13
t
16
t
17
09760-005
SCLK
D
OUT
A,
D
OUT
B
FRSTDATA
CS
DB17 DB14
DB13
DB1 DB0
t
18
t
19
t
21
t
20
t
23
t
29
t
28
t
25
t
22
09760-006
CS
Figure 5.
and RD Linked Parallel Mode
Figure 6. Serial Read Operation
Rev. A | Page 10 of 36
Data Sheet AD7609
V
to AGND
−0.3 V to AVCC + 0.3 V
Input Current to Any Pin Except
±10 mA Pb/SN Temperature, Soldering

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.
Table 4.
Parameter Rating
AVCC to AGND −0.3 V to +7 V
DRIVE
Analog Input Voltage to AGND1 ±16.5 V Digital Input Voltage to AGND −0.3 V to V Digital Output Voltage to AGND −0.3 V to V REFIN to AGND −0.3 V to AVCC + 0.3 V
Supplies1
Operating Temperature Range
B Version −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C
Reflow (10 sec to 30 sec) 240(+0)°C Pb-Free Temperature, Soldering Reflow 260(+0)°C ESD (All Pins Except Analog Inputs) 2 kV ESD (Analog Input Pins Only) 7 kV
1
Transient currents of up to 100 mA do not cause SCR latch-up.
DRIVE
DRIVE
+ 0.3 V + 0.3 V
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. These specifications apply to a 4-layer board.
Table 5. Thermal Resistance
Package Type θJA θJC Unit
64-Lead LQFP 45 11 °C/W

ESD CAUTION

Rev. A | Page 11 of 36
Loading...
+ 25 hidden pages
Buy Points How it Works FAQ Contact Us Questions and Suggestions Privacy Policy Cookie Policy Terms of Use