Datasheet AD7609 Datasheet (ANALOG DEVICES)

Bipolar, Simultaneous Sampling ADC

AD7609

Rev. A

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18 Bits

AD7608

AD76091

8

V1+
V1–

R

FB

R

FB

R

FB

R

FB

R

FB

R

FB

R

FB

R

FB

R

FB

R

FB

R

FB

R

FB

R

FB

R

FB

R

FB

R

FB

1MΩ

1MΩ

CLAMP
CLAMP

T/H

V2+
V2–

1MΩ

1MΩ

CLAMP
CLAMP

T/H

V3+
V3–

1MΩ

1MΩ

CLAMP
CLAMP

T/H

V4+
V4–

1MΩ

1MΩ

CLAMP
CLAMP

T/H

V5+
V5–

1MΩ

1MΩ

CLAMP
CLAMP

T/H

V6+
V6–

1MΩ

1MΩ

CLAMP
CLAMP

T/H

V7+
V7–

1MΩ

1MΩ

CLAMP
CLAMP

T/H

V8+
V8–

1MΩ

1MΩ

CLAMP
CLAMP

T/H

8:1

MUX

AGND

BUSY
FRSTDATA

CONVST A

CONVST B

RESET

RANGE

CONTROL

INPUTS

CLK OSC

REFIN/REFOUT

REF SELECT
AGND

OS 2
OS 1
OS 0

D

OUT

A

D

OUT

B

RD/SCLK
CS

PAR/SER SEL
V

DRIVE

18-BIT

SAR

DIGITAL

FILTER

PARALLEL/

SERIAL

INTERFACE

2.5V
REF

REFCAPB

REFCAPA

SERIAL

PARALLEL

REGCAP

2.5V
LDO

REGCAP

2.5V
LDO

AV

CC

AV

CC

DB[15:0]

AD7609

09760-001

SECOND-

ORDER LPF

SECOND-

ORDER LPF

SECOND-

ORDER LPF

SECOND-

ORDER LPF

SECOND-

ORDER LPF

SECOND-

ORDER LPF

SECOND-

ORDER LPF

SECOND-

ORDER LPF

Data Sheet

FEATURES

8 simultaneously sampled inputs
True differential inputs
True bipolar analog input ranges: ±10 V, ±5 V
Single 5 V analog supply and 2.3 V to 5.25 V V
Fully integrated data acquisition solution

Analog input clamp protection
Input buffer with 1 MΩ analog input impedance
Second-order antialiasing analog filter
On-chip accurate reference and reference buffer
18-bit ADC with 200 kSPS on all channels

Oversampling capability with digital filter
Flexible parallel/serial interface
SPI/QSPI™/MICROWIRE™/DSP compatible
Performance

7 kV ESD rating on analog input channels

98 dB SNR, −107 dB THD

Dynamic range: up to 105 dB typical

Low power: 100 mW

Standby mode: 25 mW
64-lead LQFP package

8-Channel Differential DAS with 18-Bit,

APPLICATIONS

Power line monitoring and protection systems
Multiphase motor control
Instrumentation and control systems

DRIVE

Multiaxis positioning systems
Data acquisition systems (DAS)

COMPANION PRODUCTS

External References: ADR421, ADR431
Digital Isolators: ADuM1402, ADuM5000, ADuM5402
Power: ADIsimPower, Supervisor Parametric Search

Additional companion products on the AD7609 product page

Table 1. High Resolution, Bipolar Input, Simultaneous
Sampling DAS Solutions

Single­Ended

Resolution

Inputs

16 Bits AD7606 8
AD7606-6 6
AD7606-4 4
14 Bits AD7607 8

1

Patent pending.

True
Differential
Inputs

Number of
Simultaneous
Sampling Channels

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com

AD7609 Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

Companion Products ....................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

General Description ......................................................................... 3

Specifications ..................................................................................... 4

Timing Specifications .................................................................. 7

Absolute Maximum Ratings .......................................................... 11

Thermal Resistance .................................................................... 11

ESD Caution ................................................................................ 11

Pin Configuration and Function Descriptions ........................... 12

Typical Performance Characteristics ........................................... 15

Terminology .................................................................................... 19

Theory of Operation ...................................................................... 21

Converter Details ....................................................................... 21

Analog Input ............................................................................... 21

ADC Transfer Function ............................................................. 22

Internal/External Reference ...................................................... 23

Typical Connection Diagram ................................................... 24

Power-Down Modes .................................................................. 24

Conversion Control ................................................................... 25

Digital Interface .............................................................................. 26

Parallel Interface (

Serial Interface (

Reading During Conversion ..................................................... 27

Digital Filter ................................................................................ 28

Layout Guidelines....................................................................... 32

Outline Dimensions ....................................................................... 34

Ordering Guide .......................................................................... 34

PAR

/SER SEL = 0) ...................................... 26

PAR

/SER SEL = 1) ......................................... 26

REVISION HISTORY

2/12—Rev. 0 to R e v. A

Changes to Analog Input Ranges Section .................................... 21

7/11—Revision 0: Initial Version

Rev. A | Page 2 of 36

Data Sheet AD7609

GENERAL DESCRIPTION

The AD7609 is an 18-bit, 8-channel, true differential,
simultaneous sampling analog-to-digital data acquisition
system (DAS). The part contains analog input clamp protection,
a second-order antialiasing filter, a track-and-hold amplifier, an
18-bit charge redistribution successive approximation analog­to-digital converter (ADC), a flexible digital filter, a 2.5 V
reference and reference buffer, and high speed serial and
parallel interfaces.

The AD7609 operates from a single 5 V supply and can
accommodate ±10 V and ±5 V true bipolar differential input
signals while sampling at throughput rates up to 200 kSPS for
all channels. The input clamp protection circuitry can tolerate
voltages up to ±16.5 V. T he AD7609 has 1 MΩ analog input
impedance regardless of sampling frequency. The single supply
operation, on-chip filtering, and high input impedance elimi­nate the need for driver op amps and external bipolar supplies.
The AD7609 antialiasing filter has a −3 dB cutoff frequency of
32 kHz and provides 40 dB antialias rejection when sampling
at 200 kSPS. The flexible digital filter is pin driven, yields
improvements in SNR, and reduces the −3 dB bandwidth.

Rev. A | Page 3 of 36

AD7609 Data Sheet

DYNAMIC PERFORMANCE

fIN = 1 kHz sine wave unless otherwise noted

Peak Harmonic or Spurious Noise (SFDR)2

−108

dB

±5 V range

±90 LSB

Positive Full-Scale Error Matching2

±10 V range

12

80

LSB

Bipolar Zero Code Error Matching2

±10 V range

2.7

30

LSB

Negative Full-Scale Error Matching2

±10 V range

12

80

LSB

SPECIFICATIONS

V

= 2.5 V external/internal, AVCC = 4.75 V to 5.25 V, V

REF

1

noted.

Table 2.

Parameter Test Conditions/Comments Min Typ Max Unit

= 2.3 V to 5.25 V; f

DRIVE

= 200 kSPS, TA = T

SAMPLE

MIN

to T

, unless otherwise

MAX

Signal-to-Noise Ratio (SNR)

2, 3

Oversampling by 16; ±10 V range; fIN = 160 Hz 98 101 dB
Oversampling by 16; ±5 V range; fIN = 160 Hz 100 dB
No oversampling; ±10 V range 90 91 dB
No oversampling; ±5 V range 89.5 90.5 dB
Signal-to-(Noise + Distortion) (SINAD)2 No oversampling; ±10 V range 89.5 91 dB
No oversampling; ±5 V range 89 90 dB
Dynamic Range No oversampling; ±10 V range 91.5 dB
No oversampling; ±5 V range 90.5 dB
Total Harmonic Distortion (THD)

2, 3

No oversampling; ±10 V range −107 −97 dB

No oversampling; ±5 V range −110 −96 dB

Intermodulation Distortion (IMD)2 fa = 1 kHz, fb = 1.1 kHz

Second-Order Terms −110 dB
Third-Order Terms −106 dB

Channel-to-Channel Isolation2 fIN on unselected channels up to 160 kHz −95 dB

ANALOG INPUT FILTER

Full Power Bandwidth −3 dB, ±10 V range 32 kHz

−3 dB, ±5 V range 23 kHz

−0.1 dB, ±10 V range 13 kHz

−0.1 dB, ±5 V range 10 kHz
t

GROUP DELAY

±10 V range 7.1 µs

±5 V range 10.2 µs

DC ACCURACY

Resolution No missing codes 18 Bits
Differential Nonlinearity2 ±0.75 −0.99/+2 LSB4
Integral Nonlinearity2 ±3 ±7.5 LSB
Total Unadjusted Error (TUE) ±10 V range ±10 LSB

Positive Full-Scale Error

2, 5

External reference ±8 ±140 LSB
Internal reference ±40 LSB
Positive Full-Scale Error Drift External reference ±2 ppm/°C
Internal reference ±7 ppm/°C

±5 V range 40 100 LSB
Bipolar Zero Code Error2, 6 ±10 V range ±3 ±24 LSB
± 5 V range ±3 ±48 LSB
Bipolar Zero Code Error Drift ±10 V range 10 µV/°C
± 5 V range 5 µV/°C

±5 V range 13 65 LSB
Negative Full-Scale Error

2, 5

External reference ±8 ±140 LSB
Internal reference ±40 LSB
Negative Full-Scale Error Drift External reference ±4 ppm/°C
Internal reference ±8 ppm/°C

±5 V range 40 100 LSB

Rev. A | Page 4 of 36

Data Sheet AD7609

Absolute Voltage Input

±10 V range, see the Analog Input Clamp

−10 +10

V

Analog Input Current

10 V, see Figure 28

5.4 µA

LOGIC INPUTS

CONVERSION RATE

Parameter Test Conditions/Comments Min Typ Max Unit

ANALOG INPUT

Differential Input Voltage Ranges VIN = Vx+ − (Vx−)
RANGE = 1; ±10 V −20 +20 V
RANGE = 0; ±5 V −10 +10 V

Protection section
±5 V range, see the Analog Input Clamp

Protection section
Common-Mode Input Range −4 ±5 +4 V
CMRR −70 dB

5 V, see Figure 28 2.5 µA
Input Capacitance7 5 pF
Input Impedance 1 MΩ

REFERENCE INPUT/OUTPUT

Reference Input Voltage Range 2.475 2.5 2.525 V
DC Leakage Current ±1 µA
Input Capacitance7 REF SELECT = 1 7.5 pF
Reference Output Voltage REFIN/REFOUT

Reference Temperature Coefficient ±10 ppm/°C

−5 +5 V

2.49/

V

2.505

Input High Voltage (V
Input Low Voltage (V

) 0.7 × V

INH

) 0.3 × V

INL

V

DRIVE

DRIVE

V
Input Current (IIN) ±2 µA
Input Capacitance (CIN)7 5 pF

LOGIC OUTPUTS

Output High Voltage (VOH) I
Output Low Voltage (VOL) I

= 100 µA V

SOURCE

= 100 µA 0.2 V

SINK

− 0.2 V

DRIVE

Floating-State Leakage Current ±1 ±20 µA
Floating-State Output Capacitance7 5 pF
Output Coding Twos complement

Conversion Time All eight channels included 4 µs
Track-and-Hold Acquisition Time 1 µs
Throughput Rate Per channel, all eight channels included 200 kSPS

POWER REQUIREMENTS

AVCC 4.75 5.25 V
V

2.3 5.25 V

DRIVE

I

Digital inputs = 0 V or V

TOTA L

DRIVE

Normal Mode (Static) 16 22 mA
Normal Mode (Operational)8 f

= 200 kSPS 20 28.5 mA

SAMPLE

Standby Mode 5 8 mA
Shutdown Mode 2 11 µA

Rev. A | Page 5 of 36

AD7609 Data Sheet

Shutdown Mode

10

60.5

µW

Parameter Test Conditions/Comments Min Typ Max Unit

Power Dissipation

Normal Mode (Static) 80 115.5 mW
Normal Mode (Operational)8 f
Standby Mode 25 42 mW

1

Temperature range for B version is −40°C to +85°C.

2

See the Terminology section.

3

This specification applies when reading during a conversion or after a conversion. If reading during a conversion in parallel and serial modes with V

by 1.5 dB and THD by 3 dB.

4

LSB means least significant bit. With ±5 V input range, 1 LSB = 76.29 µV. With ±10 V input range, 1 LSB = 152.58 µV.

5

These specifications include the full temperature range variation and contribution from the internal reference buffer but do not include the error contribution from

the external reference.

6

Bipolar zero code error is calculated with respect to the analog input voltage. See the Analog Input Clamp Protection section.

7

Sample tested during initial release to ensure compliance.

8

Operational power/current figure includes contribution when running in oversampling mode.

= 200 kSPS 100 157 mW

SAMPLE

= 5 V, SNR typically reduces

DRIVE

Rev. A | Page 6 of 36

Data Sheet AD7609

t

Conversion time

133 158

µs

Oversampling by 32

t1

45

ns

CONVST x high to BUSY high

t8 0 ns

CS to RD setup time

37

ns

V

above 2.3 V

TIMING SPECIFICATIONS

AVCC = 4.75 V to 5.25 V, V
unless otherwise noted.

Table 3.

Limit at T
Parameter Min Ty p Max Unit Description

PARALLEL/SERIAL/BYTE MODE

t

1/throughput rate

CYCLE

5 µs

5 µs Parallel mode reading after conversion V

10.1 µs Serial mode reading after conversion; V

11.5 µs Serial mode reading after a conversion; V

CONV

3.45 4 4.15 µs Oversampling off

7.87 9.1 µs Oversampling by 2

16.05 18.8 µs Oversampling by 4
33 39 µs Oversampling by 8
66 78 µs Oversampling by 16

= 2.3 V to 5.25 V, V

DRIVE

1

MIN

= 2.5 V external reference/ internal reference, TA = T

REF

, T

MAX

Parallel mode, reading during; or after conversion V
serial mode: V
and D

OUT

B lines

= 3.3 V to 5.25 V, reading during a conversion using D

DRIVE

DRIVE

= 2.7 V, D

DRIVE

DRIVE

to T

MIN

= 2.3 V

= 2.3 V, D

,

MAX

= 2.7 V to 5.25 V; or

DRIVE

A and D

OUT

OUT

A and D

OUT

OUT

B lines

B lines

OUT

A

257 315 µs Oversampling by 64
t

WAKE -UP STANDBY

t

WAKE -UP SHUTDOWN

Internal Reference 30 ms

100 µs

STBY rising edge to CONVST x rising edge; power-up time from standby mode

STBY rising edge to CONVST x rising edge; power-up time from
shutdown mode

External Reference 13 ms

STBY rising edge to CONVST x rising edge; power-up time from
shutdown mode

t

50 ns RESET high pulse width

RESET

t

20 ns BUSY to OS x pin setup time

OS_SETUP

t

OS_HOLD

20 ns BUSY to OS x pin hold time

t2 25 ns Minimum CONVST x low pulse
t3 25 ns Minimum CONVST x high pulse
t4 0 ns

2

t

0.5 ms Maximum delay allowed between CONVST A, CONVST B rising edges

5

t6 25 ns

BUSY falling edge to

Maximum time between last

CS falling edge setup time

CS rising edge and BUSY falling edge

t7 25 ns Minimum delay between RESET low to CONVST x high

PARALLEL READ OPERATION

t9 0 ns
t10
19 ns V

24 ns V
30 ns V

t11 15 ns
t12 22 ns

CS to RD hold time
RD low pulse width

above 4.75 V

DRIVE

above 3.3 V

DRIVE

above 2.7 V

DRIVE

DRIVE

RD high pulse width
CS high pulse width (see Figure 5); CS and RD linked

Rev. A | Page 7 of 36

AD7609 Data Sheet

30

ns

V

above 2.7 V

23

ns

V

above 3.3 V

23

ns

V

above 3.3 V

Limit at T
Parameter Min Ty p Max Unit Description

t13
19 ns V

24 ns V
30 ns V
37 ns V

3

t

14

19 ns V
24 ns V

37 ns V
t15 6 ns

t16 6 ns
t17 22 ns

SERIAL READ OPERATION

f

Frequency of serial read clock

SCLK

20 MHz V
15 MHz V

12.5 MHz V
10 MHz V
t18

18 ns V

35 ns V

3

t

Data access time after SCLK rising edge

19

20 ns V
26 ns V
32 ns V
39 ns V
t20 0.4 t
t21 0.4 t

SCLK

SCLK

t22 7 SCLK rising edge to D
t23 22 ns

FRSTDATA OPERATION

t24
18 ns V

30 ns V
35 ns V
t25 ns

18 ns V
23 ns V
30 ns V
35 ns V
t26
19 ns V
23 ns V
30 ns V
35 ns V

, T

MIN

MAX

Delay from

above 4.75 V

DRIVE

above 3.3 V

DRIVE

above 2.7 V

DRIVE

above 2.3 V

DRIVE

CS until DB[15:0] three-state disabled

Data access time after

above 4.75 V

DRIVE

above 3.3 V

DRIVE

DRIVE

above 2.3 V

DRIVE

Data hold time after

RD falling edge
CS to DB[15:0] hold time
Delay from

DRIVE

DRIVE

DRIVE

DRIVE

Delay from

CS rising edge to DB[15:0] three-state enabled

above 4.75 V
above 3.3 V
above 2.7 V
above 2.3 V

CS until D

OUT

MSB valid

above 4.75 V

DRIVE

DRIVE

= 2.3 V to 2.7 V

DRIVE

above 4.75 V

DRIVE

above 3.3 V

DRIVE

above 2.7 V

DRIVE

above 2.3 V

DRIVE

ns SCLK low pulse width
ns SCLK high pulse width

CS rising edge to D

Delay from

above 4.75 V

DRIVE

DRIVE

above 2.7 V

DRIVE

above 2.3 V

DRIVE

Delay from

above 4.75 V

DRIVE

above 3.3 V

DRIVE

above 2.7 V

DRIVE

above 2.3 V

DRIVE

Delay from

above 4.75 V

DRIVE

above 3.3 V

DRIVE

above 2.7 V

DRIVE

above 2.3 V

DRIVE

OUT

CS falling edge until FRSTDATA three-state disabled

CS falling edge until FRSTDATA high, serial mode

RD falling edge to FRSTDATA high

RD falling edge

A/D

B three-state disabled/delay from CS until

OUT

A/D

OUT

A/D

B valid hold time

OUT

B three-state enabled

OUT

Rev. A | Page 8 of 36

Data Sheet AD7609

t

CYCLE

t

3

t

5

t

2

t

4

t

1

t

7

t

RESET

t

CONV

CONVST A/

CONVST B

CONVST A/

CONVST B

BUSY

CS

RESET

09760-002

t

CYCLE

t

3

t

5

t

6

t

2

t

1

t

CONV

CONVST A/

CONVST B

CONVST A/

CONVST B

BUSY

CS

t

7

t

RESET

RESET

09760-003

DATA:

DB[15:0]

FRSTDATA

CS

RD

INVALID

V1

[17:2]

V1

[1:0]

V2

[17:2]

V8

[17:2]

V8

[1:0]

V2

[1:0]

t

10

t

8

t

13

t

24

t

26

t

27

t

14

t

11

t

9

t

16

t

17

t

29

t

15

09760-004

Limit at T
Parameter Min Ty p Max Unit Description

t27
22 ns V

29 ns V
t28 Delay from 18th SCLK falling edge to FRSTDATA low
20 ns V
27 ns V
t29 29 ns

1

Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (30% to 70% of VDD) and timed from a voltage level of 1.6 V.

2

The delay between the CONVST x signals was measured as the maximum time allowed while ensuring a <40 LSB performance matching between channel sets.

3

A buffer is used on the data output pins for these measurements, which is equivalent to a load of 20 pF on the output pins.

Timing Diagrams

MIN

, T

MAX

Delay from

= 3.3 V to 5.25 V

DRIVE

= 2.3 V to 2.7 V

DRIVE

= 3.3 V to 5.25 V

DRIVE

= 2.3 V to 2.7 V

DRIVE

Delay from

RD falling edge to FRSTDATA low

CS rising edge until FRSTDATA three-state enabled

Figure 2. CONVST x Timing—Reading After a Conversion

Figure 3. CONVST x Timing—Reading During a Conversion

Figure 4. Parallel Mode Separate

Rev. A | Page 9 of 36

CS

and RD Pulses

AD7609 Data Sheet

DATA:

DB[15:0]

FRSTDATA

CS, RD

V1

[17:2]V1[1:0]V2[17:2]

V2

[1:0]

V7

[17:2]V7[1:0]V8[17:2]V8[1:0]

t

12

t

13

t

16

t

17

09760-005

SCLK

D

OUT

A,

D

OUT

B

FRSTDATA

CS

DB17 DB14

DB13

DB1 DB0

t

18

t

19

t

21

t

20

t

23

t

29

t

28

t

25

t

22

09760-006

CS

Figure 5.

and RD Linked Parallel Mode

Figure 6. Serial Read Operation

Rev. A | Page 10 of 36

Data Sheet AD7609

V

to AGND

−0.3 V to AVCC + 0.3 V

Input Current to Any Pin Except

±10 mA
Pb/SN Temperature, Soldering

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 4.

Parameter Rating

AVCC to AGND −0.3 V to +7 V

DRIVE

Analog Input Voltage to AGND1 ±16.5 V
Digital Input Voltage to AGND −0.3 V to V
Digital Output Voltage to AGND −0.3 V to V
REFIN to AGND −0.3 V to AVCC + 0.3 V

Supplies1

Operating Temperature Range

B Version −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C

Reflow (10 sec to 30 sec) 240(+0)°C
Pb-Free Temperature, Soldering Reflow 260(+0)°C
ESD (All Pins Except Analog Inputs) 2 kV
ESD (Analog Input Pins Only) 7 kV

1

Transient currents of up to 100 mA do not cause SCR latch-up.

DRIVE

DRIVE

+ 0.3 V
+ 0.3 V

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages. These
specifications apply to a 4-layer board.

Table 5. Thermal Resistance

Package Type θJA θJC Unit

64-Lead LQFP 45 11 °C/W

ESD CAUTION

Rev. A | Page 11 of 36

AD7609 Data Sheet

AD7609

TOP VIEW

(Not to S cale)

64 63 62 61 60 59 58 57

V1–

56 55 54 53 52 51 50 49

V5+

V4+

V6+

V3+

V2+

V1+

PIN 1

V7+

V8+

V2–

V3–

V4–

V5–

V6–

V7–

V8–

DB13

DB12

DB11

DB14

V

DRIVE

DB1

17 18 19 20 21 22 23 24 25

AGND

26 27 28 29 30 31 32

DB2

DB3

DB4

DB5

DB6

DB7/D

OUT

A

DB9

DB10

DB8/D

OUT

B

AGND

AV

CC

1

3
4

FRSTDATA

7

6

5

OS 2

2

8
9

10

12
13
14
15
16

11

DB0

BUSY

CONVST B

CONVST A

RANGE

RESET

RD/SCLK

CS

PAR/SER SEL

OS 1

OS 0

STBY

DECOUPLI NG CAPACITOR P IN

DATA OUTPUT

POWER SUPPLY

ANALOG I NP UT

GROUND PIN

DIGITAL OUTPUT
DIGITAL INPUT
REFERENCE I NP UT/OUTPUT

DB15

REFIN/REFOUT

48

46

45

42

43

44

47

41

40

39

37
36
35
34
33

38

AGND

AV

CC

REFGND

REFCAPA

AGND

AGND

AGND

REFCAPB

REFGND

REGCAP

REGCAP

AV

CC

AV

CC

REF SELECT

09760-007

1, 37, 38, 48

P

AVCC

AI+

V1+ to V8+

42

REF

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Table 6. Pin Function Descriptions

Pin No. Type1 Mnemonic Description

2, 26, 35,
40, 41, 47

23 P V

36, 39 P REGCAP

49, 51, 53,
55, 57, 59,
61, 63

50, 52, 54,
56, 58, 60,
62, 64

34 DI REF SELECT

44, 45 REF

43, 46 REF REFGND Reference Ground Pins. These pins should be connected to AGND.

P AGND

DRIVE

AI− V1− to V8−

REFIN/
REFOUT

REFCAPA,
REFCAPB

Figure 7. Pin Configuration

Analog Supply Voltage 4.75 V to 5.25 V. This supply voltage is applied to the internal front-end
amplifiers and to the ADC core. These supply pins should be decoupled to AGND.

Analog Ground. This pin is the ground reference point for all analog circuitry on the AD7609. All
analog input signals and external reference signals should be referred to these pins. All six of these
AGND pins should connect to the AGND plane of a system.

Logic Power Supply Input. The voltage (2.3 V to 5 V) supplied at this pin determines the operating
voltage of the interface. This pin is nominally at the same supply as the supply of the host interface
(that is, DSP, FPGA).

Decoupling Capacitor Pins for Voltage Output from Internal Regulator. These output pins should be
decoupled separately to AGND using a 1 μF capacitor. The voltage on these output pins is in the
range of 2.5 V to 2.7 V.

Analog Input V1+ to Analog Input V8+. These pins are the positive terminal of the true differential
analog inputs. The analog input range of these channels is determined by the RANGE pin.

Analog Input V1− to Analog Input V8−. These are the negative terminals of the true differential
analog inputs. The analog input range of these channels is determined by the RANGE pin. The signal
on this pin should be 180° out of phase with the corresponding Vx+ pin.

Reference Input/ Reference Output. The on-chip reference of 2.5 V is available on this pin for external
use if the REF SELECT pin is set to a logic high. Alternatively, the internal reference can be disabled by
setting the REF SELECT pin to a logic low and an external reference of 2.5 V can be applied to this
input. See the Internal/External Reference section. Decoupling is required on this pin for both the
internal or external reference options. A 10 µF capacitor should be applied from this pin to ground
close to the REFGND pins.

Internal/External Reference Selection Input. Logic input. If this pin is set to logic high, the internal
reference is selected and is enabled. If this pin is set to logic low, the internal reference is disabled and
an external reference voltage must be applied to the REFIN/REFOUT pin.

Reference Buffer Output Force/Sense Pins. These pins must be connected together and decoupled to
AGND using a low ESR 10 μF ceramic capacitor.

Rev. A | Page 12 of 36

Data Sheet AD7609

9, 10

DI

7

DI

STBY

Standby Mode Input. This pin is used to place the AD7609 into one of two power-down modes:

Pin No. Type1 Mnemonic Description

8 DI RANGE

6 DI

PAR/
SER SEL

CONVST A,
CONVST B

13 DI

12 DI

CS Chip Select. This active low logic input frames the data transfer. When both CS and RD are logic low in

RD/SCLK Parallel Data Read Control Input When Parallel Interface is Selected (RD)/Serial Clock Input When

14 DO BUSY

11 DI RESET

15 DO FRSTDATA

Analog Input Range Selection. Logic input. The polarity on this pin determines the input range of the
analog input channels. If this pin is tied to a logic high, the analog input range is ±10 V for all
channels. If this pin is tied to a logic low, the analog input range is ±5 V for all channels. A logic
change on this pin has an immediate effect on the analog input range. Changing this pin during a
conversion is not recommended. See the Analog Input section for more details.

Parallel/Serial Interface Selection Input. Logic input. If this pin is tied to a logic low, the parallel
interface is selected. If this pin is tied to a logic high, the serial interface is selected.
In serial mode, the

RD/SCLK pin functions as the serial clock input. The DB7/D

A and DB8/D

OUT

OUT

B pins

function as serial data outputs.
When the serial interface is selected, the DB[15:9] and DB[6:0] pins should be tied to AGND.

Conversion Start Input A, Conversion Start Input B. Logic inputs. These logic inputs are used to initiate
conversions on the analog input channels. For simultaneous sampling of all input channels, CONVST A
and CONVST B can be shorted together and a single conversion start signal applied. Alternatively,
CONVST A can be used to initiate simultaneous sampling for V1, V2, V3, and V4, and CONVST B can be
used to initiate simultaneous sampling on the other analog inputs ( V5, V6, V7, and V8). This is only
possible when oversampling is not switched on. When the CONVST A or CONVST B pin transitions
from low to high, the front-end track-and-hold circuitry for their respective analog inputs is set to
hold. This function allows a phase delay to be created inherently between the sets of analog inputs.

parallel mode, the output bus (DB[15:0]) is enabled and the conversion result is output on the parallel
data bus lines. In serial mode, the CS is used to frame the serial read transfer and clocks out the MSB
of the serial output data.

Serial Interface is Selected (SCLK). When both
bus is enabled. In parallel mode, two

RD pulses are required to read the full 18 bits of conversion

CS and RD are logic low in parallel mode, the output

results from each channel. The first RD pulse outputs DB[17:2], and the second RD pulses outputs
DB[1:0]. In serial mode, this pin acts as the serial clock input for data transfers. The
takes the data output lines, D

A and D

OUT

B, out of three-state and clocks out the MSB of the

OUT

CS falling edge

conversion result. The rising edge of SCLK clocks all subsequent data bits onto the serial data
outputs, D

A and D

OUT

B. For further information, see the Conversion Control section.

OUT

Busy Output. This pin transitions to a logic high after both CONVST A and CONVST B rising edges and
indicates that the conversion process has started. The BUSY output remains high until the conversion
process for all channels is complete. The falling edge of BUSY signals that the conversion data is being
latched into the output data registers and will be available to be read after a time, t

. Any data read

4

while BUSY is high should be complete before the falling edge of BUSY occurs. Rising edges on
CONVST A or CONVST B have no effect while the BUSY signal is high.

Reset Input. When set to logic high, the rising edge of RESET resets the AD7609. The part must receive
a RESET pulse after power-up. To achieve the specified performance after the RESET signal, the t

time should elapse between power-on and the RESET pulse. The RESET high pulse should be

SHUTDOWN

WAKE_UP

typically 100 ns wide. If a RESET pulse is applied during a conversion, the conversion is aborted. If a
RESET pulse is applied during a read, the contents of the output registers reset to all zeros.

Digital Output. The FRSTDATA output signal indicates when the first channel, V1, is being read back
on either the parallel or serial interface. When the CS input is high, the FRSTDATA output pin is in

three-state. The falling edge of

CS takes FRSTDATA out of three-state. In parallel mode, the falling
edge of RD corresponding to the result of V1 then sets the FRSTDATA pin high, indicating that the
result from V1 is available on the output data bus. The FRSTDATA output returns to a logic low
following the third falling edge of

RD. In serial mode, FRSTDATA goes high on the falling edge of CS
as this clocks out the MSB of V1 on DOUTA. It returns low on the 18th SCLK falling edge after the CS
falling edge. See the Conversion Control section for more details.

standby mode or shutdown mode. The power-down mode entered depends on the state of the
RANGE pin, as shown in

Tab le 8. When in standby mode, all circuitry except the on-chip reference,
regulators, and regulator buffers is powered down. When in shutdown mode, all circuitry is
powered down.

Rev. A | Page 13 of 36

AD7609 Data Sheet

Pin No. Type1 Mnemonic Description

5, 4, 3 DI OS [2:0]

33 DO/DI DB15

32 DO/DI DB14

31 to 27 DO DB[13:9]

24 DO DB7/D

25 DO DB8/D

22 to 16 DO DB[6:0]

1

Refers to classification of pin type; P denotes power, AI denotes analog input, REF denotes reference, DI denotes digital input, DO denotes digital output.

Oversampling Mode Pins. Logic inputs. These inputs are used to select the oversampling ratio. OS 2 is
the MSB control bit, and OS 0 is the LSB control bit. See the Digital Filter section for additional details
on the oversampling mode of operation and Table 9 for oversampling bit decoding.

Parallel Output Data Bits, Data Bit 15. When
output pin. This pin is used to output DB17 of the conversion result during the first

PAR/SER SEL = 0, this pin acts as three-state parallel digital

RD pulse and DB1
of the same conversion result during the second RD pulse. When PA R/SER SEL = 1, this pin should be
tied to AGND.

Parallel Output Data Bits, Data Bit 14. When
output pin. When

CS and RD are low, this pin is used to output DB16 of the conversion result during

PAR/SER SEL = 0, this pin acts as three-state parallel digital

the first RD pulse and DB0 of the same conversion result during the second RD pulse. When PAR/SER
SEL = 1, this pin should be tied to AGND.

Parallel Output Data Bits, Data Bit 13 to Data Bit 9. When
parallel digital input/output pins. When

CS and RD are low, these pins are used to output DB15 to

PAR/SER SEL = 0, these pins act as three-state

DB11 of the conversion result during the first RD pulse and output 0 during the second RD pulse.
When PAR/SER SEL = 1, these pins should be tied to AGND.

A

Parallel Output Data Bit 7 (DB7)/Serial Interface Data Output Pin (D

OUT

pins acts as a three-state parallel digital input/output pin. When
output DB9 of the conversion result. When PAR/SER SEL = 1, this pin functions as D
serial conversion data. See the

B

Parallel Output Data Bit 8 (DB8)/Serial Interface Data Output Pin (D

OUT

Conversion Control section for further details.

pins acts as a three-state parallel digital input/output pin. When

A). When PAR/SER SEL = 0, this

OUT

CS and RD are low, this pin is used to

OUT

B). When PAR/SER SEL = 0, this

OUT

CS and RD are low, this pin is used to
output DB10 of the conversion result. When PAR/SER SEL = 1, this pin functions as D
serial conversion data. See the

Parallel Output Data Bits, Data Bit 6 to Data Bit 0. When
parallel digital input/output pins. When
of the conversion result during the first

Conversion Control section for further details.

PAR/SER SEL = 0, these pins act as three-state

CS and RD are low, these pins are used to output DB8 to DB2

RD pulse and output 0 during the second RD pulse. When

PAR/SER SEL = 1, these pins should be tied to AGND.

A and outputs

B and outputs

OUT

Rev. A | Page 14 of 36

Data Sheet AD7609

–160

–140

–120

–100

–80

–60

–40

–20

0

0 20k 40k 60k 80k 100k

SNR (dB)

INPUT FRE QUENCY (Hz)

AV

CC

, V

DRIVE

= 5V
INTERNAL REFERENCE
±10V RANGE

f

SAMPLE

= 200 kSPS

f

IN

= 1kHz
16384 POINT FFT
SNR = 91.52dB
THD = –111.05dB

09760-008

–160

–140

–120

–100

–80

–60

–40

–20

0

0 20k 40k 60k 80k 100k

AMPLIT UDE ( dB)

INPUT FRE QUENCY (Hz)

AV

CC

, V

DRIVE

= 5V
INTERNAL REFERENCE
±5V RANGE

f

SAMPLE

= 200k

SPS

f

IN

= 1kHz
16,384 POINT FFT
SNR = 91.12dB
THD = –109.77dB

09760-009

–160

–140

–120

–100

–80

–60

–40

–20

0

0 1 2 3 4 5 6

AMPLIT UDE ( dB)

INPUT FRE QUENCY (kHz)

09760-109

AV

CC

, V

DRIVE

= 5V
INTERNAL REFERENCE
±10V RANGE

f

SAMPLE

= 12.5kSPS

f

IN

= 1Hz
8192 POINT FFT
SNR = 100.71dB
THD: –111.74dB

–3

–2

–1

0

1

2

3

0

32,768

INL (LSB)

CODE

65,536

98,304

131,072

163,840

196,608

229,376

±10V RANGE
AV

CC

, V

DRIVE

= 5V

T

A

= 25°C

f

SAMPLE

= 200 kSPS
WCP INL = 1.69 LSB
WCN INL = –1.3 LS B

09760-010

0

32,768

CODE

65,536

98,304

131,072

163,840

196,608

229,376

09760-011

–1.0

0

1.0

0.8

0.6

0.4

0.2

–0.2

–0.4

–0.6

–0.8

DNL (LSB)

±10V RANGE
AV

CC

, V

DRIVE

= 5V

T

A

=

25°C

f

SAMPLE

= 200 kSPS
WCP DNL = 0.33 LSB
WCN DNL = –0.32 LS B

–3

–2

–1

0

1

2

3

0

32,768

INL (LSB)

CODE

65,536

98,304

131,072

163,840

196,608

229,376

±5V RANGE
AV

CC

, V

DRIVE

= 5V

T

A

= 25°C

f

SAMPLE

=

200 kSPS
WCP INL = 1.56 LSB
WCN INL = –1.22 LS B

09760-012

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 8. FFT Plot, ±10 V Range

Figure 9. FFT Plot, ±5 V Range

Figure 11. Typical INL, ±10 V Range

Figure 12. Typical DNL, ±10 V Range

Figure 10. FFT Plot, ±10 V Range

Figure 13. Typical INL, ±5 V Range

Rev. A | Page 15 of 36

AD7609 Data Sheet

1.0

0.8

0.6

0.4

0.2

0

DNL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

0

32,768

65,536

98,304

CODE

Figure 14. Typical DNL, ±5 V Range

±5V RANGE
AV

CC

= 25°C

T

A

f

SAMPLE

WCP INL = 0. 45 LSB
WCN INL = –0.38 LSB

131,072

163,840

, V

DRIVE

= 200 kSPS

196,608

= 5V

40

32

PFS ERROR

24

16

NFS ERROR

8

0

–8

–16

–24

NFS/PFS CHANNEL MATCHING ( LSB)

–32

–40

229,376

09760-013

–40 –25 –10 5 20 35 50 65 80

TEMPERATURE ( °C)

±10V RANGE
AV

, V

= 5V

CC

DRIVE

EXTERNAL REFERENCE

09760-218

Figure 17. NFS and PFS Error Matching

80

60

40

20

0

–20

NFS ERROR (LSB)

–40

–60

–80

–40 –25 –10 5 20 35 50 65 80

TEMPERAT URE (°C)

±10V RANGE

200kSPS

, V

AV

CC

DRIVE

EXTERNAL REFERENCE

Figure 15. NFS Error vs. Temperature

80

60

40

20

0

–20

PFS ERROR (LSB)

–40

–60

–80

–40 –25 –10 5 20 35 50 65 80

TEMPERAT URE (°C)

±10V RANGE

200kSPS

, V

AV

CC

DRIVE

EXTERNAL REFERENCE

Figure 16. PFS Error vs. Temperature

±5V RANGE

= 5V

±5V RANGE

= 5V

10

8

6

4

2

PFS/NFS ERROR (%FS )

0

–2

0120k100k80k60k40k20k

09760-117

AVCC, V

f

SAMPLE

= 25°C

T

A

EXTERNAL REF ERENCE
SOURCE RESISTANCE IS MATCHED ON
THE V– INPUT
±10V AND ±5V RANGE

SOURCE RESISTANCE (Ω)

= 5V

DRIVE

= 200 kSPS

09760-219

Figure 18. PFS and NFS Error vs. Source Resistance

105

f

SAMPLE

100

95

SNR (dBs)

90

85

80

09760-118

NO OS
OS × 2
OS × 4
OS × 8
OS × 16
OS × 32
OS × 64

10 100 10k 10k 100k

INPUT FREQUENCY (Hz)

AVCC,V

CHANGES WITH OS RATE

INTERNAL REFERENCE

= 5V

DRIVE

T

= 25°C

A

±10V RANGE

09760-017

Figure 19. SNR vs. Input Frequency, ±10 V Range

Rev. A | Page 16 of 36

Data Sheet AD7609

80

85

90

95

100

105

10 100 10k 10k 100k

SNR (dBs)

INPUT FRE QUENCY (Hz)

NO OS
OS × 2
OS × 4
OS × 8
OS × 16
OS × 32
OS × 64

AV

CC

, V

DRIVE

= 5V

f

SAMPLE

CHANGES WI TH OS RATE

T

A

= 25°C

INTERNAL RE FERENCE

±5V RANGE

09760-018

–120

–110

–100

–90

–80

–70

–60

1 10 100

THD (dB)

FREQUENCY (kHz)

±10V RANGE
AV

CC

, V

DRIVE

= 5V

T

A

= 25°C

f

SAMPLE

= 200 kSPS

R

SOURCE

MATCHED

ON V

x

+, V

x

– INPUTS

10kΩ

5kΩ

10Ω

0Ω

1.2kΩ

500Ω

09760-020

–120

–110

–100

–90

–80

–70

–60

–50

–40

1 10 100

THD (dB)

FREQUENCY (kHz)

09760-019

±5V RANGE

AV

CC

, V

DRIVE

= 5V

T

A

= 25°C

f

SAMPLE

= 200 kSPS

R

SOURCE

MATCHED

ON V

x

+, V

x

– INPUTS

10kΩ

5kΩ

10Ω

0Ω

1.2kΩ

500Ω

200 kSPS
AV

CC

,V

DRIVE

= 5V

EXTERNAL REFERENCE

09760-023

±5V RANGE

±10V RANGE

–6

–4

–2

0

2

4

6

8

–40 –20

0

20 40 60 80

BIPOLAR ZERO ERROR (LSB)

TEMPERATURE (°C)

16

12

8

4

0

–4

–8

–12

–40 –25 –10 5 20 35 50 65 80

–16

BIPOLAR ZERO CODE ERROR MATCHING ( LSB)

TEMPERATURE (°C)

200kSPS
AV

CC

, V

DRIVE

= 5V

EXTERNAL RE FERENCE

±5V RANGE

±10V RANGE

09760-224

–50

–60

–70

–80

–90

–100

–110

–120

–130

0 1601401201008060

4020

–140

CHANNEL-TO-CHANNEL ISOLATION (dB)

NOISE F RE QUENCY (kHz)

AV

CC

, V

DRIVE

= 5V
INTERNAL REF E RE NCE
AD7609 RECOMMENDED DE COUPLING US E D

f

SAMPLE

= 200kSPS

T

A

= 25°C

09760-225

±5V RANGE

±10V RANGE

Figure 20. SNR vs. Input Frequency, ±5 V Range

Figure 21. THD vs. Input Frequency for Various Source Impedances,

±10 V Range

Figure 23. Bipolar Zero Code Error vs. Temperature

Figure 24. Bipolar Zero Code Error Matching Between Channels

Figure 22. THD vs. Input Frequency for Various Source Impedances,

±5 V Range

Figure 25. Channel-to-Channel Isolation

Rev. A | Page 17 of 36

AD7609 Data Sheet

09760-023

80

85

90

95

100

105

110

NO OS OS × 2 OS × 4 OS × 8 OS × 16 OS × 32 OS × 64

DYNAMIC RANGE ( dB)

OVERSAMPLING RATIO

AV

CC

= V

DRIVE

= 5V

T

A

= 25°C

INTERNAL REF E RE NCE

f

SAMPLE

SCALES WITH OS RATIO

±10V RANGE

±5V RANGE

2.5010

2.5005

2.5000

2.4995

2.4990

2.4985

–40 –25 –10 5 20 35 50 65 80

2.4980

REFOUT VOLTAGE (V)

TEMPERATURE (°C)

AV

CC

= 4.75V

AV

CC

= 5V

AVCC = 5.25V

09760-029

–15

–10

–5

0

5

10

–20 –15 –10 –5 0 5 10 15 20

CURRENT (µA)

DIFFERENTIALANALOG INPUT V OLTAGE (Vx+ – (Vx–)) (V)

+25°C V+
+25°C V–
+85°C V–
+85°C V+
–40°C V–
–40°C V+

AV

CC

, V

DRIVE

= 5V

f

SAMPLE

= 200kSPS

09760-025

22

20

18

16

14

12

10

8

AV

CC

SUPPLY CURRENT (mA)

OVERSAMPLING RATIO

AV

CC

, V

DRIVE

= 5V

T

A

= 25°C

INTERNAL RE FERENCE

f

SAMPLE

VARIES WITH OS RATE

NO OS OS × 2 O S × 4 OS × 8 OS × 16 OS × 32 OS × 64

09760-227

140

0 11001000900800700600500400300200100

60

70

80

90

100

110

120

130

POWER SUP P LY REJECTION RATIO ( dB)

AVCC NOISE F RE QUENCY (kHz)

AVCC, V

DRIVE

= 5V
INTERNAL RE FERENCE
AD7609 RECOMMENDED DE COUPLING US E D

f

SAMPLE

= 200kSPS

T

A

= 25°C

±10V RANGE

±5V RANGE

09760-130

–100

–90

–80

–70

–60

–50

–40

–30

–20

0

–10

10 100 1k 10k 100k

CMRR (dB)

FREQUENCY (Hz)

±10V RANGE

±5V RANGE

AVCC, V

DRIVE

= 5V

T

A

= 25°C

f

SAMPLE

= 200kSPS

INTERNAL RE FERENCE

09760-028

Figure 26. Dynamic Range vs. Oversampling Ratio

Figure 27. Reference Output Voltage vs. Temperature for Different Supply

Voltages

Figure 29. Supply Current vs. Oversampling Rate

Figure 30. PSRR

Figure 28. Analog Input Current vs. Input Voltage Over Temperature

Figure 31. CMRR vs. Common-Mode Ripple Frequency

Rev. A | Page 18 of 36

Data Sheet AD7609

1

98765432

V

VVVVVVVV

22222222

+++++++

TERMINOLOGY

Integral Nonlinearity

The maximum deviation from a straight line passing through
the endpoints of the ADC transfer function. The endpoints of
the transfer function are zero scale, a ½ LSB below the first code
transition, and full scale at ½ LSB above the last code transition.

Differential Nonlinearity

The difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.

Bipolar Zero Code Error

The deviation of the midscale transition (all 1s to all 0s) from
the ideal V

voltage, that is, AGND.

IN

Bipolar Zero Code Error Match

The difference in bipolar zero code error between any two input
channels.

Positive Full-Scale Error

The last transition (from 011 . . . 10 to 011 . . . 11 in twos
complement coding) should occur for an analog voltage 1½
LSB below the nominal full scale (9.99977 V for the ±10 V
range and 4.99988 V for the ±5 V range). The positive full-scale
error is the deviation of the actual level of the last transition
from the ideal level.

Positive Full-Scale Error Match

The difference in positive full-scale error between any two input
channels.

Negative Full-Scale Error

The first transition (from 100 . . . 00 to 100 . . . 01 in twos
complement coding) should occur for an analog voltage ½ LSB
above the negative full scale (−9.999923 V for the ±10 V range
and −4.9999618 for the ±5 V range). The negative full-scale
error is the deviation of the actual level of the first transition
from the ideal level.

Negative Full-Scale Error Match

The difference in negative full-scale error between any two
input channels.

Track-and-Hold Acquisition Time

The track-and-hold amplifier returns to track mode at the end
of the conversion. The track-and-hold acquisition time is the
time required for the output of the track-and-hold amplifier to
reach its final value, within ±1 LSB, after the end of the conversion.
See the Tra c k -and-Hold Amplifiers section for more details.

Signal-to-(Noise + Distortion) Ratio

The measured ratio of signal-to-(noise + distortion) at the
output of the ADC. The signal is the rms amplitude of the
fundamental. Noise is the sum of all nonfundamental signals
up to half the sampling frequency (f

/2, excluding dc). The ratio

S

depends on the number of quantization levels in the digitization
process: the more levels, the smaller the quantization noise. The
theoretical signal-to-(noise + distortion) ratio for an ideal N-bit
converter with a sine wave input is given by

Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB

Thus, for an 18-bit converter, this is 110.12 dB.

Total Harmonic Distortion (THD)

The ratio of the rms sum of the harmonics to the fundamental.
For the AD7609, it is defined as

THD (dB) =

20log

where:

V

is the rms amplitude of the fundamental.

1

to V9 are the rms amplitudes of the second through ninth

V

2

harmonics.

Peak Harmonic or Spurious Noise

The ratio of the rms value of the next largest component in the
ADC output spectrum (up to f

/2, excluding dc) to the rms value

S

of the fundamental. Normally, the value of this specification is
determined by the largest harmonic in the spectrum, but for
ADCs where the harmonics are buried in the noise floor, it is
determined by a noise peak.

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa and fb,
any active device with nonlinearities creates distortion products
at sum and difference frequencies of mfa ± nfb, where m, n = 0,
1, 2, 3. Intermodulation distortion terms are those for which
neither m nor n is equal to 0. For example, the second-order
terms include (fa + fb) and (fa − fb), and the third-order terms
include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb).

The calculation of the intermodulation distortion is per the
THD specification, where it is the ratio of the rms sum of the
individual distortion products to the rms amplitude of the
sum of the fundamentals expressed in decibels (dB).

Rev. A | Page 19 of 36

AD7609 Data Sheet

Power Supply Rejection (PSR)

Variations in power supply affect the full-scale transition but
not the converter’s linearity. Power supply rejection is the
maximum change in full-scale transition point due to a change
in power supply voltage from the nominal value. The power
supply rejection ratio is defined as the ratio of the power in
the ADC output at full-scale frequency, f, to the power of a
200 mV p-p sine wave applied to the ADC V
of Frequency f

PSRR (dB) = 10 log (Pf/Pf

.

S

)

S

and VSS supplies

DD

where:
Pf is equal to the power at Frequency f in the ADC output.

is equal to the power at Frequency fS coupled onto the VDD

Pf

S

and V

supplies.

SS

Channel-to-Channel Isolation

Channel-to-channel isolation is a measure of the level of crosstalk
between any two channels. It is measured by applying a full-scale,
10 kHz sine wave signal to all unselected input channels and
determining the degree to which the signal attenuates in the
selected channel with a 1 kHz signal.

Common-Mode Rejection Ratio (CMRR)

CMRR is defined as the ratio of the power in the ADC
common-mode input at full-scale frequency, f, to the power in
the output of a full-scale p-p sine wave applied to the common­mode voltage of V

CMRR (dB) = 20 log (Pf/Pf

X+ and VINX− of frequency, fS,

IN

)

S

where:
Pf is equal to the power at Frequency f in the ADC input.

is equal to the power at Frequency fS in the ADC output.

Pf

S

Rev. A | Page 20 of 36

Data Sheet AD7609

1MΩ

CLAMPVx+

1MΩ

CLAMPVx–

SECOND-

ORDER

LPF

R

FB

R

FB

09760-129

09760-033

30

–50

–40

–30

–20

–10

0

10

20

–20 –15 –10 –5 0 5 10 15 20

INPUT CLAM P CURRE NT (mA)

SOURCE VOLTAGE (V)

AV

CC

, V

DRIVE

= 5V

T

A

= 25°C

1MΩ

CLAMP

VINx+

1MΩ

CLAMP

VINx–

R

FB

R

FB

C

R

R

+10V
–10V

AD7609

09760-031

+10V
–10V

THEORY OF OPERATION

CONVERTER DETAILS

The AD7609 is a data acquisition system that employs a high
speed, low power, charge redistribution successive approxima­tion analog-to-digital converter (ADC) and allows the
simultaneous sampling of eight true differential analog input
channels. The analog inputs on the AD7609 can accept true
bipolar input signals. The RANGE pin is used to select either
±10 V or ±5 V as the input range. The AD7609 operates from
a single 5 V supply.

The AD7609 contains input clamp protection, input signal
scaling amplifiers, a second-order antialiasing filter, track-and­hold amplifiers, an on-chip reference, reference buffers, a high
speed ADC, a digital filter, and high speed parallel and serial
interfaces. Sampling on the AD7609 is controlled using
CONVST x signals.

ANALOG INPUT

Analog Input Ranges

The AD7609 can handle true bipolar input voltages. The logic
level on the RANGE pin determines the analog input range of
all analog input channels. If this pin is tied to a logic high, the
analog input range is ±10 V for all channels. If this pin is tied
to a logic low, the analog input range is ±5 V for all channels.
A logic change on this pin has an immediate effect on the
analog input range; however, there is a settling time of 80 µs
typically, in addition to the normal acquisition time requirement.
The recommended practice is to hardwire the RANGE pin
according to the desired input range for the system signals.

During normal operation, the applied analog input voltage should
remain within the analog input range selected via the RANGE
pin. A RESET pulse must be applied to the part to ensure the
analog input channels are configured for the range selected.

When in a power-down mode, it is recommended to tie the
analog inputs together or both analog input pins (Vx+, Vx−) to
GND. As per the Analog Input Clamp Protection section, the
overvoltage clamp protection is recommended for use in
transient overvoltage conditions, and should not remain active
for extended periods. Stressing the analog inputs outside of
these conditions may degrade the Bipolar Zero Code error and
THD performance of the AD7609.

Analog Input Impedance

The analog input impedance of the AD7609 is 1 MΩ. This is a
fixed input impedance and does not vary with the AD7609 sam­pling frequency. This high analog input impedance eliminates
the need for a driver amplifier in front of the AD7609 allowing
for direct connection to the source or sensor. With the need for
a driver amplifier eliminated, bipolar supplies can be removed
from the signal chain, which are often a source of noise in a system.

Analog Input Clamp Protection

Figure 32 shows the analog input structure of the AD7609.
Each AD7609 analog input contains clamp protection circuitry.
Despite a single 5 V supply operation, this analog input clamp
protection allows for an input overvoltage up to ±16.5 V.

Figure 32. Analog Input Circuitry

Figure 33 shows the current vs. voltage characteristic of the
clamp circuit. For input voltages up to ±16.5 V, no current flows
in the clamp circuit. For input voltages above ±16.5 V, the

AD7609 clamp circuitry turns on and clamps the analog input

to ±16.5 V. A series resister should be placed on the analog
input channels to limit the current to ±10 mA for input voltages
above ±16.5 V. In an application where there is a series resistance
on an analog input channel, VINx+, a corresponding resistance
is required on the VINx− channel (see Figure 34). If there is no
corresponding resister on the Vx− channel, this results in an
offset error on that channel. It is recommended that the input
overvoltage clamp protection circuitry be used to protect the

AD7609 against transient overvoltage events. It is not recom-

mended to leave the AD7609 in a condition where the clamp
protection circuitry is active (in normal or power-down
conditions) for extended periods because this may degrade the
bipolar zero code error performance of the AD7609.

Figure 33. Input Protection Clamp Profile

Rev. A | Page 21 of 36

Figure 34. Input Resistance Matching on the Analog Input

AD7609 Data Sheet

–40

–35

–30

–25

–20

–15

–10

–5

0

100 1k 10k 100k

ATTENUATION (dB)

FREQUENCY (Hz)

10V DIFF

5V DIFF

09760-032

10V

0.1dBTEMP 3dB

–40°C 13,354Hz 33,520Hz

25°C 12,769Hz 32,397Hz
85°C 12,427Hz 31,177Hz

5V

–40°C 10,303Hz 24,365Hz

25°C 9619Hz 23,389Hz
85°C 9326Hz 22,607Hz

09760-133

10 100k10k1k

PHASE DELAY (µs)

INPUT FRE QUENCY (Hz)

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

±5V RANGE

±10V RANGE

AVCC, V

DRIVE

= 5V

f

SAMPLE

= 200kSPS

T

A

= 25°C

ADC CODE

V+ ± (V–)

REF

Midscale – 1 LSB

−152.58 µV

−76 µV

0x3FFFF

Analog Input Antialiasing Filter

An analog antialiasing filter is also provided on the AD7609.
The filter is a second-order Butterworth. Figure 35 and
Figure 36 show the frequency and phase response respectively
of the analog antialiasing filter. In the ±5 V range, the −3 dB
frequency is typically 23 kHz. In the ±10 V range, the −3 dB
frequency is typically 32 kHz.

Figure 35. Analog Antialiasing Filter Frequency Response

The conversion clock for the part is internally generated, and
the conversion time for all channels is 4 µs on the AD7609. The
BUSY signal returns low after all eight conversions to indicate the
end of the conversion process. On the falling edge of BUSY, the
track-and-hold amplifiers return to track mode. New data can
be read from the output register via the parallel, or serial
interface after BUSY goes low; or, alternatively, data from the
previous conversion can be read while BUSY is high. Reading data
from the AD7609 while a conversion is in progress has little
effect on performance and allows a faster throughput to be
achieved. With a V

> 3.3 V, the SNR is reduced by ~1.5 dB

DRIVE

when reading during a conversion.

ADC TRANSFER FUNCTION

The output coding of the AD7609 is twos complement. The
designed code transitions occur midway between successive
integer LSB values, that is, 1/2 LSB, 3/2 LSB. The LSB size is
FSR/262,144 for the AD7609. The FSR for the AD7609 is 40 V
for the ±10 V range and 20 V for the ±5 V range. The ideal
transfer characteristic for the AD7609 is shown in Figure 37.

±10V CODE = × 131,072 ×

±5V CODE = × 131,072 ×

10V

V+ ± (V–)

5V

2.5V
REF

2.5V

Figure 36. Analog Antialiasing Filter Phase Response

Track-and-Hold Amplifiers

The track-and-hold amplifiers on the AD7609 allow the ADC to
accurately acquire an input sine wave of full-scale amplitude
to 18-bit resolution. The track-and-hold amplifiers sample
their respective inputs simultaneously on the rising edge of
CONVST x. The aperture time for track-and-hold (that is, the
delay time between the external CONVST x signal and the
track-and-hold actually going into hold) is well matched, by design,
across all eight track-and-holds on one device and from device
to device. This matching allows more than one AD7609 device
to be sampled simultaneously in a system.

The end of the conversion process across all eight channels is
indicated by the falling edge of BUSY; and it is at this point that the
track-and-holds return to track mode and the acquisition time
for the next set of conversions begins.

011...111

011...110

000...001

000...000

111...111

100...010

100...001

100...000

–FS + 1/2LSB 0V – 1LSB +FS – 3/2LSB

ANALOG I NP UT

LSB =

+FSR – (–FSR)

18

2

09760-034

Figure 37. AD7609 Transfer Characteristic

The LSB size is dependent on the analog input range selected
(see Tab l e 7).

Table 7. Output Codes and Ideal Input Values

Analog
Analog Input
(V+ − (V−)

Description

10 V Range

FSR − 0.5 LSB +19.99992 V 9.999961 V 0x1FFFF
Midscale + 1 LSB +152.58 µV 76 µV 0x00001
Midscale 0 V 0 V 0x00000

−FSR + 1 LSB −19.99984 V −9.99992 V 0x20001

−FSR −20 V −10 V 0x20000

Input

V+ − (V−)

5 V Range

Digital
Output
Code (Hex)

Rev. A | Page 22 of 36

Data Sheet AD7609

BUF

SAR

2.5V
REF

REFCAPB

REFIN/REFOUT

REFCAPA

10µF

09760-035

AD7609

REF SELECT

REFIN/REFOUT

+

10µF

AD7609

REF SELECT

REFIN/REFOUT

100nF

AD7609

REF SELECT

REFIN/REFOUT

100nF

V

DRIVE

09760-036

AD7609

REF SELECT

REFIN/REFOUT

AD7609

REF SELECT

REFIN/REFOUT

100nF

0.1µF

100nF

AD7609

REF SELECT

REFIN/REFOUT

100nF

ADR421

09760-037

INTERNAL/EXTERNAL REFERENCE

The AD7609 contains an on-chip 2.5 V band gap reference. The
REFIN/REFOUT pin allows access to the 2.5 V reference that
generates the on-chip 4.5 V reference internally, or it allows an
external reference of 2.5 V to be applied to the AD7609. An
externally applied reference of 2.5 V is also amplified to 4.5 V using
the internal buffer. This 4.5 V buffered reference is the reference
used by the SAR ADC.

The REF SELECT pin is a logic input pin that allows the user to
select between the internal reference and the external reference.
If this pin is set to logic high, the internal reference is selected
and is enabled; if this pin is set to logic low, the internal refer­ence is disabled and an external reference voltage must be
applied to the REFIN/REFOUT pin. The internal reference
buffer is always enabled. After a reset, the AD7609 operates in
the reference mode selected by the REF SELECT pin. Decoupling
is required on the REFIN/REFOUT pin for both the internal
or external reference options. A 10 µF ceramic capacitor is
required on the REFIN/REFOUT to ground close to the
REFGND pins. The AD7609 contains a reference buffer
configured to amplify the REF voltage up to ~4.5 V, as shown
in Figure 38. The REFCAPA and REFCAPB pins must be
shorted together externally and a ceramic capacitor of 10 μF
applied to REFGND to ensure the reference buffer is in
closed-loop operation. The reference voltage available at the
REFIN/REFOUT pin is 2.5 V.

When the AD7609 is configured in external reference mode,
the REFIN/REFOUT pin is a high input impedance pin. For
applications using multiple AD7609 devices, the following
configurations are recommended depending on the application
requirements.

External Reference Mode

One ADR421 external reference can be used to drive the
REFIN/REFOUT pins of all AD7609 devices (see Figure 39). In
this configuration, each AD7609 REFIN/REFOUT pin should
be decoupled with a 100 nF decoupling capacitor.

Internal Reference Mode

One AD7609 device, configured to operate in the internal
reference mode, can be used to drive the remaining AD7609
devices, which are configured to operate in external reference
mode (see Figure 40). The REFIN/REFOUT pin of the AD7609,
configured in internal reference mode, should be decoupled
using a 10 µF ceramic decoupling capacitor. The other AD7609
devices, configured in external reference mode, should use a
100 nF decoupling capacitor on their REFIN/REFOUT pins.

Figure 38. Reference Circuitry

Figure 39. Single External Reference Driving Multiple AD7609

REFIN/REFOUT Pins

Figure 40. Internal Reference Driving Multiple AD7609 REFIN Pins

Rev. A | Page 23 of 36

AD7609 Data Sheet

AV

CC

AGND

V

DRIVE

+

REFIN/REFOUT

DB0 TO DB15

CONVST A, B

CS
RD

BUSY

RESET

AD7609

1µF

10µF

100nF

DIGITAL SUPPLY
VOLTAGE +2.3V TO +5V

ANALOG SUP P LY

VOLTAGE 5V

1

EIGHT DIFFERENTIAL

ANALOG I NP UT PAIRS

PARALLEL

INTERFACE

1

DECOUPLI NG SHOWN ON THE AVCC PIN APPLIES TO EACH AVCC PIN (PIN 1, PIN 37, PI N 38, PIN 48).
DECOUPLI NG CAPACITOR CAN BE S HARE D BE TWEEN AV

CC

PIN 37 AND PIN 38.

2

DECOUPLI NG SHOWN ON THE REGCAP PIN APPLIE S TO EACH REGCAP P IN (PIN 36, PIN 39).

REGCAP

2

+

10µF

REFCAPA

REFCAPB

OS 2
OS 1
OS 0

OVERSAMPLING

100nF

V1+

PAR/SER SEL

STBY

REF SELECT

RANGE

V2+
V3+
V4+
V5+
V6+
V7+
V8+

REFGND

V1–
V2–
V3–

V4–
V5–

V6–
V7–
V8–

V

DRIVE

V

DRIVE

MICROPROCESSOR/

MICROCONVERTER/

DSP

09760-038

TYPICAL CONNECTION DIAGRAM

Figure 41 shows the typical connection diagram for the
AD7609. There are four AV
can be tied together and decoupled using a 100 nF capacitor at
each supply pin and a 10 µF capacitor at the supply source. The

AD7609 can operate with the internal reference or an externally

applied reference. In this configuration, the AD7609 is config­ured to operate with the internal reference. When using a single

AD7609 device on the board, the REFIN/REFOUT pin should

be decoupled with a 10 µF capacitor. In an application with
multiple AD7609 devices, see the Internal/External Reference
section. The REFCAPA and REFCAPB pins are shorted together
and decoupled with a 10 µF ceramic capacitor.

The V

supply is connected to the same supply as the pro-

DRIVE

cessor. The voltage on V
output logic signals. For layout, decoupling, and grounding
hints, see the Layout Guidelines section.

After supplies are applied to the AD7609, a reset should be
applied to the AD7609 to ensure that it is configured for the
correct mode of operation.

supply pins on the part that

CC

controls the voltage value of the

DRIVE

POWER-DOWN MODES

There are two power-down modes available on the AD7609.

STBY

The
or one of the two power-down modes. The two power-down
modes available are standby mode and shutdown mode. The
power-down mode is selected through the state of the RANGE
pin when the
required to choose the desired power-down mode. When the

AD7609 is placed in standby mode, the current consumption is

8 mA maximum and power-up time is approximately 100 µs
because the capacitor on the REFCAPA/REFCAPB pins must
charge up. In standby mode, the on-chip reference and
regulators remain powered up and the amplifiers and ADC core
are powered down. When the AD7609 is placed in shutdown
mode, the current consumption is 11 µA maximum and power
up time is about 13 ms. In shutdown mode, all circuitry
is powered down. When the AD7609 is powered up from
shutdown mode, a reset signal must be applied to the AD7609
after the required power-up time has elapsed.

Table 8. Power-Down Mode Selection

Power-Down Mode

Standby 0 1
Shutdown 0 0

pin controls whether the AD7609 is in normal mode

STBY

pin is low. Ta ble 8 shows the configurations

STBY

RANGE

Figure 41. Typical Connection Diagram

Rev. A | Page 24 of 36

Data Sheet AD7609

09760-039

CONVST A

CONVST B

BUSY

CS, RD

DATA: DB[15:0]

FRSTDATA

t

5

t

CONV

V1 TO V4 T RACK- AND- HOLD
ENTER HOL D

V5 TO V8 T RACK- AND- HOLD
ENTER HOL D

AD7609 CONVERTS

ON ALL 8 CHANNELS

V1 V8V2

CONVERSION CONTROL

Simultaneous Sampling on All Analog Input Channels

The AD7609 allows simultaneous sampling of all analog input
channels. All channels are sampled simultaneously when both
CONVST x pins (CONVST A, CONVST B) are tied together. A
single CONVST x signal is used to control both CONVST x inputs.
The rising edge of this common CONVST x signal initiates
simultaneous sampling on all analog input channels.

The AD7609 contains an on-chip oscillator that is used to
perform the conversions. The conversion time for all ADC
channels is t
conversions are in progress, so that when the rising edge of
CONVST x is applied, BUSY goes logic high and transitions low
at the end of the entire conversion process. The falling edge of
the BUSY signal is used to place all eight track-and-hold
amplifiers back into track mode. The falling edge of BUSY also
indicates that the new data can now be read from the parallel
bus (DB[15:0]) or the serial data lines, D

. The BUSY signal indicates to the user when

CONV

A and D

OUT

OUT

B.

Simultaneously Sampling Two Sets of Channels

The AD7609 also allows the analog input channels to be
sampled simultaneously in two sets. This can be used in power
line protection and measurement systems to compensate for
phase differences between PT and CT transformers. In a 50 Hz
system, this allows for up to 9° of phase compensation, and in a
60 Hz system, it allows for up to 10° of phase compensation.

This is accomplished by pulsing the two CONVST x pins inde­pendently and is only possible if oversampling is not in use.
CONVST A is used to initiate simultaneous sampling of the first
set of channels (V1 to V4). CONVST B is used to initiate
simultaneous sampling on the second set of analog input
channels (V5 to V8), as illustrated in Figure 42. On the rising
edge of CONVST A, the track-and-hold amplifiers for the first
set of channels are placed into hold mode. On the rising edge
of CONVST B, the track-and-hold amplifiers for the second set
of channels are placed into hold mode. The conversion process
begins after both rising edges of CONVST x have occurred;
therefore, BUSY goes high on the rising edge of the later
CONVST x signal. The falling edge of BUSY also indicates that
the new data can now be read from the parallel bus or the serial
data lines, D

A and D

OUT

B. There is no change to the data

OUT

read process when using two separate CONVST x signals.

Connect all unused analog input channel to AGND. The results
for any unused channels are still included in the data read
because all channels are always converted.

Figure 42. Simultaneous Sampling on Channel Sets Using Independent CONVST A/CONVST B Signals—Parallel Mode

Rev. A | Page 25 of 36

AD7609 Data Sheet

AD7609

14

BUSY

12

RD

33:16

DB[15:0]

13

CS

DIGITAL

HOST

INTERRUPT

09760-040

DIGITAL INTERFACE

The AD7609 provides two interface options: a parallel interface
and a high speed serial interface. The required interface mode is
selected via the

The operation of the interface modes is described in the
following sections.

PARALLEL INTERFACE (PAR/SER SEL = 0)

Data can be read from the AD7609 via the parallel data bus with
standard
bus, the
input signals are internally gated to enable the conversion result
onto the data bus. The data lines, DB15 to DB0, leave their high
impedance state when both

The rising edge of the
the falling edge of the
high impedance state.
data lines; it is the function that allows multiple AD7609
devices to share the same parallel data bus. The
be permanently tied low, and the
access the conversion results, as shown in

operation of new data can take place after the BUSY signal
goes low (Figure 2), or, alternatively, a read operation of data
from the previous conversion process can take place while
BUSY is high (Figure 3).

RD

The
results register. Two
18-bit conversion result from each channel. Applying a
sequence of 16
conversion results out from each channel onto the parallel
output bus, DB[15:0], in ascending order. The first
edge after BUSY goes low clocks out DB[17:2] of the V1 result,
the next
result. It takes 16
results from the AD7609. The 16
the DB[1:0] conversion result for Channel V8. When the
signal is logic low, it enables the data conversion result from

each channel to be transferred to the digital host (DSP, FPGA).

When there is only one AD7609 in a system/board and it
does not share the parallel bus, data can be read using only one
control signal from the digital host. The
can be tied together, as shown in
bus comes out of three-state on the falling edge of

combined
of the

AD7609 and to be read by the digital host. In this case,

CS

is used to frame the data transfer of each data channel and

CS

16

pulses are required to read the eight channels of data.

PAR

/SER SEL pin.

CS

and RD signals. To read the data over the parallel

PAR

/SER SEL pin should be tied low. The CS and RD

CS

and RD are logic low.

CS

input signal three-states the bus and

CS

input signal takes the bus out of the

CS

is the control signal that enables the

CS

signal can

RD

signal can be used to

Figure 4. A read

pin is used to read data from the output conversion

RD

pulses are required to read the full

RD

pulses to the AD7609 RD pin clocks the

RD

falling

RD

falling edge updates the bus with DB[1:0] of the V1

RD

pulses to read the eight 18-bit conversion

th

falling edge of RD clocks out

RD

CS

and RD signals

Figure 5. In this case, the data

CS/RD

. The

CS

and RD signal allows the data to be clocked out

Figure 43. AD7609 Interface Diagram: One AD7609 Using the Parallel Bus;

RD

Shorted Together

and

CS

SERIAL INTERFACE (PAR/SER SEL = 1)

To read data back from the AD7609 over the serial interface,

PAR

the
signals are used to transfer data from the AD7609. The
has two serial data output pins, D
read back from the AD7609 using one or both of these D
lines. For the AD7609, conversion results from Channel V1 to
Channel V4 first appear on D
from Channel V5 to Channel V8 first appear on D

The
D
sion result. The rising edge of SCLK clocks all subsequent data
bits onto the serial data outputs, D
input can be held low for the entire serial read or it can be
pulsed to frame each channel read of 18 SCLK cycles.

Figure 44 shows a read of eight simultaneous conversion results
using two D
transfer is used to access data from the AD7609 and
low to frame the entire 72 SCLK cycles. Data can also be clocked
out using only one D
mended to access all conversion data, because the channel data
is output in ascending order. For the AD7609 to access all eight
conversion results on one D
are required. These 144 SCLK cycles can be framed by one
signal or each group of 18 SCLK cycles can be individually
framed by the
D
conversion. The unused D
in serial mode. For the AD7609, if D
single D
order: V5, V6, V7, V8, V1, V2, V3, V4; however, the FRSTDATA
indicator returns low after V5 is read on D

/SER SEL pin should be tied high. The CS and SCLK

A and D

OUT

A, whereas conversion results

OUT

CS

falling edge takes the data output lines (D

B) out of three-state and clocks out the MSB of the conver-

OUT

A and D

OUT

lines on the AD7609. In this case, a 72 SCLK

OUT

B. Data can be

OUT

B.

OUT

A and

OUT

B. The CS

OUT

CS

line, in which case D

OUT

line, a total of 144 SCLK cycles

OUT

CS

signal. The disadvantage of using only one

line is that the throughput rate is reduced if reading after

OUT

line should be left unconnected

OUT

B is to be used as a

OUT

line, the channel results are output in the following

OUT

OUT

OUT

B.

A is recom-

AD7609

OUT

is held

CS

Rev. A | Page 26 of 36

Data Sheet AD7609

V1

V4V2 V3

V5

V8V6 V7

SCLK

D

OUT

A

D

OUT

B

CS

72

09760-041

Figure 6 shows the timing diagram for reading one channel of
data, framed by the

CS

signal, from the AD7609 in serial mode.
The SCLK input signal provides the clock source for the serial
read operation.
The falling edge of

CS

goes low to access the data from the AD7609.

CS

takes the bus out of three-state and
clocks out the MSB of the 18-bit conversion result. This MSB
is valid on the first falling edge of the SCLK after the

CS

falling
edge. The subsequent 17 data bits are clocked out of the

AD7609 on the SCLK rising edge. Data is valid on the SCLK

falling edge. Eighteen clock cycles must be provided to the

AD7609 to access each conversion result.

The FRSTDATA output signal indicates when the first channel,
V1, is being read back. When the

CS

input is high, the FRSTDATA
output pin is in three-state. In serial mode, the falling edge of
CS

takes FRSTDATA out of three-state and sets the FRSTDATA
pin high indicating that the result from V1 is available on the
D

A output data line. The FRSTDATA output returns to a

OUT

logic low following the 18

th

SCLK falling edge. If all channels

are read on D
when V1 is being output on this serial data output pin. It only
goes high when V1 is available on D
is available on D

READING DURING CONVERSION

Data can be read from the AD7609 while BUSY is high
and conversions are in progress. This has little effect on the
performance of the converter and allows a faster throughput
rate to be achieved. A parallel or serial read can be performed
during conversions and when oversampling may or may not
be in use. Figure 3 shows the timing diagram for reading while
BUSY is high in parallel or serial mode. Reading during conver­sions allows the full throughput rate to be achieved when using
the serial interface with a V

Data can be read from the AD7609 at any time other than on
the falling edge of BUSY because this is when the output data
registers are updated with the new conversion data. t
in Tab l e 3, should be observed in this condition.

B, the FRSTDATA output does not go high

OUT

A (and this is when V5

OUT

B).

OUT

of 3.3 V to 5.25 V.

DRIVE

, outlined

6

Figure 44. AD7609 Serial Interface with Two D

OUT

Lines

Rev. A | Page 27 of 36

AD7609 Data Sheet

CONVST A,

CONVST B

BUSY

OS x

t

OS_SETUP

t

OS_HOLD

CONVERSION N CONVERSION N + 1

OVERSAMPLE RATE
LATCHED FOR CONVERSION N + 1

09760-042

010 4 95.5

96.4

18.5

21.5

50

DIGITAL FILTER

The AD7609 contains an optional digital filter. This digital filter
is a first-order sinc filter. This digital filter should be used in
applications where slower throughput rates are used or where
higher signal-to-noise ratio or dynamic range is desirable. The
oversampling ratio of the digital filter is controlled using the
oversampling pins, OS [2:0] (see Tabl e 9). OS 2 is the MSB
control bit and OS 0 is the LSB control bit. Tab le 9 provides
the oversampling bit decoding to select the different oversample
rates. The OS pins are latched on the falling edge of BUSY.
This sets the oversampling rate for the next conversion (see
Figure 45). In addition to the oversampling function, the output
result is decimated to 18-bit resolution.

If the OS pins are set to select an OS ratio of 8, the next
CONVST x rising edge takes the first sample for each channel
and the remaining seven samples for all channels are taken with
an internally generated sampling signal. These samples are then
averaged to yield an improvement in SNR performance. Tab le 9
shows typical SNR performance for both the ±10 V and the
±5 V ranges. As Tabl e 9 indicates, there is an improvement in
SNR as the OS ratio increases. As the OS ratio increases, the
3 dB frequency is reduced and the allowed sampling frequency
is also reduced. In an application where the required sampling
frequency is 10 kSPS, an OS ratio of up to 16 can be used. In
this case, the application sees an improvement in SNR but the
input −3 dB bandwidth is limited to ~6 kHz.

The CONVST A and CONVST B pins must be tied/driven
together when oversampling is turned on. When the over­sampling function is turned on, the BUSY high time for the
conversion process extends. The actual BUSY high time
depends on the oversampling rate selected; the higher the
oversampling rate, the longer the BUSY high, or total
conversion time, see Tab le 9.

Figure 46 shows that the conversion time extends as the over­sampling rate is increased, and the BUSY signal lengthens for the
different oversampling rates. For example, a sampling frequency
of 10 kSPS yields a cycle time of 100 µs. Figure 46 shows OS × 2
and OS × 4; for a 10 kSPS example, there is adequate cycle time
to further increase the oversampling rate and yield greater
improvements in SNR performance. In an application where
the initial sampling or throughput rate is at 200 kSPS, for
example, and oversampling is turned on, the throughput rate
must be reduced to accommodate the longer conversion time
and to allow for the read. To achieve the fastest throughput
rate possible when oversampling is turned on, the read can be
performed during the BUSY high time. The falling edge of BUSY
is used to update the output data registers with the new conver­sion data; therefore, the reading of conversion data should not
occur on this edge. Figure 47 to Figure 53 illustrate the effect of
oversampling on the code spread in a dc histogram plot. As the
oversample rate is increased, the spread of codes is reduced. (In
Figure 47 to Figure 53, AV

CC

= V

= 5 V and the sampling

DRIVE

rate was scaled with OS ratio.)

Figure 45. OS Pin Timing

Table 9. Oversampling Bit Decoding (100 Hz Input Signal)

OS
[2:0]

OS
Ratio

SNR ±5 V Range
(dB)

SNR ±10 V Range
(dB)

−3 dB BW 5 V Range
(kHz)

−3 dB BW 10 V
Range (kHz)

Maximum Throughput
CONVST x Frequency (kHz)

000 No OS 90.8 91.5 22 33 200
001 2 93.3 93.9 22 28.9 100

011 8 98 98.9 11.9 12 25
100 16 100.6 101 6 6 12.5
101 32 101.8 102 3 3 6.25
110 64 102.7 102.9 1.5 1.5 3.125
111 Invalid

Rev. A | Page 28 of 36

Data Sheet AD7609

CS

RD

DATA:

DB[15:0]

BUSY

CONVST A,

CONVST B

t

CYCLE

t

CONV

4µs

t

4

t

4

t

4

9µs

19µs

OS = 0 OS = 2 OS = 4

09760-043

0

200

400

600

800

1000

1200

1400

1600

–9 –8 –7 –6 –5 –4 –3 –2 –1 0

CODE

1 2 3 4 5 6 7 8 9

NO OVERSAMPLING

NUMBER OF O CCURRE NCE S

09760-044

2

10

27

83

210

450

727

1062

1384

1373

1167

840

492

219

100

32

11

2

1

0

200

400

600

800

1000

1400

1800

1200

1600

2000

–7 –6 –5 –4 –3 –2 –1 0

CODE

1 2 3 4 5 6 7

OVERSAMPLING BY 2

NUMBER OF O CCURRE NCE S

09760-045

1

12

46

214

599

1146

1785

1772

1389

788

317

105

15

2

1

500

0

1000

1500

2500

2000

3000

–5 –4 –3 –2 –1 0

CODE

1 2 3 4

OVERSAMPLING BY 4

NUMBER OF O CCURRE NCE S

09760-046

5

49

341

1191

2363

2394

1340

422

79

8

0

500

1000

1500

2000

2500

3000

4000

3500

–4 –3 –2 –1 0

CODE

1 2 3

OVERSAMPLING BY 8

NUMBER OF O CCURRE NCE S

09760-047

1

41

549

229

15

1568

3392

2397

Figure 46. AD7609—No Oversampling, Oversampling × 4, and Oversampling × 8 Using Read After Conversion

Figure 47. Histogram of Codes—No OS (19 Codes)

Figure 49. Histogram of Codes—OS × 4 (10 Codes)

Figure 48. Histogram Of Codes—OS × 2 (15 Codes)

Figure 50. Histogram of Codes—OS × 8 (Eight Codes)

Rev. A | Page 29 of 36

AD7609 Data Sheet

OVERSAMPLING BY 16

0

500

1000

1500

2000

3000

4000

2500

3500

4500

–2–3 –1 0

CODE

1 2

385

NUMBER OF O CCURE NCE S

09760-048

3

406

3279

3833

657

14

45

5090

341

OVERSAMPLING BY 32

0

1000

2000

3000

4000

5000

6000

–2 –1

CODE

0 1

NUMBER OF O CCURE NCE S

09760-049

2716

1

5871

75

OVERSAMPLING BY 64

0

1000

2000

3000

4000

6000

5000

7000

–2 –1

CODE

0 1

NUMBER OF O CCURE NCE S

09760-050

2245

0

–10

–20

–30

–40

–50

–60

–70

–80

100 1k 10k 100k 10M1M

–90

ATTENUATION (dB)

FREQUENCY ( Hz )

AV

CC

= 5V

V

DRIVE

= 5V

T

A

= 25°C
10V RANGE
OS BY 2

09760-051

0

–10

–20

–30

–40

–50

–60

–70

–80

100 1k 10k 100k 10M1M

–100

–90

ATTENUATION (dB)

FREQUENCY ( Hz )

09760-052

AV

CC

= 5V

V

DRIVE

= 5V

T

A

= 25°C
10V RANGE
OS BY 4

When the oversampling mode is selected, this has the effect
of adding a digital filter function after the ADC. The different
oversampling rates and the CONVST x sampling frequency
produces different digital filter frequency profiles.

Figure 54 to Figure 59 show the digital filter frequency profiles
for the different oversampling rates. The combination of the
analog antialiasing filter and the oversampling digital filter can
be used to eliminate or reduce the complexity of the design of
the filter before the AD7609. The digital filtering combines
steep roll-off and linear phase response.

Figure 51. Histogram of Codes—OS × 16 (Six Codes)

Figure 52. Histogram of Codes—OS × 32 (Four Codes)

Figure 53. Histogram of Codes – OS × 64 (Four Codes)

Figure 54. Digital Filter Response for OS × 2

Figure 55. Digital Filter Response for OS × 4

Rev. A | Page 30 of 36

Data Sheet AD7609

0

–10

–20

–30

–40

–50

–60

–70

–80

100 1k 10k 100k 10M1M

–100

–90

ATTENUATION (dB)

FREQUENCY ( Hz )

AV

CC

= 5V

V

DRIVE

= 5V

T

A

= 25°C

10V RANGE
OS BY 8

09760-053

0

–10

–20

–30

–40

–50

–60

–70

–80

100 1k 10k 100k 10M1M

–100

–90

ATTENUATION (dB)

FREQUENCY ( Hz )

AV

CC

= 5V

V

DRIVE

= 5V

T

A

= 25°C

10V RANGE
OS BY 16

09760-054

0

–10

–20

–30

–40

–50

–60

–70

–80

100 1k 10k 100k 10M1M

–100

–90

ATTENUATION (dB)

FREQUENCY ( Hz )

AV

CC

= 5V

V

DRIVE

= 5V

T

A

= 25°C
10V RANGE
OS BY 32

09760-055

0

–10

–20

–30

–40

–50

–60

–70

–80

100 1k 10k 100k 10M1M

–100

–90

ATTENUATION (dB)

FREQUENCY ( Hz )

AV

CC

= 5V

V

DRIVE

= 5V

T

A

= 25°C
10V RANGE
OS BY 64

09760-056

Figure 56. Digital Filter Response for OS × 8

Figure 57. Digital Filter Response for OS × 16

Figure 58. Digital Filter Response for OS × 32

Figure 59. Digital Filter Response for OS × 64

Rev. A | Page 31 of 36

AD7609 Data Sheet

09760-057

09760-058

LAYOUT GUIDELINES

The printed circuit board that houses the AD7609 should be
designed so that the analog and digital sections are separated
and confined to different areas of the board.

Use at least one ground plane. It can be common or split
between the digital and analog sections. In the case of the split
plane, the digital and analog ground planes should be joined in
only one place, preferably as close as possible to the AD7609.

If the AD7609 is in a system where multiple devices require
analog-to-digital ground connections, the connection should
still be made at only one point, a star ground point, which
should be established as close as possible to the AD7609. Good
connections should be made to the ground plane. Avoid sharing
one connection for multiple ground pins. Individual vias or
multiple vias to the ground plane should be used for each
ground pin.

Avoid running digital lines under the devices because doing
so couples noise onto the die. Allow the analog ground plane
to run under the AD7609 to avoid noise coupling. Shield fast­switching signals like CONVST A, CONVST B, or clocks with
digital ground to avoid radiating noise to other sections of the
board, and they should never run near analog signal paths.
Avoid crossover of digital and analog signals. Run traces on
layers in close proximity on the board at right angles to each
other to reduce the effect of feedthrough through the board.

The power supply lines to the AV

and V

CC

pins on the

DRIVE

AD7609 should use as large a trace as possible to provide low

impedance paths and reduce the effect of glitches on the power
supply lines. Where possible, use supply planes. Good connec­tions should be made between the AD7609 supply pins and the
power tracks on the board; this should involve the use of a single
via or multiple vias for each supply pin.

Good decoupling is also important to lower the supply imped­ance presented to the AD7609 and to reduce the magnitude of
the supply spikes. Place the decoupling capacitors close to,
ideally right up against, these pins and their corresponding
ground pins. Place the decoupling capacitors for the REFIN/
REFOUT pin and the REFCAPA and REFCAPB pins as close as
possible to their respective AD7609 pins. Where possible, they
should be placed on the same side of the board as the AD7609
device. Figure 60 shows the recommended decoupling on the
top layer of the AD7609 board. Figure 61 shows bottom layer
decoupling. Bottom layer decoupling is for the four AV
and the V

DRIVE

pin.

CC

pins

Figure 60. Top Layer Decoupling REFIN/REFOUT, REFCAPA, REFCAPB, and

REGCAP Pins

Figure 61. Bottom Layer Decoupling

Rev. A | Page 32 of 36

Data Sheet AD7609

09760-059

To ensure good device-to-device performance matching in a
system that contains multiple AD7609 devices, a symmetrical
layout between the AD7609 devices is important. Figure 62
shows a layout with two AD7609 devices. The AV
plane runs to the right of both devices. The V
runs to the left of the two AD7609 devices. The reference chip
is positioned between both AD7609 devices and the reference
voltage track runs north to Pin 42 of U1 and south to Pin 42
to U2. A solid ground plane is used. These symmetrical layout
principles can be applied to a system that contains more than
two AD7609 devices. The AD7609 devices can be placed in a
north-to-south direction with the reference voltage located
midway between the AD7609 devices and the reference track
running in the north-to-south direction similar to Figure 62.

supply

CC

supply track

DRIVE

Figure 62. Multiple AD7609 Layout, Top Layer and Supply Plane Layer

Rev. A | Page 33 of 36

AD7609 Data Sheet

COMPLIANT TO JE DE C S TANDARDS MS-026-BCD

051706-A

TOP VIEW

(PINS DOW N)

1

16

17

33

32

48

4964

0.27

0.22

0.17

0.50
BSC

LEAD PITCH

12.20

12.00 SQ

11.80

PIN 1

1.60
MAX

0.75

0.60

0.45

10.20

10.00 SQ

9.80

VIEW A

0.20

0.09

1.45

1.40

1.35

0.08
COPLANARITY

VIEW A

ROTATED 90° CCW

SEATING
PLANE

0.15

0.05

7°

3.5°
0°

OUTLINE DIMENSIONS

Figure 63. 64-Lead Low Profile Quad Flat Package [LQFP]

(ST-64-2)

Dimensions shown in millimeters

ORDERING GUIDE

Model1 Temperature Range Package Description Package Option

AD7609BSTZ −40°C to +85°C 64-Lead Low Profile Quad Flat Package [LQFP] ST-64-2
AD7609BSTZ-RL −40°C to +85°C 64-Lead Low Profile Quad Flat Package [LQFP] ST-64-2
EVA L-AD7609EDZ −40°C to +85°C Evaluation Board for the AD7609
CED1Z Converter Evaluation Development

1

Z = RoHS Compliant Part.

Rev. A | Page 34 of 36

Data Sheet AD7609

NOTES

Rev. A | Page 35 of 36

AD7609 Data Sheet

©2011–2012 Analog Devices, Inc. All rights reserved. Trademarks and

NOTES

registered trademarks are the property of their respective owners.
D09760-0-2/12(A)

Rev. A | Page 36 of 36