Bit, Bipolar
Input, Simultaneous Sampling ADC
AD7606/AD7606-6/AD7606-4
Rev. C
Trademarks and registered trademarks are the property of their respective owners.
Fax: 781.461.3113 ©2010–2012 Analog Devices, Inc. All rights reserved.
V1
V1GND
R
FB
1MΩ
1MΩ
R
FB
CLAMP
CLAMP
SECOND-
ORDER LPF
T/H
V2
V2GND
R
FB
1MΩ
1MΩ
R
FB
CLAMP
CLAMP
SECOND-
ORDER LPF
T/H
V3
V3GND
R
FB
1MΩ
1MΩ
R
FB
CLAMP
CLAMP
SECOND-
ORDER LPF
T/H
V4
V4GND
R
FB
1MΩ
1MΩ
R
FB
CLAMP
CLAMP
SECOND-
ORDER LPF
T/H
V5
V5GND
R
FB
1MΩ
1MΩ
R
FB
CLAMP
CLAMP
SECOND-
ORDER LPF
T/H
V6
V6GND
R
FB
1MΩ
1MΩ
R
FB
CLAMP
CLAMP
SECOND-
ORDER LPF
T/H
V7
V7GND
R
FB
1MΩ
1MΩ
R
FB
CLAMP
CLAMP
SECOND-
ORDER LPF
T/H
V8
V8GND
R
FB
1MΩ
1MΩ
R
FB
CLAMP
CLAMP
SECOND-
ORDER LPF
T/H
8:1
MUX
AGND
BUSY
FRSTDATA
CONVST A CONVST B
RESET
RANGE
CONTROL
INPUTS
CLK OSC
REFIN/REFOUT
REF SELECT
AGND
OS 2
OS 1
OS 0
D
OUT
A
D
OUT
B
RD/SCLK
CS
PAR/SER/BYTE SEL
V
DRIVE
16-BIT
SAR
DIGITAL
FILTER
PARALLEL/
SERIAL
INTERFACE
2.5V
REF
REFCAPB
REFCAPA
SERIAL
PARALLEL
REGCAP
2.5V
LDO
REGCAP
2.5V
LDO
AV
CC
AV
CC
DB[15:0]
AD7606
08479-001
Data Sheet
FEATURES
8/6/4 simultaneously sampled inputs
True bipolar analog input ranges: ±10 V, ±5 V
Single 5 V analog supply and 2.3 V to 5 V V
Fully integrated data acquisition solution
Analog input clamp protection
Input buffer with 1 MΩ analog input impedance
Second-order antialiasing analog filter
On-chip accurate reference and reference buffer
16-bit ADC with 200 kSPS on all channels
Oversampling capability with digital filter
Flexible parallel/serial interface
SPI/QSPI™/MICROWIRE™/DSP compatible
Performance
7 kV ESD rating on analog input channels
95.5 dB SNR, −107 dB THD
±0.5 LSB INL, ±0.5 LSB DNL
Low power: 100 mW
Standby mode: 25 mW
64-lead LQFP package
DRIVE
8-/6-/4-Channel DAS with 16-
APPLICATIONS
Power-line monitoring and protection systems
Multiphase motor control
Instrumentation and control systems
Multiaxis positioning systems
Data acquisition systems (DAS)
Table 1. High Resolution, Bipolar Input, Simultaneous
Sampling DAS Solutions
Resolution
18 Bits AD7608 AD7609 8
16 Bits AD7606 8
AD7606-6 6
AD7606-4 4
14 Bits AD7607 8
FUNCTIONAL BLOCK DIAGRAM
SingleEnded
Inputs
Tru e
Differential
Inputs
Number of
Simultaneous
Sampling Channels
Information furnishe d by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Figure 1.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
AD7606/AD7606-6/AD7606-4 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
General Description ......................................................................... 3
Specifications ..................................................................................... 4
Timing Specifications .................................................................. 7
Absolute Maximum Ratings .......................................................... 11
Thermal Resistance .................................................................... 11
ESD Caution ................................................................................ 11
Pin Configurations and Function Descriptions ......................... 12
Typical Performance Characteristics ........................................... 17
Term i nol ogy .................................................................................... 21
Theory of Operation ...................................................................... 22
Converter Details........................................................................ 22
Analog Input ............................................................................... 22
ADC Transfer Function ............................................................. 23
Internal/External Reference ...................................................... 24
Typ i cal Connection Diagram ................................................... 25
Power-Down Modes .................................................................. 25
Conversion Control ................................................................... 26
Digital Interface .............................................................................. 27
Parallel Interface (
Parallel Byte (
Serial Interface (
Reading During Conversion ..................................................... 28
Digital Filter ................................................................................ 29
Layout Guidelines....................................................................... 32
Outline Dimensions ....................................................................... 34
Ordering Guide .......................................................................... 34
PAR
/SER/BYTE SEL = 0) .......................... 27
PAR
/SER/BYTE SEL = 1, DB15 = 1) ............... 27
PAR
/SER/BYTE SEL = 1) ............................. 27
REVISION HISTORY
1/12—Rev. B to Rev. C
Changes to Analog Input Ranges Section ................................... 22
10/11—Rev. A to Rev. B
Changes to Input High Voltage (V
(V
) Parameters and Endnote 6, Table 2 ..................................... 4
INL
Changes to Table 3 ............................................................................ 7
Changes to Table 4 .......................................................................... 11
Changes to Pin 32 Description, Table 6 ....................................... 13
Changes to Analog Input Clamp Protection Section ................. 22
Changes to Typical Connection Diagram Section ..................... 25
8/10—Rev. 0 to Rev. A
Changes to Note 1, Table 2 .............................................................. 6
5/10—Revision 0: Initial Versi o n
) and Input Low Voltage
INH
Rev. C | Page 2 of 36
Data Sheet AD7606/AD7606-6/AD7606-4
GENERAL DESCRIPTION
The AD76061/AD7606-6/AD7606-4 are 16-bit, simultaneous
sampling, analog-to-digital data acquisition systems (DAS) with
eight, six, and four channels, respectively. Each part contains
analog input clamp protection, a second-order antialiasing filter,
a track-and-hold amplifier, a 16-bit charge redistribution successive
approximation analog-to-digital converter (ADC), a flexible
digital filter, a 2.5 V reference and reference buffer, and high
speed serial and parallel interfaces.
The AD7606/AD7606-6/AD7606-4 operate from a single 5 V
supply and can accommodate ±10 V and ±5 V true bipolar input
signals while sampling at throughput rates up to 200 kSPS for
all channels. The input clamp protection circuitry can tolerate
voltages up to ±16.5 V. The AD7606 has 1 MΩ analog input
impedance regardless of sampling frequency. The single supply
operation, on-chip filtering, and high input impedance eliminate
the need for driver op amps and external bipolar supplies. The
AD7606/AD7606-6/AD7606-4 antialiasing filter has a 3 dB cutoff
frequency of 22 kHz and provides 40 dB antialias rejection when
sampling at 200 kSPS. The flexible digital filter is pin driven, yields
improvements in SNR, and reduces the 3 dB bandwidth.
1
Patent pending.
Rev. C | Page 3 of 36
AD7606/AD7606-6/AD7606-4 Data Sheet
No oversampling; ±5 V range
87
89 dB
t
±10 V Range
11 µs
DC ACCURACY
Bipolar Zero Code Error2, 6
±10 V range
±1
±6
LSB
SPECIFICATIONS
V
= 2.5 V external/internal, AVCC = 4.75 V to 5.25 V, V
REF
Table 2.
Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE fIN = 1 kHz sine wave unless otherwise noted
Signal-to-Noise Ratio (SNR)
2, 3
Oversampling by 16; ±10 V range; fIN = 130 Hz 94 95.5 dB
Oversampling by 16; ±5 V range; fIN = 130 Hz 93 94.5 dB
No oversampling; ±10 V Range 88.5 90 dB
No oversampling; ±5 V range 87.5 89 dB
Signal-to-(Noise + Distortion) (SINAD)2 No oversampling; ±10 V range 88 90 dB
Dynamic Range No oversampling; ±10 V range 90.5 dB
No oversampling; ±5 V range 90 dB
Total Harmonic Distortion (THD)2 −107 −95 dB
Peak Harmonic or Spurious Noise (SFDR)2 −108 dB
Intermodulation Distortion (IMD)2 fa = 1 kHz, fb = 1.1 kHz
Second-Order Terms −110 dB
Third-Order Terms −106 dB
Channel-to-Channel Isolation2 fIN on unselected channels up to 160 kHz −95 dB
ANALOG INPUT FILTER
Full Power Bandwidth −3 dB, ±10 V range 23 kHz
−3 dB, ±5 V range 15 kHz
−0.1 dB, ±10 V range 10 kHz
−0.1 dB, ±5 V range 5 kHz
GROUP DELAY
±5 V Range 15 µs
= 2.3 V to 5.25 V, f
DRIVE
= 200 kSPS, TA = T
SAMPLE
MIN
to T
, unless otherwise noted.1
MAX
Resolution No missing codes 16 Bits
Differential Nonlinearity2 ±0.5 ±0.99 LSB4
Integral Nonlinearity2 ±0.5 ±2 LSB
Total Unadjusted Error (TUE) ±10 V range ±6 LSB
±5 V range ±12 LSB
Positive Full-Scale Error
2, 5
External reference ±8 ±32 LSB
Internal reference ±8 LSB
Positive Full-Scale Error Drift External reference ±2 ppm/°C
Internal reference ±7 ppm/°C
Positive Full-Scale Error Matching2 ±10 V range 5 32 LSB
±5 V range 16 40 LSB
± 5 V range ±3 ±12 LSB
Bipolar Zero Code Error Drift ±10 V range 10 µV/°C
± 5 V range 5 µV/°C
Bipolar Zero Code Error Matching2 ±10 V range 1 8 LSB
±5 V range 6 22 LSB
Negative Full-Scale Error
2, 5
External reference ±8 ±32 LSB
Internal reference ±8 LSB
Negative Full-Scale Error Drift External reference ±4 ppm/°C
Internal reference ±8 ppm/°C
Negative Full-Scale Error Matching2 ±10 V range 5 32 LSB
±5 V range 16 40 LSB
Rev. C | Page 4 of 36
Data Sheet AD7606/AD7606-6/AD7606-4
5 V; see Figure 31
2.5 µA
AD7606-4
12
17
mA
Parameter Test Conditions/Comments Min Typ Max Unit
ANALOG INPUT
Input Voltage Ranges RANGE = 1 ±10 V
RANGE = 0 ±5 V
Analog Input Current 10 V; see Figure 31 5.4 µA
Input Capacitance7 5 pF
Input Impedance See the Analog Input section 1 MΩ
REFERENCE INPUT/OUTPUT
Reference Input Voltage Range See the ADC Transfer Function section 2.475 2.5 2.525 V
DC Leakage Current ±1 µA
Input Capacitance7 REF SELECT = 1 7.5 pF
Reference Output Voltage REFIN/REFOUT 2.49/
2.505
Reference Temperature Coefficient ±10 ppm/°C
LOGIC INPUTS
Input High Voltage (V
Input Low Voltage (V
) 0.7 × V
INH
) 0.3 × V
INL
V
DRIVE
Input Current (IIN) ±2 µA
Input Capacitance (CIN)7 5 pF
LOGIC OUTPUTS
Output High Voltage (VOH) I
Output Low Voltage (VOL) I
= 100 µA V
SOURCE
= 100 µA 0.2 V
SINK
− 0.2 V
DRIVE
Floating-State Leakage Current ±1 ±20 µA
Floating-State Output Capacitance7 5 pF
Output Coding Twos complement
CONVERSION RATE
Conversion Time All eight channels included; see Table 3 4 µs
Track-and-Hold Acquisition Time 1 µs
Throughput Rate Per channel, all eight channels included 200 kSPS
POWER REQUIREMENTS
AVCC 4.75 5.25 V
V
2.3 5.25 V
DRIVE
I
Digital inputs = 0 V or V
TOTAL
DRIVE
Normal Mode (Static) AD7606 16 22 mA
AD7606-6 14 20 mA
V
V
DRIVE
Normal Mode (Operational)8 f
= 200 kSPS
SAMPLE
AD7606 20 27 mA
AD7606-6 18 24 mA
AD7606-4 15 21 mA
Standby Mode 5 8 mA
Shutdown Mode 2 6 µA
Rev. C | Page 5 of 36
AD7606/AD7606-6/AD7606-4 Data Sheet
AD7606-6
90
126
mW
Parameter Test Conditions/Comments Min Typ Max Unit
Power Dissipation
Normal Mode (Static) AD7606 80 115.5 mW
Normal Mode (Operational)8 f
AD7606 100 142 mW
AD7606-4 75 111 mW
Standby Mode 25 42 mW
Shutdown Mode 10 31.5 µW
1
Temperature range for the B version is −40°C to +85°C. The AD7606 is operational up to 125°C with throughput rates ≤ 160 kSPS, and the SNR typically reduces by
0.7 dB at 125°C.
2
See the Terminology section.
3
This specification applies when reading during a conversion or after a conversion. If reading during a conversion in parallel mode with V
and THD by 3 dB.
4
LSB means least significant bit. With ±5 V input range, 1 LSB = 152.58 µV. With ±10 V input range, 1 LSB = 305.175 µV.
5
These specifications include the full temperature range variation and contribution from the internal reference buffer but do not include the error contribution from
the external reference.
6
Bipolar zero code error is calculated with respect to the analog input voltage. See the Analog Input Clamp Protection section.
7
Sample tested during initial release to ensure compliance.
8
Operational power/current figure includes contribution when running in oversampling mode.
= 200 kSPS
SAMPLE
= 5 V, SNR typically reduces by 1.5 dB
DRIVE
Rev. C | Page 6 of 36
Data Sheet AD7606/AD7606-6/AD7606-4
PARALLEL/SERIAL/BYTE MODE
t
2
Conversion time
16.05
18.8
16.05
18.8
µs
Oversampling by 4; AD7606
t
100
100
µs
t
20
20
ns
BUSY to OS x pin setup time
t4 0 0
ns
21
24
ns
V
above 3.3 V
TIMING SPECIFICATIONS
AVCC = 4.75 V to 5.25 V, V
Table 3.
Parameter Min Typ Max Min Typ Max Unit Description
t
1/throughput rate
CYCLE
5 5 µs Parallel mode, reading during or after conversion; or
9.4 µs Serial mode reading after a conversion; V
9.7 10.7 µs Serial mode reading after a conversion; V
CONV
3.45 4 4.15 3.45 4 4.15 µs Oversampling off; AD7606
3 3 µs Oversampling off; AD7606-6
2 2 µs Oversampling off; AD7606-4
7.87 9.1 7.87 9.1 µs Oversampling by 2; AD7606
= 2.3 V to 5.25 V, V
DRIVE
Limit at T
(0.1 × V
Logic Input Levels)
0.9 × V
= 2.5 V external reference/internal reference, TA = T
REF
MIN
DRIVE
DRIVE
, T
MAX
and
Limit at T
(0.3 × V
0.7 × V
MIN
DRIVE
DRIVE
, T
MAX
and
Logic Input Levels)
to T
MIN
serial mode: V
DRIVE
conversion using D
D
A and D
OUT
OUT
B lines
, unless otherwise noted.1
MAX
= 3.3 V to 5.25 V, reading during a
A and D
OUT
OUT
B lines
DRIVE
DRIVE
= 2.7 V
= 2.3 V,
33 39 33 39 µs Oversampling by 8; AD7606
66 78 66 78 µs Oversampling by 16; AD7606
133 158 133 158 µs Oversampling by 32; AD7606
257 315 257 315 µs Oversampling by 64; AD7606
STBY
WAKE-UP STAND BY
rising edge to CONVST x rising edge; power-up
time from standby mode
t
WAKE-UP S HUTDOWN
Internal Reference 30 30 ms
STBY
rising edge to CONVST x rising edge; power-up
time from shutdown mode
External Reference 13 13 ms
STBY
rising edge to CONVST x rising edge; power-up
time from shutdown mode
t
50 50 ns RESET high pulse width
RESET
OS_SETUP
t
OS_HOLD
20 20 ns BUSY to OS x pin hold time
t1 40 45 ns CONVST x high to BUSY high
t2 25 25 ns Minimum CONVST x low pulse
t3 25 25 ns Minimum CONVST x high pulse
BUSY falling edge to CS falling edge setup time
3
t
0.5 0.5 ms Maximum delay allowed between CONVST A, CONVST
5
B rising edges
t6 25 25 ns
Maximum time between last
CS
rising edge and BUSY
falling edge
t7 25 25 ns Minimum delay between RESET low to CONVST x high
PARALLEL/BYTE READ
OPERATION
t8 0 0 ns
t9 0 0 ns
t10
16 19 ns V
25 30 ns V
32 37 ns V
t11 15 15 ns
t12 22 22 ns
CS
to RD setup time
CS
to RD hold time
RD
low pulse width
above 4.75 V
DRIVE
DRIVE
above 2.7 V
DRIVE
above 2.3 V
DRIVE
RD
high pulse width
CS
high pulse width (see Figure 5); CS and RD linked
Rev. C | Page 7 of 36
AD7606/AD7606-6/AD7606-4 Data Sheet
25
30
ns
V
above 2.7 V
17
15
MHz
V
above 3.3 V
t18
t
Data access time after SCLK rising edge
FRSTDATA OPERATION
20
23
ns
V
above 3.3 V
20
23
ns
V
above 3.3 V
Limit at T
(0.1 × V
0.9 × V
Logic Input Levels)
MIN
DRIVE
DRIVE
, T
MAX
and
Parameter Min Typ Max Min Typ Max Unit Description
t13
16 19 ns V
20 24 ns V
30 37 ns V
4
t
14
16 19 ns V
21 24 ns V
25 30 ns V
32 37 ns V
t15 6 6 ns
t16 6 6 ns
t17 22 22 ns
SERIAL READ OPERATION
f
Frequency of serial read clock
SCLK
23.5 20 MHz V
14.5 12.5 MHz V
11.5 10 MHz V
15 18 ns V
20 23 ns V
30 35 ns V
4
19
17 20 ns V
23 26 ns V
27 32 ns V
34 39 ns V
t20 0.4 t
t21 0.4 t
0.4 t
SCLK
0.4 t
SCLK
t22 7 7 SCLK rising edge to D
t23 22 22 ns
Limit at T
(0.3 × V
0.7 × V
MIN
DRIVE
DRIVE
, T
MAX
and
Logic Input Levels)
Delay from
above 4.75 V
DRIVE
above 3.3 V
DRIVE
DRIVE
above 2.3 V
DRIVE
Data access time after
above 4.75 V
DRIVE
above 3.3 V
DRIVE
above 2.7 V
DRIVE
above 2.3 V
DRIVE
Data hold time after
CS
to DB[15:0] hold time
Delay from
enabled
above 4.75 V
DRIVE
DRIVE
above 2.7 V
DRIVE
above 2.3 V
DRIVE
Delay from CS until D
disabled/delay from
above 4.75 V
DRIVE
above 3.3 V
DRIVE
= 2.3 V to 2.7 V
DRIVE
above 4.75 V
DRIVE
above 3.3 V
DRIVE
above 2.7 V
DRIVE
above 2.3 V
DRIVE
ns SCLK low pulse width
SCLK
ns SCLK high pulse width
SCLK
CS
rising edge to D
CS
until DB[15:0] three-state disabled
RD
falling edge
RD
falling edge
CS
rising edge to DB[15:0] three-state
A/D
B three-state
OUT
until MSB valid
A/D
B valid hold time
OUT
B three-state enabled
OUT
OUT
OUT
CS
OUT
A/D
t24
15 18 ns V
20 23 ns V
25 30 ns V
30 35 ns V
t25 ns
15 18 ns V
25 30 ns V
30 35 ns V
t26
16 19 ns V
25 30 ns V
30 35 ns V
Rev. C | Page 8 of 36
Delay from
CS
state disabled
above 4.75 V
DRIVE
above 3.3 V
DRIVE
above 2.7 V
DRIVE
above 2.3 V
DRIVE
Delay from
CS
serial mode
above 4.75 V
DRIVE
DRIVE
above 2.7 V
DRIVE
above 2.3 V
DRIVE
Delay from
DRIVE
DRIVE
DRIVE
DRIVE
RD
above 4.75 V
above 2.7 V
above 2.3 V
falling edge until FRSTDATA three-
falling edge until FRSTDATA high,
falling edge to FRSTDATA high
Data Sheet AD7606/AD7606-6/AD7606-4
t28 Delay from 16th SCLK falling edge to FRSTDATA low
t
CYCLE
t
3
t
5
t
2
t
4
t
1
t
7
t
RESET
t
CONV
CONVST A,
CONVST B
CONVST A,
CONVST B
BUSY
CS
RESET
08479-002
t
CYCLE
t
3
t
5
t
6
t
2
t
1
t
CONV
CONVST A,
CONVST B
CONVST A,
CONVST B
BUSY
CS
t
7
t
RESET
RESET
08479-003
Limit at T
(0.1 × V
0.9 × V
Logic Input Levels)
MIN
DRIVE
DRIVE
, T
MAX
and
Parameter Min Typ Max Min Typ Max Unit Description
t27
19 22 ns V
24 29 ns V
Limit at T
(0.3 × V
0.7 × V
MIN
DRIVE
DRIVE
, T
MAX
and
Logic Input Levels)
Delay from
= 3.3 V to 5.25V
DRIVE
= 2.3 V to 2.7V
DRIVE
RD
falling edge to FRSTDATA low
17 20 ns V
22 27 ns V
t29 24 29 ns
= 3.3 V to 5.25V
DRIVE
= 2.3 V to 2.7V
DRIVE
Delay from
CS
rising edge until FRSTDATA three-
state enabled
1
Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of V
2
In oversampling mode, typical t
t
= 3 µs; and for the AD7606-4, t
CONV
3
The delay between the CONVST x signals was measured as the maximum time allowed while ensuring a <10 LSB performance matching between channel sets.
4
A buffer is used on the data output pins for these measurements, which is equivalent to a load of 20 pF on the output pins.
for the AD7606-6 and AD7606-4 can be calculated using ((N × t
CONV
= 2 µs.
CONV
) + ((N − 1) × 1 µs)). N is the oversampling ratio. For the AD7606-6,
CONV
) and timed from a voltage level of 1.6 V.
DRIVE
Timing Diagrams
Figure 2. CONVST Timing—Reading After a Conversion
Figure 3. CONVST Timing—Reading During a Conversion
Rev. C | Page 9 of 36
AD7606/AD7606-6/AD7606-4 Data Sheet
CS
t
9
t
16
t
17
t
29
08479-004
t
16
t
17
RD
DATA:
DB[15:0]
FRSTDATA
t
8
t
10
t
13
INVALID V1 V2 V3 V7 V8V4
t
26
t
24
t
11
t
14
t
27
Figure 4. Parallel Mode, Separate
CS
and RD Pulses
t
15
t
12
CS AND RD
t
13
DATA:
DB[15:0]
V1 V2 V3 V4 V5 V6 V7 V8
FRSTDATA
Figure 5.
CS
and RD, Linked Parallel Mode
8479-005
CS
t21t
SCLK
D
OUT
D
OUT
FRSTDATA
t
t
A,
B
18
19
DB15 DB14 DB13 DB1 DB0
t
25
20
t
22
t
28
t
23
t
29
08479-006
Figure 6. Serial Read Operation (Channel 1)
RD
DATA: DB[7:0]
FRSTDATA
CS
t
t
t
8
t
10
13
INVALID
24
HIGH
BYTE V1
t
26
t
14
LOW
BYTE V1
t
27
t
15
HIGH
BYTE V8
t
11
LOW
BYTE V8
t
29
t
9
t
16
t
17
08479-007
Figure 7. BYTE Mode Read Operation
Rev. C | Page 10 of 36
Data Sheet AD7606/AD7606-6/AD7606-4
Input Current to Any Pin Except Supplies1
±10 mA
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 4.
Parameter Rating
AVCC to AGND −0.3 V to +7 V
V
to AGND −0.3 V to AVCC + 0.3 V
DRIVE
Analog Input Voltage to AGND1 ±16.5 V
Digital Input Voltage to AGND −0.3 V to V
Digital Output Voltage to AGND −0.3 V to V
REFIN to AGND −0.3 V to AVCC + 0.3 V
Operating Temperature Range
B Version −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
Pb/SN Temperature, Soldering
Reflow (10 sec to 30 sec) 240 (+0)°C
Pb-Free Temperature, Soldering Reflow 260 (+0)°C
ESD (All Pins Except Analog Inputs) 2 kV
ESD (Analog Input Pins Only) 7 kV
1
Transient currents of up to 100 mA do not cause SCR latch-up.
DRIVE
DRIVE
+ 0.3 V
+ 0.3 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages. These
specifications apply to a 4-layer board.
Table 5. Thermal Resistance
Package Type θJA θJC Unit
64-Lead LQFP 45 11 °C/W
ESD CAUTION
Rev. C | Page 11 of 36
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