ANALOG DEVICES AD 7541 AKN Datasheet

®

R

P

E

T

E

L

O

S

B

O
I

S

S

O

P

UB

S

E

L

B

UT

T

I

T

S

1

2

5

7

D

A

T

C

U

D

O

R

P

E

T

UC

D

O

Data Sheet May 2002

AD7541

FN3107.3

12-Bit, Multiplying D/A Converter

The AD7541 is a monolithic, low cost, high performance ,
12-bit accurate, multiplying digital-to-analog converter
(DAC).

Intersil’ wafer level laser-trimmed thin-film resistors on
CMOS circuitry provide true 12-bit linearity with TTL/CMOS
compatible operation.

Special tabbed-resistor geometries (improving time stability),
full input protection from damage due to static discharge by
diode clamps to V+ and ground, large I

OUT1

and I

OUT2

bus
lines (improving superposition errors) are some of the
features offered by Intersil AD7541.

Pinout

AD7541

(PDIP)

TOP VIEW

I

OUT1

I

OUT2

GND

BIT 1 (MSB)

BIT 2
BIT 3
BIT 4
BIT 5
BIT 6

1
2
3
4
5
6
7
8
9

18

R

FEEDBACK

17

V

REF IN

16

V+

15

BIT 12 (LSB)

14

BIT 11
BIT 10

13

BIT 9

12

BIT 8

11

BIT 7

10

Features

• 12-Bit Linearity 0.01%

•Pretrimmed Gain

• Low Gain and Linearity Tempcos

• Full Temperature Range Operation

• Full Input Static Protection

• TTL/CMOS Compatible

• +5V to +15V Supply Range

• 20mW Low Power Dissipation

• Current Settling Time 1µs to 0.01% of FSR

• Four Quadrant Multiplication

Functional Block Diagram

V

REF IN

(17)

SPDT
NMOS

SWITCHES

NOTE: Switches shown for digital inputs “High”.

10kΩ 10kΩ 10kΩ 10kΩ

MSB

(4)

BIT 3BIT 2

(5) (6)

10kΩ

20kΩ

(3)

I

(2)

OUT2

I

(1)

OUT1

R

FEEDBACK

(18)

20kΩ20kΩ20kΩ20kΩ20kΩ

Part Number Information

PART NUMBER NONLINEARITY TEMP. RANGE (oC) PACKAGE PKG. NO.

AD7541JN 0.02% (11-Bit) 0 to 70 18 Ld PDIP E18.3

AD7541KN 0.01% (12-Bit) 0 to 70 18 Ld PDIP E18.3

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

| Intersil (and design) is a trademark of Intersil Americas Inc.

Copyright © Intersil Americas Inc. 2002. All Rights Reserved

AD7541

Absolute Maximum Ratings Thermal Information

Supply Voltage (V+ to GND) . . . . . . . . . . . . . . . . . . . . . . . . . . +17V

V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25V

REF

Digital Input Voltage Range. . . . . . . . . . . . . . . . . . . . . . . V+ to GND

Output Voltage Compliance. . . . . . . . . . . . . . . . . . . . .-100mV to V+

Operating Conditions

Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

1. θ

JA

Thermal Resistance (Typical, Note 1) θ

(oC/W)

JA

PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . .150

Maximum Storage Temperature . . . . . . . . . . . . . . . -65

o

C to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300

o

o

C

C

Electrical Specifications V+ = +15V, V

PARAMETER TEST CONDITIONS

= +10V, V

REF

OUT1

= V

= 0V, TA = 25oC, Unless Otherwise Specified

OUT2

= 25oCT

T

A

MIN-MAX

A

UNITSMIN TYP MAX MIN MAX

SYSTEM PERFORMANCE (Note 4)

Resolution 12 - - 12 - Bits
Nonlinearity J -10V ≤ V

V

K--±0.012 - ±0.012 % of FSR

OUT1

See Figure 4 (Note 5)

= V

REF

≤ +10V

OUT2

= 0V

--±0.024 - ±0.024 % of FSR

Monotonicity Guaranteed
Gain Error -10V ≤ V
Output Leakage Current (Either Output) V

OUT1

≤ +10V (Note 5) - - ±0.3 - ±0.4 % of FSR

REF

= V

= 0 - - ±50 - ±200 nA

OUT2

DYNAMIC CHARACTERISTICS

Power Supply Rejection V+ = 14.5V to 15.5V

See Figure 5 (Note 5)

Output Current Settling Time To 0.1% of FSR

--±0.005 - ±0.01 % of FSR/% of
∆V+

--1-1 µs

See Figure 9 (Note 6)

Feedthrough Error V

= 20V

REF

All Digital Inputs Low

P-P

, 10kHz

--1-1mV

See Figure 8 (Note 6)

P-P

REFERENCE INPUTS

Input Resistance All Digital Inputs High

I

at Ground

OUT1

51020520 kΩ

ANALOG OUTPUT

Voltage Compliance Both Outputs, See Maximum

-100mV to V+

Ratings (Note 7)

Output Capacitance C

C
C
C

OUT1

OUT2

OUT1

OUT2

All Digital Inputs High
See Figure 7 (Note 6)

All Digital Inputs Low
See Figure 7 (Note 6)

- - 200 - 200 pF

--60-60 pF

--60-60 pF

- - 200 - 200 pF

Output Noise (Both Outputs) See Figure 6 Equivalent to 10kΩ Johnson Noise

2

AD7541

Electrical Specifications V+ = +15V, V

PARAMETER TEST CONDITIONS

DIGITAL INPUTS

Low State Threshold, V
High State Threshold, V
Input Current V
Input Coding See Tables 1 and 2 (Note 6) Binary/Offset Binary
Input Capacitance (Note 6) - - 8 - 8 pF

POWER SUPPLY CHARACTERISTICS

Power Supply Voltage Range Accuracy Is Not Guaranteed Over

I+ All Digital Inputs High or Low

Total Power Dissipation (Including Ladder Network) - 20 - - - mW

NOTES:

2. The digital control inputs are zener protected; however, permanent damage may occur on unconnected units under high energy electrostatic
fields. Keep unused units in conductive foam at all times.

3. Do not apply voltages higher than V

4. Full scale range (FSR) is 10V for unipolar and ±10V for bipolar modes.

5. Using internal feedback resistor, R

6. Guaranteed by design or characterization and not production tested.

7. Accuracy not guaranteed unless outputs at ground potential.

IL

IH

(Notes 2, 6) - - 0.8 - 0.8 V

IN

This Range

(Excluding Ladder Network)

or less than GND potential on any terminal except V

DD

FEEDBACK

= +10V, V

REF

= 0V or V+ (Note 6) - - ±1-±1 µA

.

OUT1

= V

= 0V, TA = 25oC, Unless Otherwise Specified (Continued)

OUT2

= 25oCT

T

A

2.4 - - 2.4 - V

+5 to +16 V

- - 2.0 - 2.5 mA

and R

REF

MIN-MAX

A

FEEDBACK

.

UNITSMIN TYP MAX MIN MAX

Definition of Terms

Nonlinearity: Error contributed by deviation of the DAC
transfer function from a “best fit straight line” function.
Normally expressed as a percentage of full scale range. For
a multiplying DAC, this should hold true over the entire V
range.

Resolution: Value of the LSB. F or example, a unipolar
converter with n bits has a resolution of LSB = (V

REF

bipolar converter of N bits has a resolution of
LSB = (V

REF

(N-1)

)/2

. Resolution in no way implies linearity.

Settling Time: Time required for the output function of the
DAC to settle to within

1

/2 LSB for a given digital input

stimulus, i.e., 0 to Full Scale.
Gain Error: Ratio of the DAC’s operational amplifier output

voltage to the nominal input voltage value.
Feedthrough Error: Error caused by capacitive coupling

from V
Output Capacitance: Capacita nce from I

to output with all switches OFF.

REF

OUT1

, and I

terminals to ground.
Output Leakage Current: Current which appears on

I

, terminal when all digital inputs are LOW or on I

OUT1

terminal when all inputs are HIGH.

REF

)/2N. A

OUT2

OUT2

Detailed Description

The AD7541 is a 12-bit, monolithic, multiplying D/A converte r.
A highly stable thin film R-2R resistor ladder network and
NMOS SPDT switches form the basis of the converter circuit.
CMOS level shifters provide low power TTL/CMOS
compatible operation. An external voltage or current reference
and an operational amplifier are all that is required for most
voltage output applications. A simplified equivalent circuit of
the DAC is shown on page 1, (Functional Diagram). The
NMOS SPDT switches steer the ladder leg currents between
I

OUT1

and I

buses which must be held at ground

OUT2

potential. This configuration maintains a constant current in
each ladder leg independent of the input code. Converter
errors are further eliminated by using wider metal
interconnections between the major bits and the outputs. Use
of high threshold switches reduces the offset (leakage) errors
to a negligible level.

Each circuit is laser-trimmed, at the wafer level, to better
than 12-bits linearity. For the first four bits of the ladder,
special trim-tabbed geometries are used to keep the body of
the resistors, carrying the majority of the output current,
undisturbed. The resultant time stability of the trimmed
circuits is comparable to that of untrimmed units.

3

AD7541

The level shifter circuits are comprised of three inverters with
a positive feedback from the output of the second to first
(Figure 1). This configuration results in TTL/COMS
compatible operation over the full military temperature
range. With the ladder SPDT switches driven by the level
shifter, each switch is binary weighted for an “ON” resistance
proportional to the respective ladder leg current. This
assures a constant voltage drop across each switch,
creating equipotential terminations for the 2R ladder resistor,
resulting in accurate leg currents.

V+

TTL/CMOS

INPUT

FIGURE 1. CMOS LEVEL SHIFTER AND SWITCH

13

4

6

TO LADDER

89

5

72

I

OUT2IOUT1

Typical Applications

General Recommendations

Static performance of the AD7541 depends on I
I

(pin 1 and pin 2) potentials being exactly equal to

OUT2

GND (pin 3).
The output amplifier should be selected to have a low input

bias current (typically less than 75nA), and a low drift
(depending on the temperature range). The voltage offset of
the amplifier should be nulled (typically less than ±200µV).

The bias current compensation resistor in the amplifier’s
non-inverting input can cause a variable offset. Non­inverting input should be connected to GND with a low
resistance wire.

Ground-loops must be avoided by taking all pins going to
GND to a common point, using separate connections.

The V+ (pin 16) power supply should have a low noise level
and should not have any transients exceeding +17V.

Unused digital inputs must be connected to GND or V+ for
proper operation.

A high value resistor (~1MΩ) can be used to prevent static
charge accumulation, when the inputs are open-circuited for
any reason.

When gain adjustment is required, low tempco
(approximately 50ppm/

o

C) resistors or trim-pots should be

selected.

OUT1

and

Unipolar Binary Operation

The circuit configuration for operating the AD7541 in
unipolar mode is shown in Figure 2. With positive and
negative V

values the circuit is capable of 2-Quadrant

REF

multiplication. The “Digital Input Code/Analog Output Value”
table for unipolar mode is given in Table 1. A Schottky diode
(HP5082-2811 or equivalent) prevents I

from negative

OUT1

excursions which could damage the device. This precaution
is only necessary with certain high speed amplifiers.

+15V

V

REF

±10V

BIT 1 (MSB)

DIGITAL

INPUT

BIT 12 (LSB)

FIGURE 2. UNIPOLAR BINARY OPERATION (2-QUADRANT

17

4
5

AD7541

15
GND

MULTIPLICATION)

R

16

FEEDBACK

18

I

OUT1

1

I

OUT2

2

3

CR1

-

+

V

A

OUT

Zero Offset Adjustment

1. Connect all digital inputs to GND.

2. Adjust the offset zero adjust trimpot of the output
operational amplifier for 0V ±0.5mV (Max) at V

OUT

.

Gain Adjustment

1. Connect all digital inputs to VDD.

2. Monitor V

3. To increase V
250Ω), in the I

4. To decrease V

OUT

for a -V

OUT

OUT1
OUT

REF

, connect a series resistor, (0Ω to

amplifier feedback loop.

, connect a series resistor, (0Ω to
250Ω), between the reference voltage and the V
terminal.

TABLE 1. CODE TABLE - UNIPOLAR BINARY OPERATION

DIGITAL INPUT ANALOG OUTPUT

111111111111 -V
100000000001 -V
100000000000 -V
011111111111 -V
000000000001 -V
000000000000 0

(1 - 1/

REF
REF
REF
REF
REF

12

) reading.

2

(1 - 1/
(1/2 + 1/
/2
(1/2 - 1/

12

(1/

2

REF

12

)

2

12

)

2

12

)

2

)

Bipolar (Offset Binary) Operation

The circuit configuration for operating the AD7541 in the
bipolar mode is given in Figure 3. Usi n g offset binary digital
input codes and positive and negative reference voltage
values Four-Quadrant multiplication can be realized. The
“Digital Input Code/Analog Output Value” table for bipolar
mode is given in Table 2.

4

AD7541

A “Logic 1” input at any digital input forces the corresponding
ladder switch to steer the bit current to I
input forces the bit current to I
I

OUT1

and I

bus currents are complements of one

OUT2

another. The current amplifier at I
I

current and the transconductance amplifier at I

OUT2

bus. For any code the

OUT2

OUT2

bus. A “Logic 0”

OUT1

changes the polarity of

OUT1

output sums the two currents. This configuration doubles the
output range of the DAC. The difference current resulting at
zero offset binary code, (MSB = “Logic 1”, All other bits =
“Logic 0”), is corrected by using an external resistive divider,
from V

REF

to I

OUT2

.

Offset Adjustment

1. Adjust V

2. Set R4 to zero.

3. Connect all digital inputs to “Logic 1”.

4. Adjust I
±0.1mV at I

5. Connect a short circuit across R2.

6. Connect all digital inputs to “Logic 0”.

7. Adjust I
±0.1mV at I

8. Remove short circuit across R2.

to approximately +10V.

REF

amplifier offset zero adjust trimpot for 0V

OUT1

OUT2

amplifier output.

OUT2

amplifier offset zero adjust trimpot for 0V

amplifier output.

OUT1

9. Connect MSB (Bit 1) to “Logic 1” and all other bits to
“Logic 0”.

10. A djust R4 for 0V ±0.2mV at V

OUT

.

Gain Adjustment

1. Connect all digital inputs to VDD.

2. Monitor V

3. To increase V
250Ω), in the I

4. To decrease V

OUT

for a -V

OUT

OUT1

REF

, connect a series resistor, (0Ω to

amplifier feedback loop.

, connect a series resistor, (0Ω to

OUT

250Ω), between the reference voltage and the V
terminal.

TABLE 2. CODE TABLE - BIPOLAR (OFFSET BINARY)

OPERATION

DIGITAL INPUT ANALOG OUTPUT

111111111111 -V
100000000001 -V
100000000000 0
011111111111 V
000000000001 V
000000000000 V

(1 - 1/

REF

REF

REF

REF

REF

11

) volts reading.

2

11

(1 - 1/

2

11

(1/

)

2

11

(1/

)

2

11

(1 - 1/

)

2

REF

)

V

REF

DIGITAL

INPUT

±10V

+15V

17

BIT 1 (MSB)

BIT 12 (LSB)

NOTE: R1 and R2 should be 0.01%, low-TCR resistors.

FIGURE 3. BIPOLAR OPERATION (4-QUADRANT MULTIPLICATION)

4

15

16

AD7541

3

18

GND

I

OUT1

1

2

I

OUT2

-

A1

6

+

R1 10K

R2 10K

R5 10K

-

A2

6

+

R3
390K

V

OUT

R4
500Ω

5

Test Circuits

AD7541

12-BIT

BINARY

COUNTER

CLOCK

V

REF

+10V

BIT 1 (MSB)

BIT 12
(LSB)

V

REF

BIT 1 (MSB)

BIT 12
(LSB)

BIT 1
(MSB)

BIT 12
BIT 13
BIT 14

+15V

4

5

15

V

REF

REFERENCE

17 16

AD7541

AD7541

14-BIT

DAC

3

GND

18

1

2

R

FEEDBACK

I

OUT1

I

OUT2

-

HA2600

+

10K

0.01%

10K 0.01%

FIGURE 4. NONLINEARITY TEST CIRCUIT

+15V

UNGROUNDED
SINE WAVE
GENERATION
40Hz 1.0V

P-P

-

17 16
4
5

AD7541
15

3

18

GND

R
I

OUT1

1

I

OUT2

2

5K 0.01%

FEEDBACK

5K 0.01%

-

HA2600
+

HA2600

+

1MΩ

-

HA2600

+

500K

LINEARITY
ERROR X 100

V

ERROR

X 100

+11V (ADJUST FOR V

15µF

6

FIGURE 5. POWER SUPPLY REJECTION TEST CIRCUIT

= 0V)

OUT

+15V

1K

100Ω 10K

17 16
4
5

AD7541

15

I

OUT2

2

-

I

OUT1

1

3

1K50K

0.1µF

101ALN
+

-50V

V

FIGURE 6. NOISE TEST CIRCUIT

OUT

f = 1kHz

BW = 1Hz

QUAN

TECH

MODEL

134D

WAVE

ANALYZER

Test Circuits (Continued)

AD7541

+15V

BIT 1 (MSB)

BIT 12 (LSB)

NC +15V

17 16

4
5

AD7541

17

3

V

= 20V

REF

SCOPE

NC

1K

100mV
1MHz

P-P

18

1
2

10kHz SINE WAVE

P-P

BIT 1 (MSB)

BIT 12 (LSB)

+15V

17 16
4
5

AD7541

15

3

GND

18

I

OUT1

1

I

OUT2

2

FIGURE 7. OUTPUT CAPACITANCE TEST CIRCUIT FIGURE 8. FEEDTHROUGH ERROR TEST CIRCUIT

+5V

0V

DIGITAL INPUT

+10V

BIT 12 (LSB)

V

REF

BIT 1 (MSB)

17 16
4
5

AD7541

15

3

+15V

EXTRAPOLATE

1

I

OUT2

2

GND

+100mV

3t: 5% SETTLING
9t: 0.01% SETTLING

100Ω

OSCILLOSCOPE

3

2

HA2600

6

V

OUT

FIGURE 9. OUTPUT CURRENT SETTLING TIME TEST CIRCUIT

+10V

V

REF

BIT 1 (MSB)

BIT 2

BIT 12 (LSB)

17 16
4
5

AD7541

15

FIGURE 10. GENERAL DAC CIRCUIT WITH COMPENSATION CAPACITOR, C

Dynamic Performance

The dynamic performance of the DAC, also depends on the
output amplifier selection. For low speed or static
applications, AC specifications of the amplifier are not very
critical. For high-speed applications slew-rate, settling-time,
openloop gain and gain/phase-margin specifications of the
amplifier should be selected for the de si re d p erf ormance.

The output impedance of the AD7541 looking into I
varies between 10kΩ (R
(R

FEEDBACK

in parallel with the ladder resistance).

FEEDBACK

alone) and 5kΩ

OUT1

3

+15V

18

GND

R

FEEDBACK

C

I

OUT1

1

I

OUT2

2

C

-

A

+

V

OUT

C

Similarly the output capacitance varies between the
minimum and the maximum values depending on the input
code. These variations necessitate the use of compensation
capacitors, when high speed amplifiers are used.

A capacitor in parallel with the feedback resistor (as shown
in Figure 10) provides the necessary phase compensation to
critically damp the output.

A small capacitor connected to the compensation pin of the
amplifier may be required for unstable situations causing
oscillations. Careful PC board layout, minimizing parasitic
capacitances, is also vital.

7

Dual-In-Line Plastic Packages (PDIP)

AD7541

N

D1

-C-

E1

-B-

A1

A2

E

A

L

e

C

C

L

e

A

C

e

B

INDEX

AREA

BASE

PLANE

SEATING

PLANE

D1

B1

12 3 N/2

-A­D

e

B

0.010 (0.25) C AM BS

NOTES:

1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.

4. Dimensions A, A1 and L are measured with the package seated in
JEDEC seating plane gauge GS-3.

5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).

6. E and are measured with the leads constrained to be perpendic-

7. e

e

A

ular to datum .

and eC are measured at the lead tips with the leads unconstrained.

B

e

must be zero or greater.

C

-C-

8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).

9. N is the maximum number of terminal positions.

10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).

E18.3 (JEDEC MS-001-BC ISSUE D)

18 LEAD DUAL-IN-LINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A - 0.210 - 5.33 4
A1 0.015 - 0.39 - 4
A2 0.115 0.195 2.93 4.95 -

B 0.014 0.022 0.356 0.558 ­B1 0.045 0.070 1.15 1.77 8, 10

C 0.008 0.014 0.204 0.355 -

D 0.845 0.880 21.47 22.35 5
D1 0.005 - 0.13 - 5

E 0.300 0.325 7.62 8.25 6
E1 0.240 0.280 6.10 7.11 5

e 0.100 BSC 2.54 BSC ­e

A

e

B

0.300 BSC 7.62 BSC 6

- 0.430 - 10.92 7
L 0.115 0.150 2.93 3.81 4
N18 189

NOTESMIN MAX MIN MAX

Rev. 0 12/93

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data she ets are current before placin g orders. Information furn ished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or othe rwise under any patent or patent rights of Intersil or its subsidia ries.

For information regarding Intersil Corporation and its products, see www.intersil.com

8