Analog Devices AD75019 Datasheet

16 ⴛ 16 Crosspoint

SHIFT

REGISTER

CELL #256

LATCH

SERIAL DATA IN

ANALOG

SWITCH

BUSED CLOCK

LINES

SERIAL

DATA
TO NEXT
STAGES

+12V –12V +5V DGND

AD75019

16 3 16 ARRAY OF SWITCHES,

LATCHES, AND SHIFT REGISTER

CELLS (ONLY TWO LOCATIONS

ARE SHOWN FOR CLARITY)

SHIFT

REGISTER

CELL #1

LATCH

ANALOG

SWITCH

PARALLEL

CLOCK

SERIAL
CLOCK

SERIAL

DATA
FROM

PRIOR

STAGES

BUSED CLOCK

LINES

VDDVSSV

CC

DGND

X0 X15

ANALOG

INPUTS/OUTPUTS

Y0

Y15

ANALOG

OUTPUTS/

INPUTS

PCLK SCLK SOUT

a

FEATURES
256 Switches in a 16 ⴛ 16 Array
Wide Signal Range: to Supply Rails of 24 V or ⴞ12 V
Low On-Resistance: 200 ⍀ Typ
TTL/CMOS/Microprocessor-Compatible Control Lines
Serial Input Simplifies Interface
Serial Output Allows Cascading for More Channels
Low Power Consumption: 2 mW Quiescent
Compact 44-Lead PLCC

PRODUCT DESCRIPTION

The AD75019 contains 256 analog switches in a 16 × 16 array.

Any of the X or Y pins may serve as an input or output. Any or
all of the X terminals may be programmed to connect to any or
all of the Y terminals. The switches can accommodate signals
with amplitudes up to the supply rails and have a typical on-

resistance of 150 Ω.

Data is loaded serially via the SIN input and clocked into an on­board 256-bit shift register via SCLK. When all the switch set­tings have been programmed, data is transferred into a set of
256 latches via PCLK. The serial shift register is dynamic, so
there is a minimum clock rate of 20 kHz. The maximum clock

rate of 5 MHz allows loading times as short as 52 µs. The switch

control latches are static and will hold their data as long as power
is applied.

Switch Array

AD75019

FUNCTIONAL BLOCK DIAGRAM

To extend the number of switches in the array, you may cascade
multiple AD75019s. The SOUT output is the end of the shift
register, and may be connected to the SIN input of the next
AD75019.

The AD75019 is fabricated in Analog Devices’ BiMOS II
process. This epitaxial BiCMOS process features CMOS
devices for low distortion switches and bipolar devices for
ESD protection.

REV. C

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1999

1

AD75019–SPECIFICATIONS

AD75019 Symbol Min Typ Max Units

MULTIPLEXER

Input Signal Range V
Switch ON Resistance, V
Switch ON Resistance, V
Switch ON Resistance Matching
Leakage Current, V
Input/Output Capacitance C
Isolation Between Any Two Channels

R

= 600 Ω, RL = 10 kΩ, V

S

f

= 1 kHz 92 dB

SIGNAL

f

= 20 kHz 69 dB

SIGNAL

f

= 1 MHz 38 dB

SIGNAL

Total Harmonic Distortion

R

= 600 Ω, RL = 10 kΩ, V

S

Switch Frequency Response, –3 dB

R

= 600 Ω, RL = 10 kΩ, V

S

Propagation Delay 48 ns

DIGITAL INPUTS (SIN, SCLK, PCLK)

Logic Levels (TTL Compatible)

Input Voltage, Logic “1” V
Input Voltage, Logic “0” V
Input Current, V
Input Current, V

Input Capacitance C

IH

IL

DIGITAL OUTPUTS (SOUT)

Logic Levels (TTL Compatible)

Output Voltage, Logic “1” V
Output Voltage, Logic “0” V
Output Current, V
Output Current, VOL = 0.4 V I

POWER SUPPLY REQUIREMENTS

Voltage Range, Total Analog V
Voltage Range, Positive Analog V
Voltage Range, Negative Analog V
Voltage Range, Digital V
Supply Current, SCLK = 5 MHz, I

V

= 0.8 V, VIH = 2.4 V I

IL

Supply Current, Quiescent, I

VIL = 0.8 V, VIH = 2.4 V I

TEMPERATURE RANGE

Operating T

Storage –65 +150 °C

NOTES

1

All minimum and maximum specifications are guaranteed, and specifications shown in boldface are tested on all production units at final electrical test. Results from those tests
are used to calculate outgoing quality levels.

2

Switch resistance matching is measured with zero volts at each analog input and refers to the difference between the maximum and minimum values.

Specifications subject to change without notice.

and V

DD

and V

DD

= ±10 V 2 10 nA

SIGNAL

= ±12 V, V

SS

= ±5 V, V

SS

2

, V

SIGNAL

= 2 V p-p

SIGNAL

= 2 V p-p 0.01 %

SIGNAL

= 2 V p-p 20 MHz

SIGNAL

SIGNAL

= ±12 V ∆R

= 5.5 V I

= 0.8 V I

= 2.8 V I

OH

PIN FUNCTION DESCRIPTIONS

(TA = +25ⴗC, VDD and VSS = ⴞ12 V, VCC = +5 V unless otherwise noted)

= ±12 V R

SIGNAL

= ±5 V R

IN

ON

ON

ON

IN

IH

IL

IH

IL

IN

OH

OL

OH

OL

DD – VSS

– V

DD

– V

SS

– V

CC

, I

DD

SS

CC

, I

DD

SS

CC

, T

MIN

DGND

DGND

DGND

MAX

VSS – 0.5 VDD + 0.5 V

150 300 Ω
300 500 Ω
20 30 Ω

2.4 5.5 V
0 0.8 V

2.8 V

3.2 mA

3.2 mA

9.0 25.2 V
(VCC – 0.5) 25.2 V
–20.7 0 V

4.5 5 5.5 V

_ ⴞ400 µA
_ 100 µA

–25 +85 °C

PIN CONFIGURATION

25 pF

±1 µA
±1 µA

10 pF

0.4 V

±70 mA
800 µA

Pin Name Description

1 PCLK Parallel Clock Input
2 SCLK Serial Clock Input
3 SIN Serial Data Input
4VSSNegative Analog Power Supply
5 NC No Internal Connection
6 NC No Internal Connection
7 Y15 Analog Output (or Input)
8 Y14 Analog Output (or Input)
9 Y13 Analog Output (or Input)
10 Y12 Analog Output (or Input)
11 Y11 Analog Output (or Input)
12 Y10 Analog Output (or Input)
13 Y9 Analog Output (or Input)
14 Y8 Analog Output (or Input)
15 X0 Analog Input (or Output)
16 X1 Analog Input (or Output)
17 X2 Analog Input (or Output)
18 X3 Analog Input (or Output)
19 X4 Analog Input (or Output)
20 X5 Analog Input (or Output)
21 X6 Analog Input (or Output)
22 X7 Analog Input (or Output)

Pin Name Description

23 X8 Analog Input (or Output)
24 X9 Analog Input (or Output)
25 X10 Analog Input (or Output)
26 X11 Analog Input (or Output)
27 X12 Analog Input (or Output)
28 X13 Analog Input (or Output)
29 X14 Analog Output (or Input)
30 X15 Analog Output (or Input)
31 Y0 Analog Output (or Input)
32 Y1 Analog Output (or Input)
33 Y2 Analog Output (or Input)
34 Y3 Analog Output (or Input)
35 Y4 Analog Output (or Input)
36 Y5 Analog Output (or Input)
37 Y6 Analog Output (or Input)
38 Y7 Analog Output (or Input)
39 NC No Internal Connection
40 NC No Internal Connection
41 V
42 V
43 DGND Digital Ground

Positive Analog Power Supply

DD

Digital Power Supply

CC

44 SOUT Serial Data Output: Positive True

–2–

NCNCV

6 5 4 3 2 1 44 43 42 41 40

7

Y15
Y14

8
9

Y13

10

Y12
Y11

11
12

Y10

13

Y9

14

Y8

15

X0

16

X1

17

X2

18 19 20 21 22 23 24 25 26 27 28

X3

NC = NO CONNECT

SS

(Not to Scale)

X4

X5X6X8

SIN

SCLK

PCLK

AD75019

TOP VIEW

X7

SOUT

DGND

PIN 1
IDENTIFIER

X9

X10

CC

V

X11

DD

NC

V

X12

X13

REV. C

39

NC

38

Y7

37

Y6

36

Y5

35

Y4

34

Y3

33

Y2

32

Y1

31

Y0

30

X15

29

X14