ANALOG DEVICES AD7492 Service Manual

1.25 MSPS, 16 mW Internal REF and CLK,

A

V

FEATURES

Specified for VDD of 2.7 V to 5.25 V Throughput rate of 1 MSPS (AD7492) Throughput rate of 1.25 MSPS (AD7492-5) Throughput rate of 400 kSPS (AD7492-4) Low power 4 mW typ at 1 MSPS with 3 V supplies 11 mW typ at 1 MSPS with 5 V supplies Wide input bandwidth 70 dB typ SNR at 100 kHz input frequency

2.5 V internal reference On-chip CLK oscillator Flexible power/throughput rate management No pipeline delays High speed parallel interface Sleep mode: 50 24-lead SOIC and TSSOP packages

nA typ

V

CONVST

12-Bit Parallel ADC

FUNCTIONAL BLOCK DIAGRAM

V

DV

DD

4

2.5V REF

6

IN

10

T/H

AD7492

REF OUT

20 5

CLOCK

BUF

AGND DGND

OSCILLAT OR

12-BIT SAR

ADC

CONTROL

LOGIC

719

Figure 1.

AD7492

DRIVE

21

OUTPUT

DRIVERS

11

12

8

9

DB11

DB0

PS/FS

CS

RD

BUSY

01128-001

GENERAL DESCRIPTION

The AD7492, AD7492-4, and AD7492-5 are 12-bit high speed, low power, successive approximation ADCs. The parts operate from a single 2.7 V to 5.25 V power supply and feature throughput rates up to 1.25 MSPS. They contain a low noise, wide bandwidth track/hold amplifier that can handle bandwidths up to 10 MHz.

The conversion process and data acquisition are controlled using standard control inputs allowing for easy interface to microprocessors or DSPs. The input signal is sampled on the falling edge of point. The BUSY pin goes high at the start of conversion and goes low 880 ns (AD7492/AD7492-4) or 680 ns (AD7492-5) later to indicate that the conversion is complete. There are no pipeline delays associated with the part. The conversion result is accessed via standard parallel interface.

The AD7492 uses advanced design techniques to achieve very low power dissipation at high throughput rates. With 5 V supplies and 1.25 MSPS, the average current consumption AD7492-5 is typically 2.75 mA. The part also offers flexible power/throughput rate management.

It is also possible to operate the part in a full sleep mode and a partial sleep mode, where the part wakes up to do a conversion and automatically enters a sleep mode at the end of conversion.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

CONVST

CS

and conversion is also initiated at this

and RD signals over a high speed

FS

The type of sleep mode is hardware selected by the PS/

pin.

Using these sleep modes allows very low power dissipation numbers at lower throughput rates.

The analog input range for the part is 0 V to REFIN. The

2.5 V reference is supplied internally and is available for external referencing. The conversion rate is determined by the internal clock.

PRODUCT HIGHLIGHTS

1. High Throughput with Low Power Consumption. The

AD7492-5 offers 1.25 MSPS throughput with 16 mW power consumption.

2. Flexible Power/Throughput Rate Management. The

conversion time is determined by an internal clock. The part also features two sleep modes, partial and full, to maximize power efficiency at lower throughput rates.

3. No Pipeline Delay. The part features a standard successive

approximation ADC with accurate control of the sampling instant via a control.

4. Flexible Digital Interface. The V

voltage levels on the I/O digital pins.

5. Fewer Peripheral Components. The AD7492 optimizes

PCB space by using an internal reference and internal CLK.

CONVST

input and once-off conversion

feature controls the

DRIVE

AD7492

REVISION HISTORY

5/06—Rev. 0 to Rev. A

Added AD7492-4................................................................Universal

Changes to Table 4............................................................................ 8

Updated Outline Dimensions....................................................... 22

Changes to Ordering Guide.......................................................... 22

1/01—Revision 0: Initial Version

Rev. A | Page 2 of 24

AD7492

SPECIFICATIONS

AD7492-5

VDD = 4.75 V to 5.25 V, TA = T

Table 1.

Parameter A Version1 B Version1 Unit Test Conditions/Comments

DYNAMIC PERFORMANCE fS = 1.25 MSPS

Signal-to-Noise and Distortion (SINAD) 69 69 dB typ fIN = 500 kHz sine wave 68 68 dB min fIN = 100 kHz sine wave Signal-to-Noise Ratio (SNR) 70 70 dB typ fIN = 500 kHz sine wave 68 68 dB min fIN = 100 kHz sine wave Total Harmonic Distortion (THD) −83 −83 dB typ fIN = 500 kHz sine wave

−87 −87 dB typ fIN = 100 kHz sine wave

−75 −75 dB max fIN = 100 kHz sine wave Peak Harmonic or Spurious-Free

Dynamic Noise (SFDR)

−90 −90 dB typ fIN = 100 kHz sine wave

−76 −76 dB max fIN = 100 kHz sine wave Intermodulation Distortion (IMD)

Second Order Terms −82 −82 dB typ fIN = 500 kHz sine wave

−90 −90 dB typ fIN = 100 kHz sine wave Third Order Terms −71 −71 dB typ fIN = 500 kHz sine wave

−88 −88 dB typ fIN = 100 kHz sine wave Aperture Delay 5 5 ns typ Aperture Jitter 15 15 ps typ Full Power Bandwidth 10 10 MHz typ

DC ACCURACY fS = 1.25 MSPS

Resolution 12 12 Bits Integral Nonlinearity ±1.5 ±1.25 LSB max Differential Nonlinearity +1.5/–0.9 +1.5/−0.9 LSB max

Offset Error ±9 ±9 LSB max Gain Error ±2.5 ±2.5 LSB max

ANALOG INPUT

Input Voltage Ranges 0 to 2.5 0 to 2.5 V DC Leakage Current ±1 ±1 μA max Input Capacitance 33 33 pF typ

REFERENCE OUTPUT

REF OUT Output Voltage Range 2.5 2.5 V ±1.5% for specified performance

LOGIC INPUTS

Input High Voltage, V Input Low Voltage, V

INH

2

INL

Input Current, IIN ±1 ±1 μA max Typically 10 nA, VIN = 0 V or VDD Input Capacitance, C

3

10 10 pF max

IN

LOGIC OUTPUTS

Output High Voltage, VOH V Output Low Voltage, VOL 0.4 0.4 V max I Floating-State Leakage Current ±10 ±10 μA max Floating-State Output Capacitance 10 10 pF max Output Coding

to T

MIN

2

V

, unless otherwise noted.

MAX

V

−83 −83 dB typ f

× 0.7 V

DRIVE

× 0.3 V

DRIVE

− 0.2 V

DRIVE

Straight (natural) binary

× 0.7 V min VDD = 5 V ± 5%

DRIVE

× 0.3 V max VDD = 5 V ± 5%

DRIVE

− 0.2 V min I

DRIVE

Straight (natural) binary

= 500 kHz sine wave

IN

Guaranteed no missed codes to 12 bits (A and B versions)

= 200 μA

SOURCE

= 200 μA

SINK

Rev. A | Page 3 of 24

AD7492

Parameter A Version1 B Version1 Unit Test Conditions/Comments

CONVERSION RATE

Conversion Time 680 680 ns max

Track/Hold Acquisition Time 120 120 ns min

Throughput Rate 1.25 1.25 MSPS max

POWER REQUIREMENTS

V

4.75/5.25 4.75/5.25 V min/max

DD

IDD Digital I/Ps = 0 V or DVDD

Normal Mode 3.3 3.3 mA max fS = 1.25 MSPS, typ 2.75 mA Quiescent Current 1.8 1.8 mA max Partial Sleep Mode 250 250 μA max Static, typ 190 μA Full Sleep Mode 1 1 μA max Static, typ 200 nA

Power Dissipation4 Digital I/Ps = 0 V or DVDD

Normal Mode 16.5 16.5 mW max Partial Sleep Mode 1.25 1.25 mW max Full Sleep Mode 5 5 μW max

1

Temperature ranges as follows: A and B Versions: −40°C to +85°C.

2

V

and V

INH

3

Sample tested @ 25°C to ensure compliance.

4

See the Power vs. Throughput section.

trigger levels are set by the V

INL

voltage. The logic interface circuitry is powered by V

DRIVE

.

AD7492/AD7492-4

VDD = 2.7 V to 5.25 V, TA = T

MIN

to T

, unless otherwise noted.

MAX

Table 2.

Parameter A Version

2

DYNAMIC PERFORMANCE fS = 1 MSPS for AD7492

f

Signal-to-Noise and Distortion (SINAD) 69 69 dB typ fIN = 500 kHz sine wave

68 68 dB min fIN = 100 kHz sine wave

Signal-to-Noise Ratio (SNR) 70 70 dB typ fIN = 500 kHz sine wave3

68 68 dB min fIN = 100 kHz sine wave

Total Harmonic Distortion (THD) −85 −85 dB typ fIN = 500 kHz sine wave3

−87 −87 dB typ fIN = 100 kHz sine wave

−75 −75 dB max fIN = 100 kHz sine wave

Peak Harmonic or Spurious-Free

−86 −86 dB typ f

Dynamic Noise (SFDR)

−90 −90 dB typ fIN = 100 kHz sine wave

−76 −76 dB max fIN = 100 kHz sine wave

Intermodulation Distortion (IMD)

Second Order Terms −77 −77 dB typ fIN = 500 kHz sine wave3

−90 −90 dB typ fIN = 100 kHz sine wave Third Order Terms −69 −69 dB typ fIN = 500 kHz sine wave3

−88 −88 dB typ fIN = 100 kHz sine wave

Aperture Delay 5 5 ns typ

Aperture Jitter 15 15 ps typ

Full Power Bandwidth 10 10 MHz typ

1

B Version2 Unit Test Conditions/Comments

Conversion time + acquisition time

= 400 kSPS for AD7492-4

S

= 500 kHz sine wave3

IN

3

Rev. A | Page 4 of 24

AD7492

Parameter A Version

2

B Version2 Unit Test Conditions/Comments

DC ACCURACY fS = 1 MSPS for AD7492

f

= 400 kSPS for AD7492-4

S

Resolution 12 12 Bits Integral Nonlinearity ±1.5 LSB max ±0.6 LSB typ VDD = 5 V ±1 LSB max VDD = 3 V Differential Nonlinearity +1.5/−0.9 +1.5/−0.9 LSB max Guaranteed no missed codes to 12 bits (A and B versions) Offset Error ±9 ±9 LSB max Gain Error ±2.5 ±2.5 LSB max

ANALOG INPUT

Input Voltage Ranges 0 to 2.5 0 to 2.5 V DC Leakage Current ±1 ±1 μA max Input Capacitance 33 33 pF typ

REFERENCE OUTPUT

REF OUT Output Voltage Range 2.5 2.5 V ±1.5% for specified performance

LOGIC INPUTS

Input High Voltage, V Input Low Voltage, V

4

V

INH

4

V

INL

× 0.7 V

DRIVE

× 0.3 V

DRIVE

× 0.7 V min VDD = 5 V ± 5%

DRIVE

× 0.3 V max VDD = 5 V ± 5%

DRIVE

Input Current, IIN ±1 ±1 μA max Typically 10 nA, VIN = 0 V or VDD

5

Input Capacitance, C

3,

10 10 pF max

IN

LOGIC OUTPUTS

Output High Voltage, VOH V Output Low Voltage, VOL 0.4 0.4 V max I

− 0.2 V

DRIVE

− 0.2 V min I

DRIVE

= 200 μA

SOURCE

= 200 μA

SINK

Floating-State Leakage Current ±10 ±10 μA max Floating-State Output Capacitance 10 10 pF max Output Coding

Straight (Natural) Binary

CONVERSION RATE

Conversion Time 880 880 ns max Track/Hold Acquisition Time 120 120 ns min Throughput Rate 1

400

1 MSPS max

kSPS max

Conversion time + acquisition time for AD7492

Conversion time + acquisition time for AD7492-4

POWER REQUIREMENTS

VDD 2.7/5.25 2.7/5.25 V min/max IDD Digital I/Ps = 0 V or DVDD.

Normal Mode 3 3 mA max fS = 1 MSPS, typ 2.2 mA

f

= 400 kSPS, Typ 2.2 mA

S

(AD7492-4) Quiescent Current 1.8 1.8 mA max Partial Sleep Mode 250 250 μA max Static, typ 190 μA Full Sleep Mode 1 1 μA max Static, typ 200 nA

Power Dissipation

4, 6

Digital I/Ps = 0 V or DVDD Normal Mode 15 15 mW max VDD = 5 V Partial Sleep Mode 1.25 1.25 mW max VDD = 5 V Full Sleep Mode 5 5 μW max VDD = 5 V

1

Only A version specification applies to the AD7492-4.

2

Temperature ranges as follows: A and B versions: −40°C to +85°C.

3

500 kHz sine wave specifications do not apply for the AD7492-4.

4

V

and V

INH

5

Sample tested @ 25°C to ensure compliance.

6

See the Power vs. Throughput section.

trigger levels are set by the V

INL

voltage. The logic interface circuitry is powered by V

DRIVE

.

Rev. A | Page 5 of 24

AD7492

TIMING SPECIFICATIONS

VDD = 2.7 V to 5.25 V, TA = T

MIN

to T

, unless otherwise noted.

MAX

Table 3.

Limit at T

MIN

, T

MAX

Parameter AD7492/AD7492-4 AD7492-52 Unit Description

t

880 680 ns max

CONVER T

t

203 203 μs max Partial Sleep Wake-Up Time

WAKE UP

500 500 μs max Full Sleep Wake-Up Time t1 10 10 ns min t2 10 10 ns max

40 N/A ns max t3 0 0 ns max

4

t

0 0 ns max

4

t5 20 20 ns min

4

t

15 15 ns min

6

5

t

8 8 ns max

7

t8 0 0 ns max t9 120 120 ns min Acquisition Time t10 100 100 ns min Quiet Time

1

Sample tested @ 25°C to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V (see Figure 2).

2

The AD7492-5 is specified with VDD = 4.75 V to 5.25 V.

3

This is the time needed for the part to settle within 0.5 LSB of its stable value. Conversion can be initiated earlier than 20 μs, but there is no guarantee that the part

samples within 0.5 LSB of the true analog input value. Therefore, the user should not start conversion until after the specified time.

4

Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V

5

t7 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated

back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t7, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading.

1

CONVST Pulse Width CONVST to BUSY Delay, VDD = 5 V CONVST to BUSY Delay, VDD = 3 V BUSY to

CS Setup Time CS to RD Setup Time RD Pulse Width Data Access Time after Falling Edge of Bus Relinquish Time after Rising Edge of

RD

CS to RD Hold Time

TO OUTPUT

50pF

200µA

C

L

200µA

I

OL

1.6V

I

OH

1128-002

Figure 2. Load Circuit for Digital Output Timing Specifications

Rev. A | Page 6 of 24

AD7492

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 4.

Parameter Ratings

AV

to AGND/DGND −0.3 V to +7 V

DD

DV

to AGND/DGND −0.3 V to +7 V

DD

V

to AGND/DGND −0.3 V to +7 V

DRIVE

AVDD to DV V

DRIVE

−0.3 V to +0.3 V

DD

to DV

−0.3 V to DV

DD

+ 0.3 V

DD

AGND to DGND −0.3 V to +0.3 V Analog Input Voltage to AGND −0.3 V to AVDD + 0.3 V Digital Input Voltage to DGND −0.3 V to DVDD + 0.3 V Input Current to Any Pin Except

Supplies

1

Operating Temperature Range

±10 mA

Commercial (A and B Versions) −40°C to +85°C Storage Temperature Range −65°C to +150°C

Junction Temperature 150°C SOIC, TSSOP Package Dissipation 450 mW

θ

Thermal Impedance 75°C/W (SOIC)

JA

θ

Thermal Impedance 25°C/W (SOIC)

JC

Lead Temperature, Soldering

115°C/W (TSSOP)

35°C/W (TSSOP)

Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C

1

Transient currents of up to 100 mA do not cause SCR latch-up.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Rev. A | Page 7 of 24

AD7492

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

DB9

DB10

(MSB) DB11

AV

REF OUT

V

AGND

CS

RD

CONVST

PS/FS

BUSY

DD

IN

1

2

3

4

5

AD7492

6

TOP VIEW

(Not to Scale)

7

8

9

10

11

12

24

23

22

21

20

19

18

17

16

15

14

13

DB8

DB7

DB6

V

DRIVE

DV

DD

DGND

DB5

DB4

DB3

DB2

DB1

DB0 (LSB)

01128-003

Figure 3. Pin Configuration

Table 5. Pin Function Descriptions

Pin Mnemonic Function

1 to 3, 13 to 18, 22 to 24

4 AVDD

DB11 to DB0

Data Bit 11 to Data Bit 0. Parallel digital outputs that provide the conversion result for the part. These are three-state outputs that are controlled by determined by the V

DRIVE

input.

CS and RD. The output high voltage level for these outputs is

Analog Supply Voltage, 2.7 V to 5.25 V. This is the only supply voltage for all analog circuitry on the AD7492. The AV

and DVDD voltages should ideally be at the same potential and must not be more than 0.3 V apart,

DD

even on a transient basis. This supply should be decoupled to AGND. 5 REF OUT Reference Out. The output voltage from this pin is 2.5 V ± 1%. 6 VIN

Analog Input. Single-ended analog input channel. The input range is 0 V to REFIN. The analog input presents

a high dc input impedance. 7 AGND

Analog Ground. Ground reference point for all analog circuitry on the AD7492. All analog input signals

should be referred to this AGND voltage. The AGND and DGND voltages should ideally be at the same

potential and must not be more than 0.3 V apart, even on a transient basis. 8

CS Chip Select. Active low logic input used in conjunction with RD to access the conversion result. The

conversion result is placed on the data bus following the falling edge of both

connected to the same AND gate on the input so the signals are interchangeable.

permanently low. 9

RD Read Input. Logic input used in conjunction with CS to access the conversion result. The conversion result is

placed on the data bus following the falling edge of both

CS and RD. CS and RD are both connected to the same AND gate on the input so the signals are interchangeable. low, in which case the data bus is always active and the result of the new conversion is clocked out slightly

before to the BUSY line going low.

10

CONVST Conversion Start Input. Logic input used to initiate conversion. The input track/hold amplifier goes from track

mode to hold mode on the falling edge of conversion input can be as narrow as 10 ns. If the

CONVST and the conversion process is initiated at this point. The

CONVST input is kept low for the duration of conversion and is still low at the end of conversion, the part automatically enters a sleep mode. The type of sleep mode is determined by the PS/

FS pin. If the part enters a sleep mode, the next rising edge of CONVST wakes up the

part. Wake-up time depends on the type of sleep mode.

11

FS Partial Sleep/Full Sleep Mode. This pin determines the type of sleep mode the part enters if the CONVST pin is

PS/

kept low for the duration of the conversion and is still low at the end of conversion. In partial sleep mode the internal reference circuit and oscillator circuit are not powered down and draws 250 μA maximum. In full sleep mode all of the analog circuitry are powered down and the current drawn is negligible. This pin is

12 BUSY

hardwired either high (DV BUSY Output. Logic output indicating the status of the conversion process. The BUSY signal goes high after

the falling edge of

CONVST and stays high for the duration of the conversion. Once the conversion is

) or low (GND).

DD

complete and the conversion result is in the output register, the BUSY line returns low. The track/hold returns to track mode just prior to the falling edge of BUSY and the acquisition time for the part begins when BUSY goes low. If the

CONVST input is still low when BUSY goes low, the part automatically enters its sleep mode

on the falling edge of BUSY.

19 DGND

Digital Ground. This is the ground reference point for all digital circuitry on the AD7492. The DGND and AGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis.

CS and RD. CS and RD are both

CS can be hardwired

CS and RD can be hardwired permanently

Rev. A | Page 8 of 24

ANALOG DEVICES AD7492 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

AD7492-5

AD7492/AD7492-4

TIMING SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS