Analog Devices AD7492 Datasheet

1.25 MSPS, 16 mW Internal REF and CLK,

a

FEATURES
Specified for V
Throughput Rate of 1 MSPS—AD7492
Throughput Rate of 1.25 MSPS—AD7492-5
Low Power

4 mW Typ at 1 MSPS with 3 V Supplies
11 mW Typ at 1 MSPS with 5 V Supplies

Wide Input Bandwidth

70 dB Typ SNR at 100 kHz Input Frequency

2.5 V Internal Reference
On-Chip CLK Oscillator
Flexible Power/Throughput Rate Management
No Pipeline Delays
High-Speed Parallel Interface
Sleep Mode: 50
24-Lead SOIC and TSSOP Packages

GENERAL DESCRIPTION

The AD7492 and AD7492-5 are 12-bit high-speed, low power,
successive-approximation ADCs. The parts operate from a
single 2.7 V to 5.25 V power supply and feature throughput rates
up to 1.25 MSPS. They contain a low-noise, wide bandwidth
track/hold amplifier that can handle bandwidths up to 10 MHz.

The conversion process and data acquisition are controlled using
standard control inputs allowing easy interface to microproces­sors or DSPs. The input signal is sampled on the falling edge of
CONVST and conversion is also initiated at this point. The
BUSY goes high at the start of conversion and goes low 880 ns
(AD7492) or 680 ns (AD7492-5) later to indicate that the con­version is complete. There are no pipeline delays associated with
the part. The conversion result is accessed via standard CS and
RD signals over a high-speed parallel interface.

The AD7492 uses advanced design techniques to achieve very
low power dissipation at high throughput rates. With 5 V
supplies and 1.25 MSPS, the average current consumption
AD7492-5 is typically 2.75 mA. The part also offers flexible
power/throughput rate management.

It is also possible to operate the part in a full sleep mode and a
partial sleep mode, where the part wakes up to do a conversion
and automatically enters a sleep mode at the end of conversion.
The type of sleep mode is hardware selected by the PS/FS pin.
Using these sleep modes allows very low power dissipation num­bers at lower throughput rates.

The analog input range for the part is 0 to REF IN. The 2.5 V
reference is supplied internally and is available for external refer­encing. The conversion rate is determined by the internal clock.

of 2.7 V to 5.25 V

DD

nA Typ

12-Bit Parallel ADC

AD7492

FUNCTIONAL BLOCK DIAGRAM

AVDD

DVDD

REF OUT

2.5V
REF

BUF

VIN

CONVST

PRODUCT HIGHLIGHTS

T/H

AD7492

AGND DGND

12-BIT SAR

ADC

CONTROL

LOGIC

OSCILLATOR

1. High Throughput with Low Power Consumption
The AD7492-5 offers 1.25 MSPS throughput with 16 mW
power consumption.

2. Flexible Power/Throughput Rate Management
The conversion time is determined by an internal clock. The
part also features two sleep modes, partial and full, to maxi­mize power efficiency at lower throughput rates.

3. No Pipeline Delay
The part features a standard successive-approximation ADC
with accurate control of the sampling instant via a CONVST
input and once-off conversion control.

4. Flexible Digital Interface
The V

feature controls the voltage levels on the I/O

DRIVE

digital pins.

5. Fewer Peripheral Components
The AD7492 optimizes PCB space by using an internal
Reference and internal CLK.

CLOCK

VDRIVE

OUTPUT

DRIVERS

DB11

DB0

PS/FS

CS

RD

BUSY

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 2001

AD7492

1

AD7492-5–SPECIFICATIONS

Parameter A Version

1

(VDD = 4.75 V to 5.25 V, TA = T

B Version

1

DYNAMIC PERFORMANCE fS = 1.25 MSPS

Signal to Noise + Distortion (SINAD) 69 69 dB typ f

68 68 dB min f

Signal-to-Noise Ratio (SNR) 70 70 dB typ fIN = 500 kHz Sine Wave

68 68 dB min fIN = 100 kHz Sine Wave

Total Harmonic Distortion (THD) –83 –83 dB typ fIN = 500 kHz Sine Wave

–87 –87 dB typ fIN = 100 kHz Sine Wave
–75 –75 dB max fIN = 100 kHz Sine Wave

Peak Harmonic or Spurious Noise (SFDR) –83 –83 dB typ fIN = 500 kHz Sine Wave

–90 –90 dB typ fIN = 100 kHz Sine Wave
–76 –76 dB max fIN = 100 kHz Sine Wave

Intermodulation Distortion (IMD)

Second Order Terms –82 –82 dB typ fIN = 500 kHz Sine Wave

–90 –90 dB typ fIN = 100 kHz Sine Wave

Third Order Terms –71 –71 dB typ fIN = 500 kHz Sine Wave

–88 –88 dB typ fIN = 100 kHz Sine Wave
Aperture Delay 5 5 ns typ
Aperture Jitter 15 15 ps typ
Full Power Bandwidth 10 10 MHz typ

DC ACCURACY fS = 1.25 MSPS

Resolution 12 12 Bits
Integral Nonlinearity ± 1.5 ± 1.25 LSB max
Differential Nonlinearity +1.5/–0.9 +1.5/–0.9 LSB max Guaranteed No Missed Codes to

Offset Error ± 9 ± 9 LSB max
Gain Error ± 2.5 ± 2.5 LSB max

ANALOG INPUT

Input Voltage Ranges 0 to 2.5 0 to 2.5 V
DC Leakage Current ± 1 ± 1 µA max
Input Capacitance 33 33 pF typ

REFERENCE OUTPUT

REF OUT Output Voltage Range 2.5 2.5 V ± 1.5% for Specified Performance

LOGIC INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I

IN

Input Capacitance, C

INL

IN

INH

2

2

3

V

× 0.7 V

DRIVE

V

× 0.3 V

DRIVE

× 0.7 V min VDD = 5 V ± 5%

DRIVE

× 0.3 V max VDD = 5 V ± 5%

DRIVE

± 1 ± 1 µA max Typically 10 nA, VIN = 0 V or V

10 10 pF max

LOGIC OUTPUTS

Output High Voltage, V
Output Low Voltage, V

OL

OH

V

– 0.2 V

DRIVE

– 0.2 V min I

DRIVE

0.4 0.4 V max I
Floating-State Leakage Current ± 10 ± 10 µA max
Floating-State Output Capacitance 10 10 pF max
Output Coding Straight (Natural) Binary Straight (Natural) Binary

CONVERSION RATE

Conversion Time 680 680 ns max
Track/Hold Acquisition Time 120 120 ns min
Throughput Rate 1.25 1.25 MSPS max Conversion Time + Acquisition Time

POWER REQUIREMENTS

V

DD

I

DD

4.75/5.25 4.75/5.25 V min/max

Normal Mode 3.3 3.3 mA max fS = 1.25 MSPS, Typ 2.75 mA
Quiescent Current 1.8 1.8 mA max
Partial Sleep Mode 250 250 µA max Static. Typ 190 µA
Full Sleep Mode 1 1 µA max Static. Typ 200 nA

Power Dissipation

4

Normal Mode 16.5 16.5 mW max
Partial Sleep Mode 1.25 1.25 mW max
Full Sleep Mode 5 5 µW max

NOTES

1

Temperature ranges as follows: A and B Versions: –40°C to +85°C.

2

V

and V

INH

3

Sample tested @ 25°C to ensure compliance.

4

See Power vs. Throughput Rate section.

Specifications subject to change without notice.

trigger levels are set by the V

INL

voltage. The logic interface circuitry is powered by V

DRIVE

DRIVE

–2–

to T

MIN

, unless otherwise noted.)

MAX

Unit Test Conditions/Comments

= 500 kHz Sine Wave

IN

= 100 kHz Sine Wave

IN

12 Bits (A and B Version)

= 200 µA

SOURCE

= 200 µA

SINK

Digital I/Ps = 0 V or DV

Digital I/Ps = 0 V or DV

.

DD.

DD

REV. 0

DD

AD7492

AD7492–SPECIFICATIONS

Parameter A Version

1

(VDD = 2.7 V to 5.25 V, TA = T

1

B Version

to T

MIN

1

, unless otherwise noted.)

MAX

Unit Test Conditions/Comments

DYNAMIC PERFORMANCE fS = 1 MSPS

Signal to Noise + Distortion (SINAD) 69 69 dB typ fIN = 500 kHz Sine Wave

68 68 dB min fIN = 100 kHz Sine Wave

Signal-to-Noise Ratio (SNR) 70 70 dB typ f

68 68 dB min f

Total Harmonic Distortion (THD) –85 –85 dB typ f

–87 –87 dB typ f

= 500 kHz Sine Wave

IN

= 100 kHz Sine Wave

IN

= 500 kHz Sine Wave

IN

= 100 kHz Sine Wave

IN

–75 –75 dB max fIN = 100 kHz Sine Wave

Peak Harmonic or Spurious Noise (SFDR) –86 –86 dB typ f

–90 –90 dB typ f

= 500 kHz Sine Wave

IN

= 100 kHz Sine Wave

IN

–76 –76 dB max fIN = 100 kHz Sine Wave

Intermodulation Distortion (IMD)

Second Order Terms –77 –77 dB typ f

–90 –90 dB typ f

= 500 kHz Sine Wave

IN

= 100 kHz Sine Wave

IN

Third Order Terms –69 –69 dB typ fIN = 500 kHz Sine Wave

–88 –88 dB typ fIN = 100 kHz Sine Wave
Aperture Delay 5 5 ns typ
Aperture Jitter 15 15 ps typ
Full Power Bandwidth 10 10 MHz typ

DC ACCURACY f

= 1 MSPS

S

Resolution 12 12 Bits
Integral Nonlinearity ± 1.5 LSB max

± 0.6 LSB typ VDD = 5 V
± 1 LSB max VDD = 3 V

Differential Nonlinearity +1.5/–0.9 +1.5/–0.9 LSB max Guaranteed No Missed Codes to

12 Bits (A and B Version)
Offset Error ± 9 ± 9 LSB max
Gain Error ± 2.5 ± 2.5 LSB max

ANALOG INPUT

Input Voltage Ranges 0 to 2.5 0 to 2.5 V
DC Leakage Current ± 1 ± 1 µA max
Input Capacitance 33 33 pF typ

REFERENCE OUTPUT

REF OUT Output Voltage Range 2.5 2.5 V ± 1.5% for Specified Performance

LOGIC INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I

IN

Input Capacitance, C

INL

IN

INH

2

2

3

V

× 0.7 V

DRIVE

V

× 0.3 V

DRIVE

× 0.7 V min VDD = 5 V ± 5%

DRIVE

× 0.3 V max VDD = 5 V ± 5%

DRIVE

± 1 ± 1 µA max Typically 10 nA, VIN = 0 V or V
10 10 pF max

LOGIC OUTPUTS

Output High Voltage, V
Output Low Voltage, V

OL

OH

V

– 0.2 V

DRIVE

– 0.2 V min I

DRIVE

0.4 0.4 V max I

SOURCE

= 200 µA

SINK

= 200 µA

Floating-State Leakage Current ± 10 ± 10 µA max
Floating-State Output Capacitance 10 10 pF max
Output Coding Straight (Natural) Binary Straight (Natural) Binary

CONVERSION RATE

Conversion Time 880 880 ns max
Track/Hold Acquisition Time 120 120 ns min
Throughput Rate 1 1 MSPS max Conversion Time + Acquisition Time

POWER REQUIREMENTS

V

DD

I

DD

2.7/5.25 2.7/5.25 V min/max
Digital I/Ps = 0 V or DV

DD.

Normal Mode 3 3 mA max fS = 1 MSPS, Typ 2.2 mA
Quiescent Current 1.8 1.8 mA max
Partial Sleep Mode 250 250 µA max Static. Typ 190 µA
Full Sleep Mode 1 1 µA max Static. Typ 200 nA

Power Dissipation

4

Digital I/Ps = 0 V or DV

DD

Normal Mode 15 15 mW max VDD = 5 V
Partial Sleep Mode 1.25 1.25 mW max VDD = 5 V
Full Sleep Mode 5 5 µW max VDD = 5 V

NOTES

1

Temperature ranges as follows: A and B Versions: –40°C to +85°C.

2

V

and V

INH

3

Sample tested @ 25°C to ensure compliance.

4

See Power vs. Throughput Rate section.

Specifications subject to change without notice.

trigger levels are set by the V

INL

voltage. The logic interface circuitry is powered by V

DRIVE

DRIVE

.

DD

REV. 0

–3–

AD7492

TIMING SPECIFICATIONS

1

(VDD = 2.7 V to 5.25 V, TA = T

MIN

to T

, unless otherwise noted.)

MAX

Limit at T

Parameter AD7492 AD7492-5

t

CONVERT

t

WAKEUP

880 680 ns max

3

20

MIN

, T

MAX

20

2

3

Unit Description

µs max Partial Sleep Wake-Up Time

500 500 µs max Full Sleep Wake-Up Time

t

1

t

2

t

3

4

t

4

t

5

4

t

6

5

t

7

t

8

t

9

t

10

NOTES

1

Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. See
Figure 1.

2

The AD7492-5 is specified with VDD = 4.75 V to 5.25 V.

3

This is the time needed for the part to settle within 0.5 LSB of its stable value. Conversion can be initiated earlier than 20 µs, but we cannot guarantee that the part
will sample within 0.5 LSB of the true analog input value. Therefore we recommend that the user does not start conversion until after the specified time.

4

Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.0 V.

5

t7 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
time of the part and is independent of the bus loading.

Specifications subject to change without notice.

10 10 ns min CONVST Pulsewidth
10 10 ns max CONVST to BUSY Delay, VDD = 5 V
40 N/A ns max CONVST to BUSY Delay, V

DD

= 3 V

0 0 ns max BUSY to CS Setup Time
0 0 ns max CS to RD Setup Time
20 20 ns min RD Pulsewidth
15 15 ns min Data Access Time after Falling Edge of RD
8 8 ns max Bus Relinquish Time after Rising Edge of RD
0 0 ns max CS to RD Hold Time
120 120 ns min Acquisition Time
100 100 ns min Quiet Time

, quoted in the timing characteristics is the true bus relinquish

7

TO OUTPUT

PIN

50pF

200␮A

C

L

200␮A

I

OL

1.6V

I

OH

Figure 1. Load Circuit for Digital Output Timing Specifications

–4–

REV. 0

AD7492

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS

1

(TA = 25°C unless otherwise noted)

AVDD to AGND/DGND . . . . . . . . . . . . . . . . . –0.3 V to +7 V

DV

to AGND/DGND . . . . . . . . . . . . . . . . . –0.3 V to +7 V

DD

V

to AGND/DGND . . . . . . . . . . . . . . . . –0.3 V to +7 V

DRIVE

to DVDD . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +0.3 V

AV

DD

V

to DVDD . . . . . . . . . . . . . . . . –0.3 V to DVDD + 0.3 V

DRIVE

AGND TO DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

Analog Input Voltage to AGND . . . –0.3 V to AVDD + 0.3 V
Digital Input Voltage to DGND . . . –0.3 V to DVDD + 0.3 V
Input Current to Any Pin Except Supplies

2

. . . . . . . ± 10 mA

Operating Temperature Range

Commercial (A and B Versions) . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C

SOIC, TSSOP Package Dissipation . . . . . . . . . . . . . . 450 mW

Thermal Impedance . . . . . . . . . . . . . . . 75°C/W (SOIC)

θ

JA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C/W (TSSOP)

Thermal Impedance . . . . . . . . . . . . . . . 25°C/W (SOIC)

θ

JC

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35°C/W (TSSOP)

Lead Temperature, Soldering

Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . . 215°C

Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi­tions for extended periods may affect device reliability.

2

Transient currents of up to 100 mA will not cause SCR latch-up.

PIN CONFIGURATION

1

DB9 DB8

2

DB10 DB7

(MSB) DB11 DB6

REF OUT

CONVST

3

4

AV

DD

5

AD7492

6

V

IN

TOP VIEW

(Not to Scale)

7

AGND DB5

8

CS

9

RD

10

11

PS/FS

BUSY DB0 (LSB)

12

24

23

22

21

V

DRIVE

20

DV

19

DGND

18

DB4

17

16

DB3

15

DB2

14

DB1

13

DD

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7492 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

ORDERING GUIDE

Temperature Resolution Throughput Rate Package Package

Model Range (Bits) (MSPS) Description Option

AD7492AR –40°C to +85°C 12 1 SOIC R-24
AD7492ARU –40°C to +85°C 12 1 TSSOP RU-24
AD7492BR –40°C to +85°C 12 1 SOIC R-24
AD7492BRU –40°C to +85°C 12 1 TSSOP RU-24
AD7492AR-5 –40°C to +85°C 12 1.25 SOIC R-24
AD7492ARU-5 –40°C to +85°C 12 1.25 TSSOP RU-24
AD7492BR-5 –40°C to +85°C 12 1.25 SOIC R-24
AD7492BRU-5 –40°C to +85°C 12 1.25 TSSOP RU-24
EVAL-AD7492CB
EVAL-CONTROL BRD2

NOTES

1

R = SOIC; RU = TSSOP.

2

This can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD2 for evaluation/demonstration purposes.

3

This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.

2

3

Evaluation Board
Controller Board

1

REV. 0

–5–